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RE: [PATCH] MIPS EVA ASE Support

From: "Moore, Catherine" <Catherine_Moore at mentor dot com>
To: Richard Sandiford <rdsandiford at googlemail dot com>
Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>, "Moore, Catherine" <Catherine_Moore at mentor dot com>
Date: Mon, 10 Jun 2013 18:34:55 +0000
Subject: RE: [PATCH] MIPS EVA ASE Support
References: <FD3DCEAC5B03E9408544A1E416F11242F8FC6EE7 at NA-MBX-01 dot mgc dot mentorg dot com> <87fvwz9hsg dot fsf at talisman dot default> <FD3DCEAC5B03E9408544A1E416F11242F8FC9639 at NA-MBX-01 dot mgc dot mentorg dot com> <87bo7g99yn dot fsf at talisman dot default>
Hi Richard,

> -----Original Message-----
> From: Richard Sandiford [mailto:rdsandiford@googlemail.com]
> Sent: Saturday, June 08, 2013 6:24 AM
> To: Moore, Catherine
> Cc: binutils@sourceware.org
> Subject: Re: [PATCH] MIPS EVA ASE Support
> 
> "Moore, Catherine" <Catherine_Moore@mentor.com> writes:
> > The MIPS opcode table now has a new ASE field and I've updated the
> > pertinent bits of gas and opcodes to use the new field.
> > This is an invasive patch.  What do you recommend for testing?  I've
> > got clean results for mips-elf and mips64-linux.  I will post the MIPS
> > EVA support once you have approved this infrastructure change.
> 
> Yeah, that's quite the patch.  Thanks for doing this.  The opcode table
> changes were pretty much impossible to review manually, so I opted for
> review by script instead.  This threw up the changes below.  Some of them
> are just minor formatting tweaks: the IOCT|IOCTP|IOCT2 lines are removing
> an excess tab that was carried over from the original, the SMT lines are using
> a tab rather than a space, and the IL2F|IL3A lines are to avoid whitespace
> changes on lines that don't need to be touched.  I think the rest are real fixes
> though.  Still, if you wrote the changes by hand, the number of differences is
> impressively small :-)
> 
I did make the modifications by hand.  I have to say, though,  that the completeness of the gas testsuite really helped with sorting this out.  The few bits that needed to be modified are likely not covered in the testsuite.  Another project?

> The bits outside opcode tables look good.
> 
> I've applied the patch with these changes and with a minor tweak to the
> mips-dis.c formatting of the mips32r2 and mips64r2 entries.
> 

Thank you for fixing and committing the patch.

I have attached the updated patch for EVA opcode support.  Okay?
Catherine

> 
> 
> Index: opcodes/micromips-opc.c
> ==========================================================
> =========
> --- opcodes/micromips-opc.c	2013-06-08 10:18:33.894842596 +0100
> +++ opcodes/micromips-opc.c	2013-06-08 10:18:44.227957964 +0100
> @@ -115,7 +115,7 @@ const struct mips_opcode micromips_opcod
>  /* These instructions appear first so that the disassembler will find
>     them first.  The assemblers uses a hash table based on the
>     instruction name anyhow.  */
> -/* name,    args,	match,      mask,	pinfo,
> 	pinfo2,		membership,	[exclusions] */
> +/* name,    args,	match,      mask,	pinfo,
> 	pinfo2,		membership,	[ase],	[exclusions] */
>  {"pref",    "k,~(b)",	0x60002000, 0xfc00f000,	RD_b,
> 	0,		I1	},
>  {"pref",    "k,o(b)",	0,    (int) M_PREF_OB,	INSN_MACRO,		0,
> 		I1	},
>  {"pref",    "k,A(b)",	0,    (int) M_PREF_AB,	INSN_MACRO,		0,
> 		I1	},
> @@ -658,7 +658,7 @@ const struct mips_opcode micromips_opcod
>  {"flush",   "t,A(b)",	0,    (int) M_LWR_AB,	INSN_MACRO,		0,
> 		I1	},
>  {"lwxs",    "d,t(b)",	0x00000118, 0xfc0007ff,	RD_b|RD_t|WR_d,
> 		0,		I1	},
>  {"madd",    "s,t",	0x0000cb3c, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,
> 	0,		I1	},
> -{"madd",    "7,s,t",	0x00000abc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,
> 		D32	},
> +{"madd",    "7,s,t",	0x00000abc, 0xfc003fff,	MOD_a|RD_s|RD_t,	0,
> 		0,	D32	},
>  {"madd.d",  "D,R,S,T",	0x54000009, 0xfc00003f,
> 	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1	},
>  {"madd.s",  "D,R,S,T",	0x54000001, 0xfc00003f,
> 	RD_R|RD_S|RD_T|WR_D|FP_S, 0,		I1	},
>  {"madd.ps", "D,R,S,T",	0x54000011, 0xfc00003f,
> 	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1	},
> Index: opcodes/mips-opc.c
> ==========================================================
> =========
> --- opcodes/mips-opc.c	2013-06-08 10:18:33.897842630 +0100
> +++ opcodes/mips-opc.c	2013-06-08 10:18:42.035933491 +0100
> @@ -314,7 +314,7 @@ const struct mips_opcode mips_builtin_op
>  {"adda.s",  "V,T",	0x46000018, 0xffe007ff,	RD_S|RD_T|FP_S,
> 		0,		EE	},
>  {"addi",    "t,r,j",	0x20000000, 0xfc000000,	WR_t|RD_s,
> 	0,		I1	},
>  {"addiu",   "t,r,j",	0x24000000, 0xfc000000,	WR_t|RD_s,
> 	0,		I1	},
> -{"addl.ob", "Y,Q",	0x78000437, 0xfc2007ff,	RD_S|RD_T|FP_D,
> 		WR_MACC,	SB1,	MX,	},
> +{"addl.ob", "Y,Q",	0x78000437, 0xfc2007ff,	RD_S|RD_T|FP_D,
> 		WR_MACC,	SB1,	MX	},
>  {"addl.qh", "Y,Q",	0x78200437, 0xfc2007ff,	RD_S|RD_T|FP_D,
> 		WR_MACC,	0,	MX	},
>  {"addr.ps", "D,S,T",	0x46c00018, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		0,	M3D	},
>  {"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,
> 		0,		I1	},
> @@ -432,7 +432,7 @@ const struct mips_opcode mips_builtin_op
>  {"c.f.ps",  "M,S,T",	0x46c00030, 0xffe000ff,
> 	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33	},
>  {"c.un.d",  "S,T",	0x46200031, 0xffe007ff,
> 	RD_S|RD_T|WR_CC|FP_D,	0,		I1,	0,	SF
> 	},
>  {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,
> 		I4_32	},
> -{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,
> 		I1,	EE	},
> +{"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,
> 		I1,	0,	EE	},
>  {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,
> 		I4_32	},
>  {"c.un.ps", "S,T",	0x46c00031, 0xffe007ff,
> 	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F	},
>  {"c.un.ps", "S,T",	0x45600031, 0xffe007ff,
> 	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E	},
> @@ -717,7 +717,7 @@ const struct mips_opcode mips_builtin_op
>  {"dmaccu",  "d,s,t",	0x00000069, 0xfc0007ff,
> 	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
>  {"dmaccus", "d,s,t",	0x00000469, 0xfc0007ff,
> 	RD_s|RD_t|WR_LO|WR_d,	0,		N412	},
>  {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,
> 		N411    },
> -{"dmfc0",   "t,G",	0x40200000, 0xffe007ff,	LCD|WR_t|RD_C0,
> 		0,		I3,	EE	},
> +{"dmfc0",   "t,G",	0x40200000, 0xffe007ff,	LCD|WR_t|RD_C0,
> 		0,		I3,	0,	EE	},
>  {"dmfc0",   "t,+D",	0x40200000, 0xffe007f8,	LCD|WR_t|RD_C0,
> 		0,		I64	},
>  {"dmfc0",   "t,G,H",	0x40200000, 0xffe007f8,	LCD|WR_t|RD_C0,
> 		0,		I64	},
>  {"dmfgc0",   "t,G",	0x40600100, 0xffe007ff, LCD|WR_t|RD_C0,
> 	0,		0,	IVIRT64	},
> @@ -725,7 +725,7 @@ const struct mips_opcode mips_builtin_op
>  {"dmfgc0",   "t,G,H",	0x40600100, 0xffe007f8, LCD|WR_t|RD_C0, 	0,
> 		0,	IVIRT64	},
>  {"dmt",     "",		0x41600bc1, 0xffffffff, TRAP,			0,
> 		0,	MT32	},
>  {"dmt",     "t",	0x41600bc1, 0xffe0ffff, TRAP|WR_t,		0,
> 	0,	MT32	},
> -{"dmtc0",   "t,G",	0x40a00000, 0xffe007ff,
> 	COD|RD_t|WR_C0|WR_CC,	0,		I3,	EE	},
> +{"dmtc0",   "t,G",	0x40a00000, 0xffe007ff,
> 	COD|RD_t|WR_C0|WR_CC,	0,		I3,	0,	EE
> 	},
>  {"dmtc0",   "t,+D",	0x40a00000, 0xffe007f8,
> 	COD|RD_t|WR_C0|WR_CC,	0,		I64	},
>  {"dmtc0",   "t,G,H",	0x40a00000, 0xffe007f8,
> 	COD|RD_t|WR_C0|WR_CC,	0,		I64	},
>  {"dmtgc0",  "t,G",	0x40600300, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,
> 	0,		0,	IVIRT64	},
> @@ -740,23 +740,23 @@ const struct mips_opcode mips_builtin_op
>  /* dmfc3 is at the bottom of the table.  */
>  /* dmtc3 is at the bottom of the table.  */
>  {"dmul",    "d,v,t",	0x70000003, 0xfc0007ff,
> WR_d|RD_s|RD_t|WR_HILO,	0,		IOCT	},
> -{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,
> 	0,		I3,	M32	},
> -{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 	I3,	M32	},
> -{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	M32	},
> +{"dmul",    "d,v,t",	0,    (int) M_DMUL,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dmul",    "d,v,I",	0,    (int) M_DMUL_I,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dmulo",   "d,v,t",	0,    (int) M_DMULO,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dmulo",   "d,v,I",	0,    (int) M_DMULO_I,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dmulou",  "d,v,t",	0,    (int) M_DMULOU,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dmulou",  "d,v,I",	0,    (int) M_DMULOU_I,	INSN_MACRO,
> 	0,		I3,	0,	M32	},
> +{"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	0,	M32	},
> +{"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	0,	M32	},
>  {"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,
> 	0,		I3	}, /* dsub 0 */
>  {"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,		0,
> 		I3	}, /* dsubu 0*/
>  {"dpop",    "d,v",	0x7000002d, 0xfc1f07ff, WR_d|RD_s,		0,
> 		IOCT	},
> -{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	M32	},
> -{"drem",    "d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"drem",    "d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	M32	},
> -{"dremu",   "d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,
> 		I3,	M32	},
> -{"dremu",   "d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,
> 	0,		I3,	M32	},
> +{"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	0,	M32	},
> +{"drem",    "d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"drem",    "d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,
> 		I3,	0,	M32	},
> +{"dremu",   "d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,
> 		I3,	0,	M32	},
> +{"dremu",   "d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,
> 	0,		I3,	0,	M32	},
>  {"dret",    "",		0x7000003e, 0xffffffff,	0,			0,
> 		N5	},
>  {"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,
> 		I3	},
>  {"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,
> 		I3	},
> @@ -816,7 +816,7 @@ const struct mips_opcode mips_builtin_op
>  {"exts",    "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s,		0,
> 		IOCT	},
>  {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		I3_33	},
>  {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,
> 	0,		I3_33	},
> -{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,
> 	0,		I2,	SF	},
> +{"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,
> 	0,		I2,	0,	SF	},
>  {"floor.w.s", "D,S",	0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,
> 	0,		I2	},
>  {"hibernate","",        0x42000023, 0xffffffff,	0, 			0,
> 		V1	},
>  {"hypcall", "",		0x42000028, 0xffffffff, TRAP,			0,
> 		0,	IVIRT	},
> @@ -1106,7 +1106,7 @@ const struct mips_opcode mips_builtin_op
>  {"msuba.s", "S,T",	0x4600001f, 0xffe007ff,	RD_S|RD_T|FP_S,
> 	0,		EE	},
>  {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,
> 		L1	},
>  {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,
> 		I32|N55	},
> -{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,
> D32	},
> +{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,
> 0,	D32	},
>  {"mtbpc",   "t",	0x4080c000, 0xffe0ffff,	COD|RD_t|WR_C0,		0,
> 		EE	},
>  {"mtdab",   "t",	0x4080c004, 0xffe0ffff,	COD|RD_t|WR_C0,		0,
> 		EE	},
>  {"mtdabm",  "t",	0x4080c005, 0xffe0ffff,	COD|RD_t|WR_C0,
> 	0,		EE	},
> @@ -1152,20 +1152,20 @@ const struct mips_opcode mips_builtin_op
>  {"mttc0",   "t,G,H",	0x41800000, 0xffe007f8,
> TRAP|COD|RD_t|WR_C0|WR_CC, 0,		0,	MT32	},
>  {"mttc1",   "t,S",	0x41800022, 0xffe007ff,
> TRAP|COD|RD_t|WR_S|FP_S, 0,		0,	MT32	},
>  {"mttc1",   "t,G",	0x41800022, 0xffe007ff,
> TRAP|COD|RD_t|WR_S|FP_S, 0,		0,	MT32	},
> -{"mttc2",   "t,g",	0x41800024, 0xffe007ff,
> 	TRAP|COD|RD_t|WR_C2|WR_CC, 0,		0,	MT32,
> 	IOCT|IOCTP|IOCT2	},
> +{"mttc2",   "t,g",	0x41800024, 0xffe007ff,
> 	TRAP|COD|RD_t|WR_C2|WR_CC, 0,		0,	MT32,
> 	IOCT|IOCTP|IOCT2	},
>  {"mttacx",  "t",	0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,
> 		0,	MT32	},
>  {"mttacx",  "t,&",	0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,
> 	0,		0,	MT32	},
>  {"mttdsp",  "t",	0x41808021, 0xffe0ffff, TRAP|RD_t,		0,
> 		0,	MT32	},
>  {"mttgpr",  "t,d",	0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,
> 	0,		0,	MT32	},
>  {"mtthc1",  "t,S",	0x41800032, 0xffe007ff,
> TRAP|COD|RD_t|WR_S|FP_D, 0,		0,	MT32	},
>  {"mtthc1",  "t,G",	0x41800032, 0xffe007ff,
> TRAP|COD|RD_t|WR_S|FP_D, 0,		0,	MT32	},
> -{"mtthc2",  "t,g",	0x41800034, 0xffe007ff,
> 	TRAP|COD|RD_t|WR_C2|WR_CC, 0,		0,	MT32,
> 	IOCT|IOCTP|IOCT2	},
> +{"mtthc2",  "t,g",	0x41800034, 0xffe007ff,
> 	TRAP|COD|RD_t|WR_C2|WR_CC, 0,		0,	MT32,
> 	IOCT|IOCTP|IOCT2	},
>  {"mtthi",   "t",	0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,		0,
> 		0,	MT32	},
>  {"mtthi",   "t,&",	0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,
> 	0,		0,	MT32	},
>  {"mttlo",   "t",	0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,		0,
> 		0,	MT32	},
>  {"mttlo",   "t,&",	0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,
> 	0,		0,	MT32	},
>  {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,		0,
> 		0,	MT32	},
> -{"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		I1,	SF	},
> +{"mul.d",   "D,V,T",	0x46200002, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		I1,	0,	SF
> 	},
>  {"mul.s",   "D,V,T",	0x46000002, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
>  {"mul.ob",  "X,Y,Q",	0x78000030, 0xfc20003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		SB1,	MX	},
>  {"mul.ob",  "D,S,T",	0x4ac00030, 0xffe0003f,	WR_D|RD_S|RD_T,
> 		0,		N54	},
> @@ -1410,14 +1410,14 @@ const struct mips_opcode mips_builtin_op
>  {"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,
> 		I1	},
>  {"ror",	    "d,w,<",	0x00200002, 0xffe0003f,	WR_d|RD_t,
> 	0,		N5|I33,	SMT },
>  {"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,
> 		0,		N5|I33,	SMT },
> -{"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,
> 		I33,	SMT },
> -{"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,
> 		I33,	SMT },
> -{"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,
> 		I33,	SMT },
> -{"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,
> 		I33,	SMT },
> -{"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,
> 		0,		I33,	SMT },
> +{"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		0,
> 		I33,	SMT	},
> +{"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		0,
> 		I33,	SMT	},
> +{"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		0,
> 		I33,	SMT	},
> +{"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		0,
> 		I33,	SMT	},
> +{"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,
> 		0,		I33,	SMT	},
>  {"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		I3_33	},
>  {"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,
> 	0,		I3_33	},
> -{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,
> 	0,		I2,	0,	SF },
> +{"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,
> 	0,		I2,	0,	SF	},
>  {"round.w.s", "D,S",	0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,
> 	0,		I2	},
>  {"rsqrt.d", "D,S",	0x46200016, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		I4_33	},
>  {"rsqrt.ps","D,S",	0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		SB1	},
> @@ -1539,7 +1539,7 @@ const struct mips_opcode mips_builtin_op
>  {"sq",      "t,A(b)",	0,    (int) M_SQ_AB,	INSN_MACRO,		0,
> 		MMI	},
>  {"sqc2",    "E,o(b)",	0xf8000000, 0xfc000000,	SM|RD_C2|RD_b,
> 		0,		EE	},
>  {"sqc2",    "E,A(b)",	0,    (int) M_SQC2_AB,	INSN_MACRO,		0,
> 		EE	},
> -{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		I2,	SF	},
> +{"sqrt.d",  "D,S",	0x46200004, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		I2,	0,	SF	},
>  {"sqrt.s",  "D,S",	0x46000004, 0xffff003f, WR_D|RD_S|FP_S,
> 	0,		I2	},
>  {"sqrt.ps", "D,S",	0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,
> 	0,		SB1	},
>  {"srav",    "d,t,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,
> 		0,		I1	},
> @@ -1563,7 +1563,7 @@ const struct mips_opcode mips_builtin_op
>  {"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,
> 		I1	},
>  {"sub",	"D,S,T",	0x45c00001,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
>  {"sub",	"D,S,T",	0x4b40000d,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
> -{"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		I1,	SF	},
> +{"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		I1,	0,	SF
> 	},
>  {"sub.s",   "D,V,T",	0x46000001, 0xffe0003f,
> 	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
>  {"sub.ob",  "X,Y,Q",	0x7800000a, 0xfc20003f,
> 	WR_D|RD_S|RD_T|FP_D,	0,		SB1,	MX	},
>  {"sub.ob",  "D,S,T",	0x4ac0000a, 0xffe0003f,	WR_D|RD_S|RD_T,
> 		0,		N54	},
> @@ -2227,8 +2227,8 @@ const struct mips_opcode mips_builtin_op
>  {"pminsh",	"D,S,T",	0x4b600008,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
>  {"pminub",	"D,S,T",	0x46e00000,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
>  {"pminub",	"D,S,T",	0x4ba00008,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
> -{"pmovmskb",	"D,S",		0x46a00005,	0xffff003f,
> 	RD_S|WR_D|FP_D,		0,	IL2E	},
> -{"pmovmskb",	"D,S",		0x4ba0000f,	0xffff003f,
> 	RD_S|WR_D|FP_D,		0,	IL2F|IL3A	},
> +{"pmovmskb",	"D,S",		0x46a00005,	0xffff003f,
> 	RD_S|WR_D|FP_D,	0,	IL2E	},
> +{"pmovmskb",	"D,S",		0x4ba0000f,	0xffff003f,
> 	RD_S|WR_D|FP_D,	0,	IL2F|IL3A	},
>  {"pmulhuh",	"D,S,T",	0x46e00002,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
>  {"pmulhuh",	"D,S,T",	0x4ba0000a,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
>  {"pmulhh",	"D,S,T",	0x46a00002,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
> @@ -2239,8 +2239,8 @@ const struct mips_opcode mips_builtin_op
>  {"pmuluw",	"D,S,T",	0x4b80000a,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
>  {"pasubub",	"D,S,T",	0x45a00001,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
>  {"pasubub",	"D,S,T",	0x4b20000d,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
> -{"biadd",	"D,S",		0x46800005,	0xffff003f,
> 	RD_S|WR_D|FP_D,		0,	IL2E	},
> -{"biadd",	"D,S",		0x4b80000f,	0xffff003f,
> 	RD_S|WR_D|FP_D,		0,	IL2F|IL3A	},
> +{"biadd",	"D,S",		0x46800005,	0xffff003f,
> 	RD_S|WR_D|FP_D,	0,	IL2E	},
> +{"biadd",	"D,S",		0x4b80000f,	0xffff003f,
> 	RD_S|WR_D|FP_D,	0,	IL2F|IL3A	},
>  {"pshufh",	"D,S,T",	0x47000002,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
>  {"pshufh",	"D,S,T",	0x4b000002,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
>  {"psllh",	"D,S,T",	0x46600002,	0xffe0003f,
> 	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
Attachment: eva.cl2
Description: eva.cl2
Attachment: eva.patch2
Description: eva.patch2
Follow-Ups:
- Re: [PATCH] MIPS EVA ASE Support
  - From: Richard Sandiford
References:
- [PATCH] MIPS EVA ASE Support
  - From: Moore, Catherine
- Re: [PATCH] MIPS EVA ASE Support
  - From: Richard Sandiford
- RE: [PATCH] MIPS EVA ASE Support
  - From: Moore, Catherine
- Re: [PATCH] MIPS EVA ASE Support
  - From: Richard Sandiford
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