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RE: [MIPS] Add new virtualization instructions

From: Chao-Ying Fu <Chao-Ying dot Fu at imgtec dot com>
To: "'Pinski, Andrew'" <Andrew dot Pinski at caviumnetworks dot com>, 'Richard Sandiford' <rdsandiford at googlemail dot com>
Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>
Date: Wed, 12 Jun 2013 23:48:07 +0000
Subject: RE: [MIPS] Add new virtualization instructions
References: <e790fa722ba34ff097a964d1dfa06e9d at BY2PR07MB058 dot namprd07 dot prod dot outlook dot com> <87wqr81o3b dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com> <98cba9069a7141f399456267fe33b95f at BY2PR07MB058 dot namprd07 dot prod dot outlook dot com> <87d2szptbr dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com>,<81D57523CB07B24881D63DE650C6ED82EDBB9B at bamail02 dot ba dot imgtec dot org> <bd8d0ebef46949869722652cd2cab2d1 at BY2PR07MB058 dot namprd07 dot prod dot outlook dot com>

Pinski, Andrew wrote:
> 
> No I don't plan on submitting the microMIPS virtualization 
> instructions support as I could not even find the 
> specifications for the microMIPS part.
> 

  Thanks for your finding.  We have asked our IT people to upload the microMIPS version.
Before the spec is posted, here is the patch to add microMIPS virtualization opcodes.

gas/ChangLog
2013-06-12  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>

	* config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips.

gas/testsuite/ChangLog
2013-06-12  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>

	* gas/mips/micromips@virt.d: New file.
	gas/mips/micromips@virt64.d: New file.
	gas/mips/mips.exp: Change micromips to use -march=mips64r2, as the virt64 test needs it.
	Enable virt and virt64 tests for micromips.

opcodes/ChangeLog
2013-06-12  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>

	* micromips-opc.c (IVIRT): New define.
	(IVIRT64): New define.
	(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.

	* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0, dmtgc0
	to print cp0 names.

Index: gas/testsuite/gas/mips/micromips@virt.d
===================================================================
RCS file: gas/testsuite/gas/mips/micromips@virt.d
diff -N gas/testsuite/gas/mips/micromips@virt.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/micromips@virt.d	12 Jun 2013 23:10:06 -0000
@@ -0,0 +1,21 @@
+#objdump: -dr --prefix-addresses  --show-raw-insn -Mvirt,cp0-names=mips32r2
+#name: virt instructions
+#source: virt.s
+#as: -32 -mvirt
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 007d 04fc 	mfgc0	v1,c0_taghi
+[0-9a-f]+ <[^>]*> 0174 2cfc 	mfgc0	t3,\$20,5
+[0-9a-f]+ <[^>]*> 02e2 06fc 	mtgc0	s7,c0_entrylo0
+[0-9a-f]+ <[^>]*> 00ee 16fc 	mtgc0	a3,\$14,2
+[0-9a-f]+ <[^>]*> 0000 c37c 	hypcall
+[0-9a-f]+ <[^>]*> 0256 c37c 	hypcall	0x256
+[0-9a-f]+ <[^>]*> 0000 417c 	tlbginv
+[0-9a-f]+ <[^>]*> 0000 517c 	tlbginvf
+[0-9a-f]+ <[^>]*> 0000 017c 	tlbgp
+[0-9a-f]+ <[^>]*> 0000 117c 	tlbgr
+[0-9a-f]+ <[^>]*> 0000 217c 	tlbgwi
+[0-9a-f]+ <[^>]*> 0000 317c 	tlbgwr
+	...
Index: gas/testsuite/gas/mips/micromips@virt64.d
===================================================================
RCS file: gas/testsuite/gas/mips/micromips@virt64.d
diff -N gas/testsuite/gas/mips/micromips@virt64.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/micromips@virt64.d	12 Jun 2013 23:10:06 -0000
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses  --show-raw-insn -Mvirt,cp0-names=mips64r2
+#name: virt64 instructions
+#source: virt64.s
+#as: -64 -mvirt
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 587d 00e7 	dmfgc0	v1,c0_taghi
+[0-9a-f]+ <[^>]*> 5974 28e7 	dmfgc0	a7,\$20,5
+[0-9a-f]+ <[^>]*> 5ae2 02e7 	dmtgc0	s7,c0_entrylo0
+[0-9a-f]+ <[^>]*> 58ee 12e7 	dmtgc0	a3,\$14,2
+	...
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.220
diff -u -p -r1.220 mips.exp
--- gas/testsuite/gas/mips/mips.exp	10 Jun 2013 18:15:48 -0000	1.220
+++ gas/testsuite/gas/mips/mips.exp	12 Jun 2013 23:10:06 -0000
@@ -442,7 +442,7 @@ mips_arch_create mips64r2 64	mips64	{ mi
 mips_arch_create mips16	32	{}	{} \
 			{ -march=mips1 -mips16 } { -mmips:16 }
 mips_arch_create micromips 64	mips64r2 {} \
-			{ -march=mips64 -mmicromips } {}
+			{ -march=mips64r2 -mmicromips } {}
 mips_arch_create r3000 	32	mips1	{} \
 			{ -march=r3000 -mtune=r3000 } { -mmips:3000 }
 mips_arch_create r3900 	32	mips1	{ gpr_ilocks } \
@@ -791,8 +791,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "lineno"
     run_dump_test "sync"
 
-    run_dump_test_arches "virt" [mips_arch_list_matching mips32r2 !micromips]
-    run_dump_test_arches "virt64" [mips_arch_list_matching mips64r2 !micromips]
+    run_dump_test_arches "virt" [mips_arch_list_matching mips32r2]
+    run_dump_test_arches "virt64" [mips_arch_list_matching mips64r2]
 
     run_dump_test_arches "mips32"	[mips_arch_list_matching mips32]
     run_dump_test_arches "mips32-imm"	[mips_arch_list_matching mips32]
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.538
diff -u -p -r1.538 tc-mips.c
--- gas/config/tc-mips.c	10 Jun 2013 18:15:47 -0000	1.538
+++ gas/config/tc-mips.c	12 Jun 2013 23:09:01 -0000
@@ -381,7 +381,8 @@ static int file_ase_mt;
 static int file_ase_virt;
 
 #define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2		\
-			       || mips_opts.isa == ISA_MIPS64R2)
+			       || mips_opts.isa == ISA_MIPS64R2		\
+			       || mips_opts.micromips)
 
 #define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2)
Index: opcodes/micromips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/micromips-opc.c,v
retrieving revision 1.10
diff -u -p -r1.10 micromips-opc.c
--- opcodes/micromips-opc.c	8 Jun 2013 10:22:55 -0000	1.10
+++ opcodes/micromips-opc.c	12 Jun 2013 23:12:15 -0000
@@ -110,6 +110,10 @@
 /* MIPS MCU (MicroController) ASE support.  */
 #define MC	ASE_MCU
 
+/* MIPS Virtualization ASE.  */
+#define IVIRT	ASE_VIRT
+#define IVIRT64	ASE_VIRT64
+
 const struct mips_opcode micromips_opcodes[] =
 {
 /* These instructions appear first so that the disassembler will find
@@ -455,9 +459,15 @@ const struct mips_opcode micromips_opcod
 {"dmfc0",   "t,G",	0x580000fc, 0xfc00ffff,	WR_t|RD_C0,		0,		I3	},
 {"dmfc0",   "t,+D",	0x580000fc, 0xfc00c7ff,	WR_t|RD_C0,		0,		I3	},
 {"dmfc0",   "t,G,H",	0x580000fc, 0xfc00c7ff,	WR_t|RD_C0,		0,		I3	},
+{"dmfgc0",  "t,G",	0x580000e7, 0xfc00ffff,	WR_t|RD_C0,		0,		0,	IVIRT64	},
+{"dmfgc0",  "t,+D",	0x580000e7, 0xfc00c7ff,	WR_t|RD_C0,		0,		0,	IVIRT64	},
+{"dmfgc0",  "t,G,H",	0x580000e7, 0xfc00c7ff,	WR_t|RD_C0,		0,		0,	IVIRT64	},
 {"dmtc0",   "t,G",	0x580002fc, 0xfc00ffff,	RD_t|WR_C0|WR_CC,	0,		I3	},
 {"dmtc0",   "t,+D",	0x580002fc, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		I3	},
 {"dmtc0",   "t,G,H",	0x580002fc, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		I3	},
+{"dmtgc0",  "t,G",	0x580002e7, 0xfc00ffff,	RD_t|WR_C0|WR_CC,	0,		0,	IVIRT64	},
+{"dmtgc0",  "t,+D",	0x580002e7, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		0,	IVIRT64	},
+{"dmtgc0",  "t,G,H",	0x580002e7, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		0,	IVIRT64	},
 {"dmfc1",   "t,S",	0x5400243b, 0xfc00ffff,	WR_t|RD_S|FP_S,		0,		I3	},
 {"dmfc1",   "t,G",	0x5400243b, 0xfc00ffff,	WR_t|RD_S|FP_S,		0,		I3	},
 {"dmtc1",   "t,G",	0x54002c3b, 0xfc00ffff,	RD_t|WR_S|FP_S,		0,		I3	},
@@ -524,6 +534,8 @@ const struct mips_opcode micromips_opcod
 {"floor.l.s", "T,V",	0x5400033b, 0xfc00ffff,	WR_T|RD_S|FP_S|FP_D,	0,		I1	},
 {"floor.w.d", "T,V",	0x54004b3b, 0xfc00ffff,	WR_T|RD_S|FP_S|FP_D,	0,		I1	},
 {"floor.w.s", "T,V",	0x54000b3b, 0xfc00ffff,	WR_T|RD_S|FP_S,		0,		I1	},
+{"hypcall",   "",	0x0000c37c, 0xffffffff,	TRAP,			0,		0,	IVIRT	},
+{"hypcall",   "B",	0x0000c37c, 0xfc00ffff,	TRAP,			0,		0,	IVIRT	},
 {"ins",     "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s,		0,		I1	},
 {"iret",    "",		0x0000d37c, 0xffffffff,	NODS,			0,		0,	MC	},
 {"jr",      "mj",	    0x4580,     0xffe0,	UBD,			RD_mj,		I1	},
@@ -670,6 +682,9 @@ const struct mips_opcode micromips_opcod
 {"mfc1",    "t,S",	0x5400203b, 0xfc00ffff,	WR_t|RD_S|FP_S,		0,		I1	},
 {"mfc1",    "t,G",	0x5400203b, 0xfc00ffff,	WR_t|RD_S|FP_S,		0,		I1	},
 {"mfc2",    "t,G",	0x00004d3c, 0xfc00ffff,	WR_t|RD_C2,		0,		I1	},
+{"mfgc0",   "t,G",	0x000004fc, 0xfc00ffff,	WR_t|RD_C0,		0,		0,	IVIRT	},
+{"mfgc0",   "t,+D",	0x000004fc, 0xfc00c7ff,	WR_t|RD_C0,		0,		0,	IVIRT	},
+{"mfgc0",   "t,G,H",	0x000004fc, 0xfc00c7ff,	WR_t|RD_C0,		0,		0,	IVIRT	},
 {"mfhc1",   "t,S",	0x5400303b, 0xfc00ffff,	WR_t|RD_S|FP_D,		0,		I1	},
 {"mfhc1",   "t,G",	0x5400303b, 0xfc00ffff,	WR_t|RD_S|FP_D,		0,		I1	},
 {"mfhc2",   "t,G",	0x00008d3c, 0xfc00ffff,	WR_t|RD_C2,		0,		I1	},
@@ -712,6 +727,9 @@ const struct mips_opcode micromips_opcod
 {"mtc1",    "t,S",	0x5400283b, 0xfc00ffff,	RD_t|WR_S|FP_S,		0,		I1	},
 {"mtc1",    "t,G",	0x5400283b, 0xfc00ffff,	RD_t|WR_S|FP_S,		0,		I1	},
 {"mtc2",    "t,G",	0x00005d3c, 0xfc00ffff,	RD_t|WR_C2|WR_CC,	0,		I1	},
+{"mtgc0",   "t,G",	0x000006fc, 0xfc00ffff,	RD_t|WR_C0|WR_CC,	0,		0,	IVIRT	},
+{"mtgc0",   "t,+D",	0x000006fc, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		0,	IVIRT	},
+{"mtgc0",   "t,G,H",	0x000006fc, 0xfc00c7ff,	RD_t|WR_C0|WR_CC,	0,		0,	IVIRT	},
 {"mthc1",   "t,S",	0x5400383b, 0xfc00ffff,	RD_t|WR_S|FP_D,		0,		I1	},
 {"mthc1",   "t,G",	0x5400383b, 0xfc00ffff,	RD_t|WR_S|FP_D,		0,		I1	},
 {"mthc2",   "t,G",	0x00009d3c, 0xfc00ffff,	RD_t|WR_C2|WR_CC,	0,		I1	},
@@ -937,6 +955,12 @@ const struct mips_opcode micromips_opcod
 {"tgeu",    "s,t,|",	0x0000043c, 0xfc000fff,	RD_s|RD_t|TRAP,		0,		I1	},
 {"tgeu",    "s,j",	0x41600000, 0xffe00000,	RD_s|TRAP,		0,		I1	}, /* tgeiu */
 {"tgeu",    "s,I",	0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I1	},
+{"tlbginv", "",		0x0000417c, 0xffffffff,	INSN_TLB,		0,		0,	IVIRT	},
+{"tlbginvf","",		0x0000517c, 0xffffffff,	INSN_TLB,		0,		0,	IVIRT	},
+{"tlbgp",   "",		0x0000017c, 0xffffffff,	INSN_TLB,		0,		0,	IVIRT	},
+{"tlbgr",   "",		0x0000117c, 0xffffffff,	INSN_TLB,		0,		0,	IVIRT	},
+{"tlbgwi",  "",		0x0000217c, 0xffffffff,	INSN_TLB,		0,		0,	IVIRT	},
+{"tlbgwr",  "",		0x0000317c, 0xffffffff,	INSN_TLB,		0,		0,	IVIRT	},
 {"tlbp",    "",		0x0000037c, 0xffffffff,	INSN_TLB,		0,		I1	},
 {"tlbr",    "",		0x0000137c, 0xffffffff,	INSN_TLB,		0,		I1	},
 {"tlbwi",   "",		0x0000237c, 0xffffffff,	INSN_TLB,		0,		I1	},
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.101
diff -u -p -r1.101 mips-dis.c
--- opcodes/mips-dis.c	8 Jun 2013 10:22:55 -0000	1.101
+++ opcodes/mips-dis.c	12 Jun 2013 23:12:16 -0000
@@ -2554,8 +2554,12 @@ print_insn_micromips (bfd_vma memaddr, s
 		    {
 		    case 0x000000fc:				/* mfc0  */
 		    case 0x000002fc:				/* mtc0  */
+		    case 0x000004fc:				/* mfgc0  */
+		    case 0x000006fc:				/* mtgc0  */
 		    case 0x580000fc:				/* dmfc0 */
 		    case 0x580002fc:				/* dmtc0 */
+		    case 0x580000e7:				/* dmfgc0 */
+		    case 0x580002e7:				/* dmtgc0 */
 		      infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
 		      break;
 		    default:

  The test result for the mips-sde-elf target is as follows.
Ex:
                === gas Summary ===

# of expected passes            2741
# of expected failures          1
../as-new 2.23.52.20130612

  Any feedback?  Is it ok to commit?  
  Thanks a lot!

Regards,
Chao-ying

Follow-Ups:
- Re: [MIPS] Add new virtualization instructions
  - From: Richard Sandiford
- RE: [MIPS] Add new virtualization instructions
  - From: Maciej W. Rozycki

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