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Re: [PATCH/AArch64 3/3] * opcodes/aarch64-tbl.h (aarch64_opcode_table): Add back the "lost" instruction aliases for scalar compare and vector compare.


Hi Philipp,

On 12/11/13 14:38, Dr. Philipp Tomsich wrote:
James,

thanks for the clarification and pointing out the change in iterators.md, which only
applies to 4.9 (I didn’t check the sources carefully enough last night), but seems to
have never made it into the 4.8.2 tree.

On 11 Dec 2013, at 10:38 , James Greenhalgh<james.greenhalgh@arm.com>  wrote:

In fact, we have this explicit comment in aarch64/iterators.md calling
out the absence of the FCMLE and FCMLT 3 register variants and
describing the workaround.

;; For comparison operators we use the FCM* and CM* instructions.
;; As there are no CMLE or CMLT instructions which act on 3 vector
;; operands, we must use CMGE or CMGT and swap the order of the
;; source operands.

If you are seeing other instructions generated it is either a bug,
or some other pattern.

I just rechecked against a fresh checkout of 4.8.2 and still don't see the n_optab
iterator there, so it appears as if that change didn’t make it onto the 4.8 tree.

In case you haven't been aware, James has backported the change to gcc-4_8-branch@206133 before Christmas:

commit 0ae4ef5a14e5a50fa125142726bc6aa5fc0a05a8
Author: jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4>
Date:   Thu Dec 19 20:01:26 2013 +0000

    [AArch64 4.8-branch] Backport: Fix <F>CM instruction generation.


Thanks,
Yufeng


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