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[Bug] subword handling for DI modes
- To: cgen at sources dot redhat dot com
- Subject: [Bug] subword handling for DI modes
- From: Ben Elliston <bje at redhat dot com>
- Date: Tue, 10 Oct 2000 12:19:12 +1100
- CC: bje at redhat dot com
Hi,
What follows is a minimal CPU description that demonstrates a problem
I'm having with the (subword ..) rtx. In the semantics for my
fictitious ADD instruction, I am taking the 0th SI subword from a
DI-sized operand, yet the generated simulator code thinks it is SI:
{
DI opval = SUBWORDSISI (CPU (h_reg));
CPU (h_reg) = opval;
TRACE_RESULT (current_cpu, abuf, "reg", 'D', opval);
}
Here is a minimal test case that reproduces the problem. Does anyone
have any ideas? Thanks,
Ben
(include "simplify.inc")
(define-arch
(name foo)
(comment "foo")
(insn-lsb0? #t)
(machs foo1)
(isas yep)
)
(define-isa
(name yep)
(comment "yep")
(base-insn-bitsize 32)
)
(define-cpu
(name foof)
(comment "foo family")
(endian either)
(word-bitsize 32)
)
(define-mach
(name foo1)
(comment "foo1 cpu")
(cpu foof)
)
(define-model
(name foo)
(comment "foo")
(mach foo1)
(unit u-exec "Execution unit" ()
1 1 ; issue done
() () () ())
)
(define-hardware
(name h-reg)
(comment "64-bit register")
(type register DI)
)
(dnf f-reg "Register" () 31 6)
(dnf f-rest "Rest of instruction" () 25 26)
(dnop reg "Register" () h-reg f-reg)
(dni add "Add"
()
"add $reg"
(+ reg (f-rest 0))
(set reg (subword SI reg 0))
()
)