Re: defining 2-operand version of 3-operand insns?

[Greg McGary <greg at mcgary dot org>]

Greg McGary <greg@mcgary.org> writes:

> I got this to work by employing a dirty trick.  Fortunately,
> the dest and src1 operands are contiguous, so I defined a
> new field that encompasses both, called f-dest2, and used
> encode/decode magic to propagate:
> 
> (df  f-dest2   "dest dup'ed into src1"      () 25 10 UINT
>      ((value pc) (add UWI value (sll UWI value (const 5))))
>      ((value pc) (srl UWI value 5)))
> 
> The decode part is actually unused, since the insn that uses
> dest2 has a NO-DIS attribute.

Whereas this works for the assembler, it causes trouble for the
simulator:

Processing decoder for bits 31 30 29 28 27 26 ...
Filtering 2 instructions.
Instruction add2rambiguity-filtered by add3r
Instruction add3rambiguity-filtered by add2r
Processing decode entry 0 in decode_table_0, invalid ...

All of the instructions for which I have 2 & 3 operand versions
defined as above are excluded from the sim decoder as ambiguous.
Since the 2-operand versions are exclusively an assembler-language
convenience, they should be ignored from the simulator.
Unfortunately, I don't see a `NO-SIM' attribute.  Should I add one, or
is there a better way out of this jam?

Greg