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bits in registers
- To: cgen at sources dot redhat dot com
- Subject: bits in registers
- From: Johan Rydberg <johan dot rydberg at netinsight dot se>
- Date: Sat, 13 Jan 2001 03:06:39 +0100
- Organization: Net Insight AB
Hi!
As you all know from my mail last night I'm working on a CPU description
for PowerPC.
As you all know (or not) the PowerPC has a condition register (32 bits
wide) that is split into eight "sub-registers", CR0-CR7. These registers
can be altered, moved, anded and compared. The whole register can be
accessed aswell.
Since CGEN don't have a 4-bit quantity I have defined the sub-registers
as bytes (QI):
(define-hardware
(name h-cr) (comment "condition register") (attrs PROFILE)
(type register QI (8))
)
Is there a simple way to, for example, modify bit 2 in (reg h-cr 2),
or do I have to mask and or it into place? I really don't want to
escape into C just for doing this !
(comments on the attached file are welcome)
--
$ ON F$ERROR("LANGUAGE","ENGLISH","IN_MESSAGE").GT.F$ERROR("NORMAL") -
THEN EXCUSE/OBJECT=ME
; PowerPC microprocessor family. -*- Scheme -*-
; Copyright (C) 2001 Free Software Foundation, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
(include "simplify.inc")
(define-arch
(name powerpc)
(comment "PowerPC microprocessor family")
(insn-lsb0? #f)
(machs ppc-603 ppc-601)
(isas ppcisa)
)
; Attributes
; The PowerPC architecture has three ISA levels:
; . user level instruction set architecture, (UISA)
; . virtual environment architecture, (VEA)
; . and operating environment architecture.
;
(define-attr
(for insn) (type enum)
(name ISA-LEVEL)
(comment "isa level") (attrs)
(values UISA VEA OEA)
(default UISA)
)
; Instruction set parameters.
(define-isa
; Name of the ISA.
(name ppcisa) ; FIXME not a good name
; Base insturction length. The insns is always 32 bits wide.
(base-insn-bitsize 32)
; Set GRP 0 to zero (hardwired). FIXME is the correct way ??
(setup-semantics (set-quiet (reg h-grp 0) 0))
)
; CPU family definitions.
(define-cpu
; CPU names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name powerpcbf)
(comment "PowerPC base family")
(endian big)
(word-bitsize 32)
)
; Generic machine
(define-mach
(name ppc-603) ; FIXME not a good name
(comment "Generic 603 cpu")
(cpu powerpcbf)
(bfd-name "powerpc:603")
)
(define-mach
(name ppc-601) ; FIXME not a good name
(comment "Generic 601 cpu")
(cpu powerpcbf)
(bfd-name "powerpc:601")
)
; Model descriptions
; Generic 603 model
(define-model
(name ppc-603)
(comment "603 generic model")
(attrs)
(mach ppc-603)
; FIXME
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-iu "Integer Unit" ()
1 1 ; issue done
() ; state
((rA INT -1) (rB INT -1)) ; FIXME inputs
((rD INT -1)) ; FIXME outputs
() ; profile action (default)
)
(unit u-sru "System Register Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-fpu "Floating-Point Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-lsu "Load/store Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; outputs
() ; profile action (default)
)
(unit u-bpu "Branch Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
)
; 603e
(define-model
(name ppc-603e)
(comment "603e model")
(attrs)
(mach ppc-603)
; FIXME
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-iu "Integer Unit" ()
1 1 ; issue done
() ; state
((rA INT -1) (rB INT -1)) ; FIXME inputs
((rD INT -1)) ; FIXME outputs
() ; profile action (default)
)
(unit u-sru "System Register Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-fpu "Floating-Point Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-lsu "Load/store Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; outputs
() ; profile action (default)
)
(unit u-bpu "Branch Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
)
; Generic 601 model
(define-model
(name ppc-601)
(comment "601 generic model")
(attrs)
(mach ppc-601)
; FIXME
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-iu "Integer Unit" ()
1 1 ; issue done
() ; state
((rA INT -1) (rB INT -1)) ; FIXME inputs
((rD INT -1)) ; FIXME outputs
() ; profile action (default)
)
(unit u-sru "System Register Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-fpu "Floating-Point Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
(unit u-lsu "Load/store Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; outputs
() ; profile action (default)
)
(unit u-bpu "Branch Unit" ()
1 1 ; issue done
() ; state
() ; FIXME inputs
() ; FIXME outputs
() ; profile action (default)
)
)
; Instruction fields.
; Attributes:
; . PCREL-ADDR pc relative value (for reloc and disassembly purposes)
; . ABS-ADDR absolute address (for reloc and disassembly purposes?)
; . RESERVED bits are not used to decode insn, must be all 0
; Absolute address bit
(dnf f-AA "absolute address" () 30 1)
; Immediate field specifying a 14-bit signed two's complement branch
; displacement that is concatenated on the right with 0b00 and
; sign-extended to 32 bits
; FIXME here
;(df f-BD "14-bit branch displacement" (PCREL-ADDR) 16 14 INT
; ((value pc) (sra WI (sub WI value pc) (const 2)))
; ((value pc) (add WI (sll WI value (const 2)) pc)))
;(df f-LI "14-bit branch displacement" (PCREL-ADDR) 6 24 INT
; ((value pc) (sra WI (sub WI value pc) (const 2)))
; ((value pc) (add WI (sll WI value (const 2)) pc)))
; 24-bit signed two's complement integer
(df f-LI "signed imm (24)" () 6 24 INT #f #f)
(df f-BD "signed imm (14)" () 16 14 INT #f #f)
; Bit in the CR to be used as the condition of a branch
; conditional instruction
(dnf f-BI "CR bits" () 11 5)
; FIXME comment
(dnf f-L "CR option" () 10 1)
(dnf f-Y "CR option" () 9 1)
; Specify options for branch conditional instructions
(dnf f-BO "CR options" () 6 5)
; Bit in the CR to be used as a source
(dnf f-crbA "CR source A" () 11 5)
(dnf f-crbB "CR source B" () 16 5)
; Bit in the CR, or in the FPSCR, as the destination of the result
; of an instruction
(dnf f-crbD "CR destination" () 6 5)
; Specify one of the CR fields, or one of the FPSCR fields,
; as a destination/source.
(dnf f-crfD "CR/FPSCR destination" () 6 3)
(dnf f-crfS "CR/FPSCR source" () 11 3)
; Mask to identify the CR fields that are to be updated by the
; MTCRF instruction.
(dnf f-CRM "CR mask" () 12 8)
; 16-bit signed two's complement integer
(df f-d "signed imm (16)" () 16 16 INT #f #f)
; Mask to identify the FPSCR fields that are to be updated by the
; MTFSF instruction.
(dnf f-FM "FPSCR mask" () 7 8)
; Speicify an FPR as a source/destination
(dnf f-frA "FPR source A" () 11 5)
(dnf f-frB "FPR source B" () 16 5)
(dnf f-frC "FPR source C" () 21 5)
(dnf f-frD "FPR destination D" () 6 5)
(dnf f-frS "FPR source S" () 6 5)
; Immediate field (4 bits)
(dnf f-IMM "FPSCR imm (4 bits)" () 16 4)
; Link bit
(dnf f-LK "link bit" () 31 1)
; Fields used in rotate instructions to specify a 32-bit mask
(dnf f-MB "FIXME" () 21 5)
(dnf f-ME "FIXME" () 26 5)
; Specify nr of bytes to mive in a immediate string load/store
(dnf f-NB "number of bytes" () 16 5)
; Used by extended arithmetic to enable setting OV and SO in XER
(dnf f-OE "OE bit" () 21 1)
; Prmary opcode field
(dnf f-OPCD "primary opcode" () 0 6)
; GPR fields
(dnf f-rA "GPR source/destination register A" () 11 5)
(dnf f-rB "GPR source register B" () 16 5)
(dnf f-rD "GPR destination register D" () 6 5)
(dnf f-rS "GPR source register S" () 6 5)
; Record bit
(dnf f-Rc "record bit" () 31 1)
; Shift amount
(dnf f-SH "shift amount" () 16 5)
; 16-bit signed/unsigned integer
(df f-SIMM "signed imm (16)" () 16 16 INT #f #f)
(dnf f-UIMM "unsigned imm (16)" () 16 16)
; Used to specify one of the 16 segment registers
(dnf f-SR "segment register" () 12 4)
; Trap
(dnf f-TO "trap" () 6 5)
; Extended opcode fields
(dnf f-XO-1 "xo-1" () 21 10)
(dnf f-XO-2 "xo-2" () 22 9)
(dnf f-XO-3 "xo-3" () 26 5)
; Enums.
;
(define-normal-insn-enum insn-class "FIXME" () OPCD_ f-OPCD
(.map .str (.iota 128))
)
(define-normal-insn-enum insn-xo-1 "FIXME" () OP1_ f-XO-1
(.map .str (.iota 1024))
)
(define-normal-insn-enum insn-xo-2 "FIXME" () OP2_ f-XO-2
(.map .str (.iota 512))
)
(define-normal-insn-enum insn-xo-2 "FIXME" () OP3_ f-XO-3
(.map .str (.iota 32))
)
; Hardware pieces.
; Program counter, also called CIA (Current Instruction Address)
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
; UISA Programming Model-User Level Registers:
(define-hardware
(name h-gpr) (comment "general registers") (attrs PROFILE)
(type register WI (32))
(indices keyword "%" ; FIXME no prefix
(("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5)
("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
("12" 12) ("13" 13) ("14" 14) ("15" 15) ("16" 16) ("17" 17)
("18" 18) ("19" 19) ("20" 20) ("21" 21) ("22" 22) ("23" 23)
("24" 24) ("25" 25) ("26" 26) ("27" 27) ("28" 28) ("29" 29)
("30" 30) ("31" 31)))
)
; Floating-Point Registers:
(define-hardware
(name h-fpr) (comment "floating point registers") (attrs PROFILE)
(type register DI (32))
(indices keyword "%" ; FIXME no prefix
((fpr0 0) (fpr1 1) (fpr2 2) (fpr3 3) (fpr4 4) (fpr5 5)
(fpr6 6) (fpr7 7) (fpr8 8) (fpr9 9) (fpr10 10) (fpr11 11)
(fpr12 12) (fpr13 13) (fpr14 14) (fpr15 15) (fpr16 16)
(fpr17 17) (fpr18 18) (fpr19 19) (fpr20 20) (fpr21 21)
(fpr22 22) (fpr23 23) (fpr24 24) (fpr25 25) (fpr26 26)
(fpr27 27) (fpr28 28) (fpr29 29) (fpr30 30) (fpr31 31)))
)
; Special Purpose Registers:
(define-hardware
(name h-spr) (comment "special purpose registers") (attrs PROFILE)
(type register WI (1024))
; We Have getter and setter for this type since we have to collect
; data from other registers (such as LR, CTR, XER, ...)
(get (index) (c-call SI "@arch@_h_spr_get_handler" index))
(set (index newval) (c-call VOID "@arch@_h_spr_set_handler" index newval))
)
; Link Register
(define-hardware
(name h-lr) (comment "link register (spr 8)") (attrs PROFILE)
(type register WI)
)
; Count Register
(define-hardware
(name h-ctr) (comment "count register (spr 9)") (attrs PROFILE)
(type register WI)
)
; XER Register
(define-hardware
(name h-xer) (comment "xer register (spr 1)") (attrs PROFILE)
(type register WI)
)
; The condition register is a 32-bit register that reflects the result
; of certain operations and provides a mechanism for testinga dn branching.
; The bits in the CR are grouped into eight 4-bit fields, CR0-CR7.
;
; Since CGEN don't have a 4-bit mode, we specify them as QI (byte).
;
(define-hardware
(name h-cr) (comment "condition register") (attrs PROFILE)
(type register QI (8))
)
(define-hardware
(name h-crb) (comment "condition register (bits)") (attrs PROFILE)
(type register BI (32))
(get (index) (c-call SI "@arch@_h_crb_get_handler" index))
(set (index newval) (c-call VOID "@arch@_h_crb_set_handler" index newval))
)
; Floating-Point Status and Condition Register
(define-hardware
(name h-fpscr) (comment "floating point status and condition register")
(attrs PROFILE) (type register WI)
)
; Record bit
(define-hardware
(name h-rc) (comment "record bit") (attrs PROFILE)
(type immediate (UINT 1))
(values keyword "" (("" 0) ("." 1)))
)
; FIXME
(define-hardware
(name h-oe) (comment "FIXME") (attrs PROFILE)
(type immediate (UINT 1))
(values keyword "" (("" 0) ("o" 1)))
)
; Absolute address bit
(define-hardware
(name h-aa) (comment "FIXME") (attrs PROFILE)
(type immediate (UINT 1))
(values keyword "" (("" 0) ("a" 1)))
)
; Link bit
(define-hardware
(name h-lk) (comment "FIXME") (attrs PROFILE)
(type immediate (UINT 1))
(values keyword "" (("" 0) ("l" 1)))
)
; Bit fields in hardware registers.
; Macro to define a hardware bit of a hardware register (with index)
(define-pmacro (define-bit/reg-multi-hardware MODE NAME COMMENT REG REGNO BIT)
(begin
(define-hardware
(name NAME) (comment COMMENT) (attrs)
(type register BI)
(get () (and (srl (reg REG REGNO) BIT) #x1))
(set (newval) (set (reg REG REGNO) (or (and (reg REG REGNO)
(inv MODE BIT))
newval)))
)
)
)
; Macro to define a hardware bit of a hardware register
(define-pmacro (define-bit/reg-hardware MODE NAME COMMENT REG BIT)
(begin
(define-hardware
(name NAME) (comment COMMENT) (attrs)
(type register BI)
(get () (and (srl (reg REG) BIT) #x1))
(set (newval) (set (reg REG) (or (and (reg REG)
(inv MODE BIT))
newval)))
)
)
)
; Macro to set bit number BN in register REG to NEWVAL. MODE is
; the mode of REG.
(define-pmacro (bit-set MODE REG BN NEWVAL)
(set REG (or (and REG (inv MODE (srl 1 BN)))
NEWVAL))
)
; Get the value of bit BN in REG. MODE is the mode of REG.
(define-pmacro (bit-get MODE REG BN)
(subword BI REG BN)
; (and REG (inv MODE (sll 1 BN)))
)
; FIXME check bitvalues!!!
; The summary overflow bit is set whenever an instruction sets the
; overflow bit (OV). Once set, the SO bit remains set until it is cleared
; by and MTSPR instruction.
(define-bit/reg-hardware SI h-xer/so "summary overflow" h-xer #x4)
; The overflow bit is set to indicate than an overflow has occurred
; during execution of an instruction.
(define-bit/reg-hardware SI h-xer/ov "overflow" h-xer #x2)
; The carry bit is set during execution of the following instructions:
; . Add carrying, subtract from carrying, add extended, and
; subtract from extended instrions set CA if there is a carry out of
; the msb, and clear it otherwise.
; . Shift right algebraic instruction set CA if any 1 bits have been
; shifted out of a negative operand, and clear it otherwise.
(define-bit/reg-hardware SI h-xer/ca "carry" h-xer #x1)
; Bit settings for CR0 field of CR:
(define-bit/reg-multi-hardware QI h-cr/0+lt "negative (lt)" h-cr 0 #x8)
(define-bit/reg-multi-hardware QI h-cr/0+gt "positive (gt)" h-cr 0 #x4)
(define-bit/reg-multi-hardware QI h-cr/0+eq "zero (eq)" h-cr 0 #x2)
(define-bit/reg-multi-hardware QI h-cr/0+so "overflow (so)" h-cr 0 #x1)
; Macros to access the CR0 bits in a simpler manner.
(define-pmacro cr0/lt (reg h-cr/0+lt))
(define-pmacro cr0/gt (reg h-cr/0+gt))
(define-pmacro cr0/eq (reg h-cr/0+eq))
(define-pmacro cr0/so (reg h-cr/0+so))
; Macros to access the XER bits in a simpler manner.
(define-pmacro xer/ca (reg h-xer/ca))
(define-pmacro xer/ov (reg h-xer/ov))
(define-pmacro xer/so (reg h-xer/so))
; Instruction operands.
; GPR registers
(dnop rA "GPR register A" () h-gpr f-rA)
(dnop rB "GPR register B" () h-gpr f-rB)
(dnop rD "GPR register D" () h-gpr f-rD)
(dnop rS "GPR register S" () h-gpr f-rS)
; condition registers
(dnop crfD "CR destination" () h-uint f-crfD)
; XXX
(dnop l "l" () h-uint f-L)
; Link Register
(dnop lr "link register" (SEM-ONLY) h-lr f-nil) ; FIXME sem-only ??
(dnop bo "BO" () h-uint f-BO)
(dnop bi "BI" () h-uint f-BI)
; FIXME!
(dnop crb "CR bits" () h-crb f-nil) ; SEM-ONLY ??
; Immediates
(dnop simm "signed 16bit" () h-sint f-SIMM)
(dnop uimm "unsigned 16bit" () h-uint f-UIMM)
(dnop li "signed 24bit" () h-iaddr f-LI)
(dnop bd "signed 14bit" () h-iaddr f-BD)
; Instruction operands for bits in the opcode.
(define-operand (name Rc) (comment "parse of Rc bit") (attrs)
(type h-rc) (index f-Rc) (handlers (parse "rc_bit"))
)
(define-operand (name OE) (comment "parse of OE bit") (attrs)
(type h-oe) (index f-OE) (handlers (parse "oe_bit"))
)
(define-operand (name AA) (comment "parse of AA bit") (attrs)
(type h-aa) (index f-AA) (handlers (parse "aa_bit"))
)
(define-operand (name LK) (comment "parse of AA bit") (attrs)
(type h-lk) (index f-LK) (handlers (parse "aa_bit"))
)
; Instructions.
; Macro to update XER bits according to SEM-OP. SEM-OP has
; to be extended to DI mode (so that we can detect overflow).
; Example:
;
; (update-xer/so+ov (add (ext DI rA)
; (ext DI rB)))
;
; FIXME check shift
(define-pmacro (update-xer/so+ov sem-op)
(sequence ((DI res) (SI top))
; update OV
(set res sem-op)
(set top (ext SI (srl res 32)))
(if VOID top (set xer/ov 1) (set xer/ov 0))
; update SO
(if VOID top (set xer/so 1)))
)
; FIXME check shift
(define-pmacro (update-xer/ca sem-op)
(sequence ((DI res) (SI top))
(set res sem-op) ; get result
(set top (ext SI (srl res 32))) ; get high 32-bit
(set xer/ca (and res #x1))) ; set CA
)
; Macro to update the bits in CR0 according to SEM-OP, A and B.
; Example:
;
; (update-cr0 (add rA rB) rA rB)
;
(define-pmacro (update-cr0 sem-op a b)
(sequence ((SI res))
(set res sem-op) ; get result
(set cr0/lt (lt res 0)) ; update LT
(set cr0/gt (gt res 0)) ; update GT
(set cr0/eq (eq res 0)) ; update EQ
(set cr0/so xer/so)) ; update SO
)
; Macro to update the bits in CRN according to SEM-OP, A and B.
; RN specifies what condition register that needs an update.
; Example:
;
; (update-crn 1 rA rB)
;
(define-pmacro (update-crn rn a b)
(sequence ()
(bit-set QI (reg h-cr rn) 0 (lt a b))
(bit-set QI (reg h-cr rn) 1 (gt a b))
(bit-set QI (reg h-cr rn) 2 (eq a b))
(if VOID xer/so (bit-set QI (reg h-cr rn) 3 xer/so)))
)
; Add
; The sum (rA) + (rB) is placed into rD.
;
; Altered registers:
; . cr0 (lt, gt, eq so) if Rc = 1
; . xer (so, ov) if OE = 1
(dni addx "addx" ((ISA-LEVEL UISA))
"add$Rc$OE $rD,$rA,$rB"
(+ OPCD_31 rD rA rB OE OP2_266 Rc)
; We do the stuff in sequence.
(sequence ()
(set rD (add rA rB))
; update CR acording to Rc=1
(if VOID Rc (update-cr0 (add rA rB) rA rB))
; update XER acording to OE=1
(if VOID OE
(update-xer/so+ov (add (ext DI rA)
(ext DI rB))))
)
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add Carrying
; The sum (rA) + (rB) is placed into rD.
;
; Altered registers:
; . cr0 (lt, gt, eq so) if Rc = 1
; . xer (ca)
; . xer (so, ov) if OE = 1
(dni addcx "addcx" ((ISA-LEVEL UISA))
"addc$Rc$OE $rD,$rA,$rB"
(+ OPCD_31 rD rA rB OE OP2_10 Rc)
; We do the stuff in sequence.
(sequence ()
(set rD (add rA rB))
; update CR acording to Rc=1
(if VOID Rc (update-cr0 (add rA rB) rA rB))
; update XER acording to OE=1
(if VOID OE
(update-xer/so+ov (add (ext DI rA)
(ext DI rB))))
(update-xer/ca (add (ext DI rA)
(ext DI rB)))
)
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add Extended
; The sum (rA) + (rB) + XER[CA] is placed into rD.
;
; Altered registers:
; . cr0 (lt, gt, eq so) if Rc = 1
; . xer (ca)
; . xer (so, ov) if OE = 1
(dni addex "addex" ((ISA-LEVEL UISA))
"adde$Rc$OE $rD,$rA,$rB"
(+ OPCD_31 rD rA rB OE OP2_138 Rc)
(sequence ()
(set rD (addc rA rB xer/ca))
; update CR acording to Rc=1
(if VOID Rc (update-cr0 (addc rA rB xer/ca) rA rB))
; update XER acording to OE=1
(if VOID OE
(update-xer/so+ov (addc (ext DI rA)
(ext DI rB)
xer/ca)))
(update-xer/ca (addc (ext DI rA)
(ext DI rB)
xer/ca))
)
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add Immediate
; The sum (rA|0) + SIMM is placed into rD.
;
; No altered registers.
(dni addi "addi" ((ISA-LEVEL UISA))
"addi $rD,$rA,$simm"
(+ OPCD_14 rD rA simm)
(set rD (add rA simm))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
(dnmi li "li" ((ISA-LEVEL UISA))
"li $rD,$simm"
(emit addi rD (rA 0) simm) ; "addi $rD,0,$simm"
)
(dnmi la "la" ((ISA-LEVEL UISA))
"la $rD,$simm($rA)"
(emit addi rD rA simm) ; "addi $rD,$rA,$simm"
)
; Add Immediate Carrying
; The sum (rA|0) + SIMM is placed into rD.
;
; Altered registers:
; . xer (ca)
(dni addic "addic" ((ISA-LEVEL UISA))
"addic $rD,$rA,$simm"
(+ OPCD_12 rD rA simm)
(sequence ()
(set rD (add rA simm))
; update XER
(update-xer/ca (add (ext DI rA)
(ext DI simm))))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add Immediate Carrying and Record
; The sum (rA|0) + SIMM is placed into rD.
;
; Altered registers:
; . cr0 (lt, gt, eq so)
; . xer (ca)
(dni addidot "addidot" ((ISA-LEVEL UISA))
"addic. $rD,$rA,$simm"
(+ OPCD_13 rD rA simm)
(sequence ()
(set rD (add rA simm))
; update CR
(update-cr0 (add rA simm) rA simm)
; update XER
(update-xer/ca (add (ext DI rA)
(ext DI simm))))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add Immediare Shifted
(dni addis "addis" ((ISA-LEVEL UISA))
"addis $rD,$rA,$simm"
(+ OPCD_15 rD rA simm)
(set rD (add rA (sll simm 16)))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add to Minus one Extended
(dni addmex "addmex" ((ISA-LEVEL UISA))
"addme$Rc$OE $rD,$rA"
(+ OPCD_31 rD rA (f-rB 0) OE OP2_234 Rc)
(sequence ()
(set rD (sub (add rA xer/ca) 1))
; update CR acording to Rc=1
(if VOID Rc
(update-cr0 (sub (add rA xer/ca) 1) rA xer/ca))
; update XER acording to OE=1
(if VOID OE
(update-xer/so+ov (sub (add (ext DI rA)
(ext DI xer/ca)) 1)))
(update-xer/ca (sub (add (ext DI rA)
(ext DI xer/ca)) 1)))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Add to Zero Extended
(dni addzex "addzex" ((ISA-LEVEL UISA))
"adde$Rc$OE $rD,$rA"
(+ OPCD_31 rD rA (f-rB 0) OE OP2_202 Rc)
(sequence ()
(set rD (add rA xer/ca))
; update CR acording to Rc=1
(if VOID Rc
(update-cr0 (add rA xer/ca) rA rD))
; update XER acording to OE=1
(if VOID OE
(update-xer/so+ov (add (ext DI rA)
(ext DI xer/ca)))))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; AND
(dni andx "andx" ((ISA-LEVEL UISA))
"and$Rc $rA,$rS,$rB"
(+ OPCD_31 rS rA rB OP1_28 Rc)
(sequence ()
(set rA (and rS rB))
; update CR acording to Rc=1
(if VOID Rc
(update-cr0 (and rS rB) rS rB)))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; AND with Complement
(dni andcx "andcx" ((ISA-LEVEL UISA))
"andc$Rc $rA,$rS,$rB"
(+ OPCD_31 rS rA rB OP1_60 Rc)
(sequence ()
(set rA (and rS (inv SI rB)))
; update CR acording to Rc=1
(if VOID Rc
(update-cr0 (and rS (inv SI rB)) rS rB)))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; AND Immediate
(dni andi "andi" ((ISA-LEVEL UISA))
"andi. $rA,$rS,$uimm"
(+ OPCD_28 rA rS uimm)
(sequence ()
(set rA (and rS uimm))
; update CR acording to Rc=1
(update-cr0 (and rS uimm) rS uimm))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; AND Immediate Shifted
(dni andis "andis" ((ISA-LEVEL UISA))
"andis. $rA,$rS,$uimm"
(+ OPCD_29 rA rS uimm)
(sequence ()
(set rA (and rS (sll uimm 16)))
; update CR acording to Rc=1
(update-cr0 (and rS (sll uimm 16)) rS rB))
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Branch
(dni bx "bx" ((ISA-LEVEL UISA))
"b$LK$AA $li"
(+ OPCD_18 li LK AA)
(sequence ()
; Set PC acording to AA
(if VOID AA
(set pc (ext SI (and li #xfffffffc)))
(set pc (add pc (ext SI (and li #xfffffffc)))))
; Set LR acording to LK=1
(if VOID LK (set lr (add pc 4))))
; FIXME override input and output
((ppc-601 (unit u-bpu))
(ppc-603 (unit u-bpu)) (ppc-603e (unit u-bpu)))
)
; Branch Conditional
(dni bcx "bx" ((ISA-LEVEL UISA))
"bc$LK$AA $bo,$bi,$bd"
(+ OPCD_16 LK AA bo bi bd)
(sequence ((SI ctr_ok) (SI cond_ok))
; if !bo[2] -> ctr = ctr - 1
(if (not BI (subword BI bo 2)) (set (reg h-ctr)
(sub (reg h-ctr) 1)))
; ctr_ok <- bo[2] || (ctr != 0) != bo[3]
(set ctr_ok (orif (subword BI bo 2) (ne (ne (reg h-ctr) 0)
(subword BI bo 3))))
; cond_ok <- bo[0] || (cr[bi] == bo[1])
(set cond_ok (orif (subword BI bo 0) (eq (subword BI crb bi)
(subword BI bo 1))))
(if (andif ctr_ok cond_ok)
(sequence ()
(if VOID AA
(set pc (ext SI (and bd #xfffffffc)))
(set pc (add pc (ext SI (and bd #xfffffffc)))))
; Set LR acording to LK=1
(if VOID LK (set lr (add pc 4)))))
)
; FIXME override input and output
((ppc-601 (unit u-bpu))
(ppc-603 (unit u-bpu)) (ppc-603e (unit u-bpu)))
)
; Branch Conditional to Count Register
(dni bcctrx "bctrx" ((ISA-LEVEL UISA))
"bcctr$LK $bo,$bi"
(+ OPCD_19 LK bo bi (f-rB 0) OP1_528)
(sequence ((SI cond_ok))
; cond_ok <- bo[0] || (cr[bi] == bo[1])
(set cond_ok (orif (subword BI bo 0) (eq (subword BI crb bi)
(subword BI bo 1))))
(if cond_ok
(sequence ()
(set pc (and (reg h-ctr) #xfffffffc))
; Set LR acording to LK=1
(if VOID LK (set lr (add pc 4)))))
)
; FIXME override input and output
((ppc-601 (unit u-bpu))
(ppc-603 (unit u-bpu)) (ppc-603e (unit u-bpu)))
)
; Branch Conditional to Link Register
(dni bclrx "bclrx" ((ISA-LEVEL UISA))
"bclr$LK $bo,$bi"
(+ OPCD_19 LK bo bi (f-rB 0) OP1_16)
(sequence ((SI ctr_ok) (SI cond_ok) (WI nia))
; if !bo[2] -> ctr = ctr - 1
(if (not BI (subword BI bo 2)) (set (reg h-ctr)
(sub (reg h-ctr) 1)))
; ctr_ok <- bo[2] || (ctr != 0) != bo[3]
(set ctr_ok (orif (subword BI bo 2) (ne (ne (reg h-ctr) 0)
(subword BI bo 3))))
; cond_ok <- bo[0] || (cr[bi] == bo[1])
(set cond_ok (orif (subword BI bo 0) (eq (subword BI crb bi)
(subword BI bo 1))))
(if (andif ctr_ok cond_ok)
(sequence ()
; Set NIA to LR
(set nia (and lr #xfffffffc))
; Set LR acording to LK=1
(if VOID LK (set lr (add pc 4)))
; Set PC to NIA
(set pc nia)))
)
; FIXME override input and output
((ppc-601 (unit u-bpu))
(ppc-603 (unit u-bpu)) (ppc-603e (unit u-bpu)))
)
; Compare
(dni cmp "cmp" ((ISA-LEVEL UISA))
"cmp $crfD,$l,$rA,$rB"
(+ OPCD_31 crfD l (f-Rc 0) (f-Y 0) rA rB OP1_0)
; We do the stuff in sequence.
(sequence ((SI a) (SI b))
(if l (set a (ext SI rA)) (set b (ext SI rB)))
(if l (set a rA) (set b rB))
(update-crn crfD a b)
)
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Compare Immediate
(dni cmpi "cmpi" ((ISA-LEVEL UISA))
"cmpi $crfD,$l,$rA,$simm"
(+ OPCD_11 crfD l (f-Y 0) rA simm)
; We do the stuff in sequence.
(sequence ()
(update-crn crfD rA simm)
)
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Compare Logical
(dni cmpl "cmpl" ((ISA-LEVEL UISA))
"cmpl $crfD,$l,$rA,$rB"
; for 32-bit implementations, if l = 1 the insn form is invalid
(+ OPCD_31 crfD (f-L 0) (f-Rc 0) (f-Y 0) rA rB OP1_32)
; We do the stuff in sequence.
(sequence ()
(update-crn crfD rA rB)
)
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
; Compare Immediate Logical
(dni cmpli "cmpli" ((ISA-LEVEL UISA))
"cmpli $crfD,$l,$rA,$uimm"
; for 32-bit implementations, if l = 1 the insn form is invalid
(+ OPCD_10 crfD (f-L 0) (f-Y 0) rA uimm)
; We do the stuff in sequence.
(sequence ()
(update-crn crfD rA uimm)
)
; FIXME override input and output
((ppc-601 (unit u-iu))
(ppc-603 (unit u-iu)) (ppc-603e (unit u-iu)))
)
(dni mulli "mulli" ((ISA-LEVEL UISA))
"mulli $rD,$rA,$simm"
(+ OPCD_7 rD rA simm)
; We do the stuff in sequence.
(sequence ((DI res))
(set res (mul rA simm))
(set rD (sra res 16))
)
; FIXME override input and output
((ppc-603 (unit u-iu (cycles 3)))
(ppc-603e (unit u-iu (cycles 3)))
(ppc-601 (unit u-iu (cycles 5))))
)