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How to handle MIPS-like general register 0?
- To: cgen at sourceware dot cygnus dot com
- Subject: How to handle MIPS-like general register 0?
- From: Greg McGary <greg at mcgary dot org>
- Date: Thu, 18 Jan 2001 01:26:21 -0700
What's the recommended way of handling simulator semantics for a
general register zero that always reads as 0, and writes as bit-bucket
(as for MIPS)? Without CGEN support, I'll need to wrap a test for
reg# 0 as destination around the semantics of every insn that modifies
registers.