This is the mail archive of the
cgen@sources.redhat.com
mailing list for the CGEN project.
SID/CGEN IRQ bug
- From: Robert Shideleff <bigbob at shideleff dot com>
- To: sid at sources dot redhat dot com, cgen at sources dot redhat dot com
- Date: Thu, 1 Jul 2004 14:18:49 -0400
- Subject: SID/CGEN IRQ bug
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
I am sending this to both the SID and CGEN mailing lists because I am not sure
who would be in a position to fix this.
The SID model of the arm7t currently enters an interrupt in a way that
resembles edge detected interrupts in hardware. (It doesn't model them
perfectly, because it currently doesn't sense high-to-low transitions.
Instead, any call to drive the pin low no matter what state it is currently
in will spark an interrupt.)
However, regardless of the correctness of how the edge detected interrupts are
currently modeled, the arm7 irq pin is actually level sensitive, not edge
sensitive. This means that any attempt to model interrupt clearing and
setting cannot be made accurate. As an example, eCos depends on the level
sensitive behavior of interrupts. Otherwise, if multiple interrupts arrive at
the same time, it will miss all but one of them.
There is an incredibly trivial way to fix this in the already comgen'ed code.
I would simply modify the function that sets cpsr to check the sense of the
two interrupt pins and drive another irq if necessary. But this wouldn't fix
the original code. I looked through the compgen stuff, and got completely
lost. Is there anybody out there who knows how to fix this in the compgen
code?
Bob
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.4 (GNU/Linux)
iD8DBQFA5FWR8XjOGQDr37YRAvlKAKCKGjrYiRDU6typvSPUgmeuI12HTACfSnAC
dyIlHVNVcg9qlLcMNtfOJcM=
=DCFz
-----END PGP SIGNATURE-----