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Constraints between operands
- From: "Will Newton" <will dot newton at imgtec dot com>
- To: <cgen at sources dot redhat dot com>
- Date: Thu, 8 Sep 2005 14:55:16 +0100
- Subject: Constraints between operands
I'm using cgen to write a binutils port for a processor. I've come
across a problem I haven't been able to solve yet with expressing a
constraint between a number of fields in an instruction.
The instruction is encoded like this:
Bit 24: Data Unit Specifier
Bits 23-19: Destination Register
Bites 18-14: Source Register
(other bits omitted for simplicity)
The data unit bit specifies with set of registers this instruction
operates on. I have modelled this as a multi field for each register.
However I need to ensure that the assembler only allows destination and
source registers from the same unit to be specified and gives an error
otherwise, e.g.:
ADD D0.1,D0.2 ; Data unit 0 for both regs, OK
ADD D0.1,D1.2 ; Data unit mismatch, error!
Is there a way to express this with cgen? I have tried using (error) to
notify the user about this but cgen_rtx_error is not defined by opcodes
and I don't really know if it's possible to define it appropriately.