Re: [RFA:] Fix breakage of manually building SID CPU

[Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>]

> Date: Tue, 14 Mar 2006 17:48:43 -0500
> From: "Frank Ch. Eigler" <fche@redhat.com>

> > (delay 1 (set pc something))
> > was already implemented and working for SIM (fr30 uses it). [...]
> 
> I'm curious how exactly that works.  fr30 isn't in src/sim/ at the
> moment, is it?

Not sure what you mean by "exactly", but it works.  Even as per
the documentation!  See src/sim/cris and src/cpu/cris.cpu.

> > (set (delay 1 pc) something)
> > was only implemtned for SID.
> 
> I recall now that when we built support for a nasty open-pipelined
> machine, this notational change made sense, since it was only register
> sets that were "delayable", not general RTL expressions.

Judging from the documentation, I guess the "only" refers to the
CGEN-SID delay support.  If the latter, I don't mind very much
changing the port, if there can be sim support as well (Someone
writing it, or perhaps Someone handholding me through
implementing it), or (worse) some test-conditional applicable
for defining a pmacro with differing contents (see
src/cpu/mt.cpu:dset).

brgds, H-P