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Re: [RFA:] Fix breakage of manually building SID CPU


> Date: Wed, 15 Mar 2006 01:20:06 +0100
> From: Hans-Peter Nilsson <hp@axis.com>
> > Date: Tue, 14 Mar 2006 17:48:43 -0500
> > From: "Frank Ch. Eigler" <fche@redhat.com>
> 
> > > (delay 1 (set pc something))
> > > was already implemented and working for SIM (fr30 uses it). [...]

(FWIW, it certainly worked for SID too, some time ago.)

> > > (set (delay 1 pc) something)
> > > was only implemtned for SID.
> > 
> > I recall now that when we built support for a nasty open-pipelined
> > machine, this notational change made sense, since it was only register
> > sets that were "delayable", not general RTL expressions.
> 
> Judging from the documentation, I guess the "only" refers to the
> CGEN-SID delay support.  If the latter, I don't mind very much
> changing the port, if there can be sim support as well

Seems the implementation has introduced a false assumption.
Changing the cris.cpu file with the patch below and retrying as
per previous description I sent, results in:

./utils-cgen.scm:167:15: In procedure error in expression (apply error (cons # arg)):
./utils-cgen.scm:167:15: delayed operand in a non-parallel cpu:
ABORT: (misc-error)

So, uh, why would only parallel CPUs have delay-slots?  Or do we
actually have differing perceptions and definitions of what a
"delay" is?  Supposing that those definitions are mergeable,
would it be ok to put back support for the "old" definition in
SID-CGEN?  If not, what can be done?

Index: cris.cpu
===================================================================
RCS file: /cvs/src/src/cpu/cris.cpu,v
retrieving revision 1.5
diff -p -u -r1.5 cris.cpu
--- cris.cpu	6 Dec 2005 21:48:28 -0000	1.5
+++ cris.cpu	15 Mar 2006 01:01:25 -0000
@@ -306,6 +306,8 @@
 	((Pd INT -1)) ())
 )
 
+(define-pmacro (dset dest src) (set (delay 1 dest) src))
+
 (define-pmacro (crisv32-timing-destreg d)
   "Timing for instructions running on a crisv32 model"
   ((crisv32
@@ -2629,7 +2631,7 @@
    ((SI retaddr))
    (set retaddr Ps)
    (reset-x-p)
-   (delay 1 (set pc retaddr)))
+   (dset pc retaddr))
 )
 
 ; MOVE    [Rs],Pd         [ Pd | 10100011 | Rs ]
@@ -3991,8 +3993,7 @@
 
    (reset-x-p)
    (if truthval
-       (delay 1
-	      (set pc o-pcrel))))
+       (dset pc o-pcrel)))
  (.splice (.unsplice (simplecris-timing))
 	  (crisv32 (unit u-branch) (unit u-exec)))
 )
@@ -4004,8 +4005,7 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (set pc o-pcrel)))
+   (dset pc o-pcrel))
  ((crisv32 (unit u-jump) (unit u-exec)))
 )
 
@@ -4028,8 +4028,7 @@
 
    (reset-x-p)
    (if truthval
-       (delay 1
-	      (set pc o-word-pcrel))))
+       (dset pc o-word-pcrel)))
  (.splice
   (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec))))
   (crisv32 (unit u-const16) (unit u-branch) (unit u-exec)))
@@ -4042,8 +4041,7 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (set pc o-word-pcrel)))
+   (dset pc o-word-pcrel))
  (.splice
   (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec))))
   (crisv32 (unit u-const16) (unit u-jump) (unit u-exec)))
@@ -4063,11 +4061,8 @@
        ; used in the v32 trampoline.  See comment at bdapqpc.
        ; CGEN-FIXME: can't use (regno srp) [== (regno (reg h-sr 11))]
        (c-call VOID "cris_flush_simulator_decode_cache" pc))
-   (delay 1
-	  (sequence
-	    ()
-	    (set Pd (add SI pc 4))
-	    (set pc Rs))))
+   (dset Pd (add SI pc 4))
+   (dset pc Rs))
  ((crisv32 (unit u-jump-r) (unit u-jump) (unit u-exec)))
 )
 ; Same semantics in pre-V32, except no delay-slot.
@@ -4093,11 +4088,8 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (sequence
-	    ()
-	    (set Pd (add SI pc 8))
-	    (set pc const32))))
+   (dset Pd (add SI pc 8))
+   (dset pc const32))
  ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec)))
 )
 
@@ -4134,8 +4126,7 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (set pc Ps)))
+   (dset pc Ps))
  ((crisv32 (unit u-jump-sr)
 	   (unit u-exec)))
 )
@@ -4149,11 +4140,8 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (sequence
-	    ()
-	    (set Pd (add SI pc 8))
-	    (set pc const32-pcrel))))
+   (dset Pd (add SI pc 8))
+   (dset pc const32-pcrel))
  ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec)))
 )
 
@@ -4166,11 +4154,8 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (sequence
-	    ()
-	    (set Pd (add SI pc 8))
-	    (set pc Rs))))
+   (dset Pd (add SI pc 8))
+   (dset pc Rs))
  ((crisv32 (unit u-jump-r) (unit u-skip4) (unit u-jump) (unit u-exec)))
 )
 
@@ -4183,11 +4168,8 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (sequence
-	    ()
-	    (set Pd (add SI pc 12))
-	    (set pc const32))))
+   (dset Pd (add SI pc 12))
+   (dset pc const32))
  ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec)))
 )
 
@@ -4200,11 +4182,8 @@
  (sequence
    ()
    (reset-x-p)
-   (delay 1
-	  (sequence
-	    ()
-	    (set Pd (add SI pc 12))
-	    (set pc const32-pcrel))))
+   (dset Pd (add SI pc 12))
+   (dset pc const32-pcrel))
  ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec)))
 )
 

brgds, H-P


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