Re: Simulator: base_insn and insn in decode.c

[Dave Brolley <brolley at redhat dot com>]

Ronald Hecht wrote:

> I switched to the SID framework. I found it easier to create a new 
> target. The disassemby works better as it calls this disassembler code 
> in src/opcodes. But I'm still in trouble with decode.cxx. It looks the 
> same as in sim. I'n my opinion the entire_insn should alwasy be left 
> aligned and not right_aligned as it is now. Base_insn should have the 
> same alignment. I think this way it is easier to support variable 
> sized instructions.
I've been looking at what other ports do and it seems that most are able 
to pass the same value base_insn and entire_insn because the opcode bits 
are scattered throughout the insns. The ones which aren't so lucky do 
one of two things:

1) Write some ugly code which examines the base_insn bits in order to 
decide how to position entire_insn.

2) Set base-insn-bitsize in the define-isa of the .cpu file to be the 
size of the largest insn. For SID, base_insn and entire_insn can then be 
passed identically as the insn bits aligned at the 'base-insn-bitsize' 
bit. For example, in your case, the max insn length appears to be 24, so 
you could simply read 3 bytes individually (to avoid endianness 
problems) and place them sequentially in the low order bytes of 
base_insn and entire_insn.

Barring some redesign of the interface as has been discussed, I don't 
see any other options for you.

Dave