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[patch][rfc] New Port: Toshiba Media Processor (MeP)
- From: Dave Brolley <brolley at redhat dot com>
- To: cgen at sources dot redhat dot com
- Date: Thu, 18 Jan 2007 15:00:56 -0500
- Subject: [patch][rfc] New Port: Toshiba Media Processor (MeP)
Hi,
Attached are .cpu files making up the description of the Toshiba Media
Processor. This port has been in house at Red Hat since 2001, but
Toshiba has now given us the go ahead to contribute it. This cpu
description is used to generate parts of opcodes, sid and gcc for MeP.
I will be the maintainer of this port and am seeking approval to commit it.
Dave
; Toshiba MeP AVC Coprocessor description. -*- Scheme -*-
; Copyright (C) 2005 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
;
; This file was customized based upon the output of a2cgen 0.42
;------------------------------------------------------------------------------
; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
; specified below for each ME_MODULE using this coprocessor.
; This coprocessor requires 16 and 32 bit insns.
;------------------------------------------------------------------------------
; begin-isas
(define-pmacro avc-core-isa () (ISA ext_core1))
(define-pmacro avc-16-isa () (ISA ext_cop1_16))
(define-pmacro avc-32-isa () (ISA ext_cop1_32))
(define-pmacro all-avc-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32))
; end-isas
(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni xname xcomment (.splice (.unsplice xattrs) avc-core-isa) xsyntax xformat xsemantics xtiming))
(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni xname xcomment (.splice (.unsplice xattrs) avc-16-isa) xsyntax xformat xsemantics xtiming))
(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni xname xcomment (.splice (.unsplice xattrs) avc-32-isa) xsyntax xformat xsemantics xtiming))
; register definitions
; ---------------------
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-cr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
(name h-cr-avc)
(comment "32-bit coprocessor registers for avc coprocessor")
(attrs VIRTUAL all-avc-isas)
(type register SI (32))
(set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
(get (index) (trunc SI (c-call DI "h_cr64_get" index)))
(indices keyword "$c" (.map -reg-pair (.iota 8)))
)
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-ccr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
(name h-ccr-avc)
(comment "Coprocessor control registers for avc coprocessor")
(attrs VIRTUAL all-avc-isas)
(type register SI (64))
(set (index newval) (c-call VOID "h_ccr_set" index newval))
(get (index) (c-call SI "h_ccr_get" index))
(indices keyword ""
(.splice
($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0)
($cbcr 1)
(.unsplice (.map -ccr-reg-pair (.iota 6)))
)
)
)
(dnop avccopCCR5 "Audio Copro Accumulator" (all-avc-isas) h-ccr 5)
(dnop avccopCCR4 "Audio Copro Accumulator" (all-avc-isas) h-ccr 4)
(dnop avccopCCR3 "Audio Copro Accumulator" (all-avc-isas) h-ccr 3)
(dnop avccopCCR2 "Audio Copro Accumulator" (all-avc-isas) h-ccr 2)
(dnop avccopCCR1 "Audio Copro Branch Condition Register" (all-avc-isas) h-ccr 1)
(dnop avccopCCR0 "Audio Copro Shift-Amount Register" (all-avc-isas) h-ccr 0)
; instruction field and operand definitions
(dnf f-avc-v3sub4u0 "sub opecode field" (avc-32-isa) 0 4)
(dnf f-avc-v1sub4u0 "sub opecode field" (avc-16-isa) 0 4)
(dnf f-avc-v3Rn "register field" (avc-32-isa) 4 4)
(dnop avcv3Rn "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rn)
(dnf f-avc-v3CCRn "register field" (avc-32-isa) 4 4)
(define-full-operand avcv3CCRn "the operand definition" (avc-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc-v3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ())
(df f-avc-v3Imm16s4x24e32-hi "split immediate field hi" (avc-32-isa) 4 8 INT #f #f)
(df f-avc-v3Imm16s4x24e32-lo "split immediate field lo" (avc-32-isa) 24 8 UINT #f #f)
(define-multi-ifield
(name f-avc-v3Imm16s4x24e32)
(comment "split immediate field")
(attrs avc-32-isa)
(mode INT)
(subfields f-avc-v3Imm16s4x24e32-hi f-avc-v3Imm16s4x24e32-lo)
(insert (sequence ()
(set (ifield f-avc-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc-v3Imm16s4x24e32) 8))
(set (ifield f-avc-v3Imm16s4x24e32-lo) (and (ifield f-avc-v3Imm16s4x24e32) #xff))))
(extract (set (ifield f-avc-v3Imm16s4x24e32)
(or (sll (ifield f-avc-v3Imm16s4x24e32-hi) 8) (ifield f-avc-v3Imm16s4x24e32-lo))))
)
(dnop avcv3Imm16s4x24e32 "the operand definition" (avc-32-isa) h-sint f-avc-v3Imm16s4x24e32)
(dnf f-avc-v3CRn "register field" (avc-32-isa) 4 4)
(define-full-operand avcv3CRn "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRn ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1CRq "register field" (avc-16-isa) 4 4)
(define-full-operand avcv1CRq "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRq ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1sub4u4 "sub opecode field" (avc-16-isa) 4 4)
(dnf f-avc-c3Rn "register field" (avc-core-isa) 4 4)
(dnop avcc3Rn "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rn)
(dnf f-avc-c3CCRn "register field" (avc-core-isa) 4 4)
(define-full-operand avcc3CCRn "the operand definition" (avc-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc-c3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ())
(df f-avc-c3Imm16s4x24e32-hi "split immediate field hi" (avc-core-isa) 4 8 INT #f #f)
(df f-avc-c3Imm16s4x24e32-lo "split immediate field lo" (avc-core-isa) 24 8 UINT #f #f)
(define-multi-ifield
(name f-avc-c3Imm16s4x24e32)
(comment "split immediate field")
(attrs avc-core-isa)
(mode INT)
(subfields f-avc-c3Imm16s4x24e32-hi f-avc-c3Imm16s4x24e32-lo)
(insert (sequence ()
(set (ifield f-avc-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc-c3Imm16s4x24e32) 8))
(set (ifield f-avc-c3Imm16s4x24e32-lo) (and (ifield f-avc-c3Imm16s4x24e32) #xff))))
(extract (set (ifield f-avc-c3Imm16s4x24e32)
(or (sll (ifield f-avc-c3Imm16s4x24e32-hi) 8) (ifield f-avc-c3Imm16s4x24e32-lo))))
)
(dnop avcc3Imm16s4x24e32 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm16s4x24e32)
(dnf f-avc-c3CRn "register field" (avc-core-isa) 4 4)
(define-full-operand avcc3CRn "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRn ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u4 "sub opecode field" (avc-core-isa) 4 4)
(dnf f-avc-v3Rm "register field" (avc-32-isa) 8 4)
(dnop avcv3Rm "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rm)
(df f-avc-v1Imm5u8 "immediate field" (avc-16-isa) 8 5 UINT #f #f)
(dnop avcv1Imm5u8 "the operand definition" (avc-16-isa) h-uint f-avc-v1Imm5u8)
(df f-avc-v1Imm6s8 "immediate field" (avc-16-isa) 8 6 INT #f #f)
(dnop avcv1Imm6s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm6s8)
(df f-avc-v1Imm8s8 "immediate field" (avc-16-isa) 8 8 INT #f #f)
(dnop avcv1Imm8s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm8s8)
(dnf f-avc-v1CRp "register field" (avc-16-isa) 8 4)
(define-full-operand avcv1CRp "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRp ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1sub4u8 "sub opecode field" (avc-16-isa) 8 4)
(dnf f-avc-c3Rm "register field" (avc-core-isa) 8 4)
(dnop avcc3Rm "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rm)
(dnf f-avc-c3sub4u8 "sub opecode field" (avc-core-isa) 8 4)
(dnf f-avc-v3sub4u12 "sub opecode field" (avc-32-isa) 12 4)
(dnf f-avc-v1CRo "register field" (avc-16-isa) 12 4)
(define-full-operand avcv1CRo "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRo ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v1sub4u12 "sub opecode field" (avc-16-isa) 12 4)
(dnf f-avc-v1sub3u13 "sub opecode field" (avc-16-isa) 13 3)
(dnf f-avc-v1sub2u14 "sub opecode field" (avc-16-isa) 14 2)
(dnf f-avc-v3sub4u16 "sub opecode field" (avc-32-isa) 16 4)
(dnf f-avc-c3sub4u16 "sub opecode field" (avc-core-isa) 16 4)
(dnf f-avc-v3CRq "register field" (avc-32-isa) 20 4)
(define-full-operand avcv3CRq "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRq ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-v3sub4u20 "sub opecode field" (avc-32-isa) 20 4)
(dnf f-avc-c3CRq "register field" (avc-core-isa) 20 4)
(define-full-operand avcc3CRq "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRq ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u20 "sub opecode field" (avc-core-isa) 20 4)
(dnf f-avc-v3sub4u24 "sub opecode field" (avc-32-isa) 24 4)
(df f-avc-c3Imm5u24 "immediate field" (avc-core-isa) 24 5 UINT #f #f)
(dnop avcc3Imm5u24 "the operand definition" (avc-core-isa) h-uint f-avc-c3Imm5u24)
(df f-avc-c3Imm6s24 "immediate field" (avc-core-isa) 24 6 INT #f #f)
(dnop avcc3Imm6s24 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm6s24)
(dnf f-avc-c3CRp "register field" (avc-core-isa) 24 4)
(define-full-operand avcc3CRp "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRp ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u24 "sub opecode field" (avc-core-isa) 24 4)
(dnf f-avc-v3sub4u28 "sub opecode field" (avc-32-isa) 28 4)
(dnf f-avc-c3CRo "register field" (avc-core-isa) 28 4)
(define-full-operand avcc3CRo "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRo ((parse "avc_cr") (print "avc_cr")) () ())
(dnf f-avc-c3sub4u28 "sub opecode field" (avc-core-isa) 28 4)
(dnf f-avc-c3sub3u29 "sub opecode field" (avc-core-isa) 29 3)
(dnf f-avc-c3sub2u30 "sub opecode field" (avc-core-isa) 30 2)
; instruction definitions
(dncpi cnop_avc_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop"))
"cnop"
(+ MAJ_15 (f-sub4 7) (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(c-call "check_option_cp" pc)
())
(dncpi cmov1_avc_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1"))
"cmov $avcc3CRn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3CRn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRn avcc3Rm)
)
())
(dncpi cmov2_avc_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2"))
"cmov $avcc3Rm,$avcc3CRn"
(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CRn (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3Rm avcc3CRn)
)
())
(dncpi cmovi_avc_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi"))
"cmovi $avcc3CRq,$avcc3Imm16s4x24e32"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm16s4x24e32 (f-avc-c3sub4u16 #xe))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (ext SI avcc3Imm16s4x24e32))
)
())
(dncpi cmovc1_avc_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1"))
"cmovc $avcc3CCRn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3CCRn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CCRn avcc3Rm)
)
())
(dncpi cmovc2_avc_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2"))
"cmovc $avcc3Rm,$avcc3CCRn"
(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CCRn (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcc3Rm avcc3CCRn)
)
())
(dncpi cmov_avc_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov"))
"cmov $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq avcc3CRp)
)
())
(dncpi cadd3_avc_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3"))
"cadd3 $avcc3CRo,$avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRo avcc3CRq avcc3CRp (f-avc-c3sub4u16 #x3) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRo (add avcc3CRq avcc3CRp))
)
())
(dncpi caddi_avc_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi"))
"caddi $avcc3CRq,$avcc3Imm6s24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm6s24 (f-avc-c3sub2u30 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (add avcc3CRq (ext SI avcc3Imm6s24)))
)
())
(dncpi csub_avc_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub"))
"csub $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sub avcc3CRq avcc3CRp))
)
())
(dncpi cneg_avc_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg"))
"cneg $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (neg avcc3CRp))
)
())
(dncpi cextb_avc_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb"))
"cextb $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (ext SI (and QI (srl avcc3CRq 0) #xff)))
)
())
(dncpi cexth_avc_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth"))
"cexth $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (ext SI (and HI (srl avcc3CRq 0) #xffff)))
)
())
(dncpi cextub_avc_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub"))
"cextub $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x8) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (zext SI (and QI (srl avcc3CRq 0) #xff)))
)
())
(dncpi cextuh_avc_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh"))
"cextuh $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (zext SI (and HI (srl avcc3CRq 0) #xffff)))
)
())
(dncpi cscltz_avc_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz"))
"cscltz $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31)))
(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
)
)
())
(dncpi cldz_avc_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz"))
"cldz $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (and avcc3CRp #x80000000) (set avcc3CRq 0)
(if (and avcc3CRp #x40000000) (set avcc3CRq 1)
(if (and avcc3CRp #x20000000) (set avcc3CRq 2)
(if (and avcc3CRp #x10000000) (set avcc3CRq 3)
(if (and avcc3CRp #x8000000) (set avcc3CRq 4)
(if (and avcc3CRp #x4000000) (set avcc3CRq 5)
(if (and avcc3CRp #x2000000) (set avcc3CRq 6)
(if (and avcc3CRp #x1000000) (set avcc3CRq 7)
(if (and avcc3CRp #x800000) (set avcc3CRq 8)
(if (and avcc3CRp #x400000) (set avcc3CRq 9)
(if (and avcc3CRp #x200000) (set avcc3CRq 10)
(if (and avcc3CRp #x100000) (set avcc3CRq 11)
(if (and avcc3CRp #x80000) (set avcc3CRq 12)
(if (and avcc3CRp #x40000) (set avcc3CRq 13)
(if (and avcc3CRp #x20000) (set avcc3CRq 14)
(if (and avcc3CRp #x10000) (set avcc3CRq 15)
(if (and avcc3CRp #x8000) (set avcc3CRq 16)
(if (and avcc3CRp #x4000) (set avcc3CRq 17)
(if (and avcc3CRp #x2000) (set avcc3CRq 18)
(if (and avcc3CRp #x1000) (set avcc3CRq 19)
(if (and avcc3CRp #x800) (set avcc3CRq 20)
(if (and avcc3CRp #x400) (set avcc3CRq 21)
(if (and avcc3CRp #x200) (set avcc3CRq 22)
(if (and avcc3CRp #x100) (set avcc3CRq 23)
(if (and avcc3CRp #x80) (set avcc3CRq 24)
(if (and avcc3CRp #x40) (set avcc3CRq 25)
(if (and avcc3CRp #x20) (set avcc3CRq 26)
(if (and avcc3CRp #x10) (set avcc3CRq 27)
(if (and avcc3CRp #x8) (set avcc3CRq 28)
(if (and avcc3CRp #x4) (set avcc3CRq 29)
(if (and avcc3CRp #x2) (set avcc3CRq 30)
(if (and avcc3CRp #x1) (set avcc3CRq 31)
(set avcc3CRq 32)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
())
(dncpi cabs_avc_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs"))
"cabs $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (abs (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1))))
)
())
(dncpi cad1s_avc_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s"))
"cad1s $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (add avcc3CRq avcc3CRp) 1)))
(set avcc3CRq (subword SI (sra tmp0 1) 1))
)
())
(dncpi csb1s_avc_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s"))
"csb1s $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1)))
(set avcc3CRq (subword SI (sra tmp0 1) 1))
)
())
(dncpi cmin_avc_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin"))
"cmin $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
())
(dncpi cmax_avc_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax"))
"cmax $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (gt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
())
(dncpi cminu_avc_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu"))
"cminu $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (ltu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
())
(dncpi cmaxu_avc_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu"))
"cmaxu $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xb) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (gtu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq)
(set avcc3CRq avcc3CRp)
)
)
())
(dncpi cclipi_avc_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi"))
"cclipi $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x4) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0)
(sequence() (set tmp0 (sll 1 (sub avcc3Imm5u24 1)))
(set tmp1 (sub (subword SI tmp0 1) 1))
(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp1 1))) (set avcc3CRq (subword SI tmp1 1))
(if (lt (ext SI avcc3CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcc3CRq (neg (subword SI tmp0 1)))
(set avcc3CRq avcc3CRq)
)
)
)
)
)
())
(dncpi cclipiu_avc_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu"))
"cclipiu $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x5) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0)
(sequence() (set tmp0 (sub (sll 1 avcc3Imm5u24) 1))
(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp0 1))) (set avcc3CRq (subword SI tmp0 1))
(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avcc3CRq 0)
(set avcc3CRq avcc3CRq)
)
)
)
)
)
())
(dncpi cor_avc_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor"))
"cor $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (or avcc3CRq avcc3CRp))
)
())
(dncpi cand_avc_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand"))
"cand $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (and avcc3CRq avcc3CRp))
)
())
(dncpi cxor_avc_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor"))
"cxor $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (xor avcc3CRq avcc3CRp))
)
())
(dncpi cnor_avc_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor"))
"cnor $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (inv (or avcc3CRq avcc3CRp)))
)
())
(dncpi csra_avc_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra"))
"csra $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sra avcc3CRq (and QI (srl avcc3CRp 0) #x1f)))
)
())
(dncpi csrl_avc_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl"))
"csrl $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (srl avcc3CRq (and QI (srl avcc3CRp 0) #x1f)))
)
())
(dncpi csll_avc_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll"))
"csll $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sll avcc3CRq (and QI (srl avcc3CRp 0) #x1f)))
)
())
(dncpi csrai_avc_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai"))
"csrai $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x2) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sra avcc3CRq avcc3Imm5u24))
)
())
(dncpi csrli_avc_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli"))
"csrli $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x3) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (srl avcc3CRq avcc3Imm5u24))
)
())
(dncpi cslli_avc_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli"))
"cslli $avcc3CRq,$avcc3Imm5u24"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x6) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (sll avcc3CRq avcc3Imm5u24))
)
())
(dncpi cfsft_avc_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft"))
"cfsft $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avcc3CRq)) 32) (zext DI avcc3CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
())
(dncpi cfsfta0_avc_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0"))
"cfsfta0 $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
())
(dncpi cfsfta1_avc_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1"))
"cfsfta1 $avcc3CRq"
(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
())
(dncpi cmula0_avc_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0"))
"cmula0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat0)) (c-call "check_option_cp" pc)
(set concat0 (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))
(set avccopCCR2 (subword SI concat0 0))
(set avccopCCR3 (subword SI concat0 1))
)
())
(dncpi cmulua0_avc_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0"))
"cmulua0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat1)) (c-call "check_option_cp" pc)
(set concat1 (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))
(set avccopCCR2 (subword SI concat1 0))
(set avccopCCR3 (subword SI concat1 1))
)
())
(dncpi cnmula0_avc_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0"))
"cnmula0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat2)) (c-call "check_option_cp" pc)
(set concat2 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat2 0))
(set avccopCCR3 (subword SI concat2 1))
)
())
(dncpi cmada0_avc_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0"))
"cmada0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat3)) (c-call "check_option_cp" pc)
(set concat3 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat3 0))
(set avccopCCR3 (subword SI concat3 1))
)
())
(dncpi cmadua0_avc_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0"))
"cmadua0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat4)) (c-call "check_option_cp" pc)
(set concat4 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat4 0))
(set avccopCCR3 (subword SI concat4 1))
)
())
(dncpi cmsba0_avc_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0"))
"cmsba0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat5)) (c-call "check_option_cp" pc)
(set concat5 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat5 0))
(set avccopCCR3 (subword SI concat5 1))
)
())
(dncpi cmsbua0_avc_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0"))
"cmsbua0 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat6)) (c-call "check_option_cp" pc)
(set concat6 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR2 (subword SI concat6 0))
(set avccopCCR3 (subword SI concat6 1))
)
())
(dncpi cmula1_avc_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1"))
"cmula1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat7)) (c-call "check_option_cp" pc)
(set concat7 (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))
(set avccopCCR4 (subword SI concat7 0))
(set avccopCCR5 (subword SI concat7 1))
)
())
(dncpi cmulua1_avc_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1"))
"cmulua1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat8)) (c-call "check_option_cp" pc)
(set concat8 (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))
(set avccopCCR4 (subword SI concat8 0))
(set avccopCCR5 (subword SI concat8 1))
)
())
(dncpi cnmula1_avc_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1"))
"cnmula1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat9)) (c-call "check_option_cp" pc)
(set concat9 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat9 0))
(set avccopCCR5 (subword SI concat9 1))
)
())
(dncpi cmada1_avc_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1"))
"cmada1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat10)) (c-call "check_option_cp" pc)
(set concat10 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat10 0))
(set avccopCCR5 (subword SI concat10 1))
)
())
(dncpi cmadua1_avc_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1"))
"cmadua1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat11)) (c-call "check_option_cp" pc)
(set concat11 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat11 0))
(set avccopCCR5 (subword SI concat11 1))
)
())
(dncpi cmsba1_avc_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1"))
"cmsba1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat12)) (c-call "check_option_cp" pc)
(set concat12 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat12 0))
(set avccopCCR5 (subword SI concat12 1))
)
())
(dncpi cmsbua1_avc_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1"))
"cmsbua1 $avcc3CRq,$avcc3CRp"
(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0))
(sequence((DI concat13)) (c-call "check_option_cp" pc)
(set concat13 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp))))
(set avccopCCR4 (subword SI concat13 0))
(set avccopCCR5 (subword SI concat13 1))
)
())
(dncpi xmula0_avc_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0"))
"xmula0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat14)) (c-call "check_option_cp" pc)
(set concat14 (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))
(set avccopCCR2 (subword SI concat14 0))
(set avccopCCR3 (subword SI concat14 1))
)
())
(dncpi xmulua0_avc_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0"))
"xmulua0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat15)) (c-call "check_option_cp" pc)
(set concat15 (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))
(set avccopCCR2 (subword SI concat15 0))
(set avccopCCR3 (subword SI concat15 1))
)
())
(dncpi xnmula0_avc_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0"))
"xnmula0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat16)) (c-call "check_option_cp" pc)
(set concat16 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat16 0))
(set avccopCCR3 (subword SI concat16 1))
)
())
(dncpi xmada0_avc_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0"))
"xmada0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat17)) (c-call "check_option_cp" pc)
(set concat17 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat17 0))
(set avccopCCR3 (subword SI concat17 1))
)
())
(dncpi xmadua0_avc_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0"))
"xmadua0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat18)) (c-call "check_option_cp" pc)
(set concat18 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat18 0))
(set avccopCCR3 (subword SI concat18 1))
)
())
(dncpi xmsba0_avc_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0"))
"xmsba0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat19)) (c-call "check_option_cp" pc)
(set concat19 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat19 0))
(set avccopCCR3 (subword SI concat19 1))
)
())
(dncpi xmsbua0_avc_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0"))
"xmsbua0 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat20)) (c-call "check_option_cp" pc)
(set concat20 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR2 (subword SI concat20 0))
(set avccopCCR3 (subword SI concat20 1))
)
())
(dncpi xmula1_avc_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1"))
"xmula1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat21)) (c-call "check_option_cp" pc)
(set concat21 (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))
(set avccopCCR4 (subword SI concat21 0))
(set avccopCCR5 (subword SI concat21 1))
)
())
(dncpi xmulua1_avc_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1"))
"xmulua1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat22)) (c-call "check_option_cp" pc)
(set concat22 (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))
(set avccopCCR4 (subword SI concat22 0))
(set avccopCCR5 (subword SI concat22 1))
)
())
(dncpi xnmula1_avc_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1"))
"xnmula1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat23)) (c-call "check_option_cp" pc)
(set concat23 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat23 0))
(set avccopCCR5 (subword SI concat23 1))
)
())
(dncpi xmada1_avc_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1"))
"xmada1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat24)) (c-call "check_option_cp" pc)
(set concat24 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat24 0))
(set avccopCCR5 (subword SI concat24 1))
)
())
(dncpi xmadua1_avc_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1"))
"xmadua1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat25)) (c-call "check_option_cp" pc)
(set concat25 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat25 0))
(set avccopCCR5 (subword SI concat25 1))
)
())
(dncpi xmsba1_avc_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1"))
"xmsba1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat26)) (c-call "check_option_cp" pc)
(set concat26 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat26 0))
(set avccopCCR5 (subword SI concat26 1))
)
())
(dncpi xmsbua1_avc_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1"))
"xmsbua1 $avcc3Rn,$avcc3Rm"
(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc))
(sequence((DI concat27)) (c-call "check_option_cp" pc)
(set concat27 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm))))
(set avccopCCR4 (subword SI concat27 0))
(set avccopCCR5 (subword SI concat27 1))
)
())
(dn16i cnop_avc_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop"))
"cnop"
(+ (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u4 #x0) (f-avc-v1sub4u0 #x0))
(c-call "check_option_cp" pc)
())
(dnmi cpnop16_avc_v1 "cpnop16"
(avc-16-isa NO-DIS)
"cpnop16"
(emit cnop_avc_v1)
)
(dn16i cmov_avc_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov"))
"cmov $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq avcv1CRp)
)
())
(dn16i cmovi_avc_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi"))
"cmovi $avcv1CRq,$avcv1Imm8s8"
(+ avcv1CRq avcv1Imm8s8 (f-avc-v1sub4u0 #x2))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (ext SI avcv1Imm8s8))
)
())
(dn16i cadd3_avc_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3"))
"cadd3 $avcv1CRo,$avcv1CRq,$avcv1CRp"
(+ avcv1CRo avcv1CRq avcv1CRp (f-avc-v1sub4u0 #x3))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRo (add avcv1CRq avcv1CRp))
)
())
(dn16i caddi_avc_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi"))
"caddi $avcv1CRq,$avcv1Imm6s8"
(+ avcv1CRq avcv1Imm6s8 (f-avc-v1sub2u14 #x0) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (add avcv1CRq (ext SI avcv1Imm6s8)))
)
())
(dn16i csub_avc_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub"))
"csub $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sub avcv1CRq avcv1CRp))
)
())
(dn16i cneg_avc_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg"))
"cneg $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (neg avcv1CRp))
)
())
(dn16i cextb_avc_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb"))
"cextb $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (ext SI (and QI (srl avcv1CRq 0) #xff)))
)
())
(dn16i cexth_avc_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth"))
"cexth $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x2) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (ext SI (and HI (srl avcv1CRq 0) #xffff)))
)
())
(dn16i cextub_avc_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub"))
"cextub $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x8) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (zext SI (and QI (srl avcv1CRq 0) #xff)))
)
())
(dn16i cextuh_avc_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh"))
"cextuh $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (zext SI (and HI (srl avcv1CRq 0) #xffff)))
)
())
(dn16i cscltz_avc_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz"))
"cscltz $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31)))
(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
)
)
())
(dn16i cldz_avc_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz"))
"cldz $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (and avcv1CRp #x80000000) (set avcv1CRq 0)
(if (and avcv1CRp #x40000000) (set avcv1CRq 1)
(if (and avcv1CRp #x20000000) (set avcv1CRq 2)
(if (and avcv1CRp #x10000000) (set avcv1CRq 3)
(if (and avcv1CRp #x8000000) (set avcv1CRq 4)
(if (and avcv1CRp #x4000000) (set avcv1CRq 5)
(if (and avcv1CRp #x2000000) (set avcv1CRq 6)
(if (and avcv1CRp #x1000000) (set avcv1CRq 7)
(if (and avcv1CRp #x800000) (set avcv1CRq 8)
(if (and avcv1CRp #x400000) (set avcv1CRq 9)
(if (and avcv1CRp #x200000) (set avcv1CRq 10)
(if (and avcv1CRp #x100000) (set avcv1CRq 11)
(if (and avcv1CRp #x80000) (set avcv1CRq 12)
(if (and avcv1CRp #x40000) (set avcv1CRq 13)
(if (and avcv1CRp #x20000) (set avcv1CRq 14)
(if (and avcv1CRp #x10000) (set avcv1CRq 15)
(if (and avcv1CRp #x8000) (set avcv1CRq 16)
(if (and avcv1CRp #x4000) (set avcv1CRq 17)
(if (and avcv1CRp #x2000) (set avcv1CRq 18)
(if (and avcv1CRp #x1000) (set avcv1CRq 19)
(if (and avcv1CRp #x800) (set avcv1CRq 20)
(if (and avcv1CRp #x400) (set avcv1CRq 21)
(if (and avcv1CRp #x200) (set avcv1CRq 22)
(if (and avcv1CRp #x100) (set avcv1CRq 23)
(if (and avcv1CRp #x80) (set avcv1CRq 24)
(if (and avcv1CRp #x40) (set avcv1CRq 25)
(if (and avcv1CRp #x20) (set avcv1CRq 26)
(if (and avcv1CRp #x10) (set avcv1CRq 27)
(if (and avcv1CRp #x8) (set avcv1CRq 28)
(if (and avcv1CRp #x4) (set avcv1CRq 29)
(if (and avcv1CRp #x2) (set avcv1CRq 30)
(if (and avcv1CRp #x1) (set avcv1CRq 31)
(set avcv1CRq 32)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
())
(dn16i cabs_avc_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs"))
"cabs $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (abs (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1))))
)
())
(dn16i cad1s_avc_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s"))
"cad1s $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (add avcv1CRq avcv1CRp) 1)))
(set avcv1CRq (subword SI (sra tmp0 1) 1))
)
())
(dn16i csb1s_avc_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s"))
"csb1s $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1)))
(set avcv1CRq (subword SI (sra tmp0 1) 1))
)
())
(dn16i cmin_avc_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin"))
"cmin $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
())
(dn16i cmax_avc_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax"))
"cmax $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (gt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
())
(dn16i cminu_avc_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu"))
"cminu $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (ltu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
())
(dn16i cmaxu_avc_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu"))
"cmaxu $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xb) (f-avc-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (gtu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq)
(set avcv1CRq avcv1CRp)
)
)
())
(dn16i cclipi_avc_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi"))
"cclipi $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x4) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0)
(sequence() (set tmp0 (sll 1 (sub avcv1Imm5u8 1)))
(set tmp1 (sub (subword SI tmp0 1) 1))
(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp1 1))) (set avcv1CRq (subword SI tmp1 1))
(if (lt (ext SI avcv1CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcv1CRq (neg (subword SI tmp0 1)))
(set avcv1CRq avcv1CRq)
)
)
)
)
)
())
(dn16i cclipiu_avc_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu"))
"cclipiu $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x5) (f-avc-v1sub4u0 #x5))
(sequence((DI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0)
(sequence() (set tmp0 (sub (sll 1 avcv1Imm5u8) 1))
(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp0 1))) (set avcv1CRq (subword SI tmp0 1))
(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avcv1CRq 0)
(set avcv1CRq avcv1CRq)
)
)
)
)
)
())
(dn16i cor_avc_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor"))
"cor $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (or avcv1CRq avcv1CRp))
)
())
(dn16i cand_avc_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand"))
"cand $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (and avcv1CRq avcv1CRp))
)
())
(dn16i cxor_avc_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor"))
"cxor $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (xor avcv1CRq avcv1CRp))
)
())
(dn16i cnor_avc_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor"))
"cnor $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (inv (or avcv1CRq avcv1CRp)))
)
())
(dn16i csra_avc_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra"))
"csra $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sra avcv1CRq (and QI (srl avcv1CRp 0) #x1f)))
)
())
(dn16i csrl_avc_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl"))
"csrl $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (srl avcv1CRq (and QI (srl avcv1CRp 0) #x1f)))
)
())
(dn16i csll_avc_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll"))
"csll $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sll avcv1CRq (and QI (srl avcv1CRp 0) #x1f)))
)
())
(dn16i csrai_avc_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai"))
"csrai $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x2) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sra avcv1CRq avcv1Imm5u8))
)
())
(dn16i csrli_avc_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli"))
"csrli $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x3) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (srl avcv1CRq avcv1Imm5u8))
)
())
(dn16i cslli_avc_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli"))
"cslli $avcv1CRq,$avcv1Imm5u8"
(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x6) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (sll avcv1CRq avcv1Imm5u8))
)
())
(dn16i cfsft_avc_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft"))
"cfsft $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avcv1CRq)) 32) (zext DI avcv1CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
())
(dn16i cfsfta0_avc_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0"))
"cfsfta0 $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
())
(dn16i cfsfta1_avc_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1"))
"cfsfta1 $avcv1CRq"
(+ avcv1CRq (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0))
)
())
(dn16i cmula0_avc_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0"))
"cmula0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x4))
(sequence((DI concat28)) (c-call "check_option_cp" pc)
(set concat28 (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))
(set avccopCCR2 (subword SI concat28 0))
(set avccopCCR3 (subword SI concat28 1))
)
())
(dn16i cmulua0_avc_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0"))
"cmulua0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x4))
(sequence((DI concat29)) (c-call "check_option_cp" pc)
(set concat29 (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))
(set avccopCCR2 (subword SI concat29 0))
(set avccopCCR3 (subword SI concat29 1))
)
())
(dn16i cnmula0_avc_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0"))
"cnmula0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x4))
(sequence((DI concat30)) (c-call "check_option_cp" pc)
(set concat30 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat30 0))
(set avccopCCR3 (subword SI concat30 1))
)
())
(dn16i cmada0_avc_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0"))
"cmada0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x4))
(sequence((DI concat31)) (c-call "check_option_cp" pc)
(set concat31 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat31 0))
(set avccopCCR3 (subword SI concat31 1))
)
())
(dn16i cmadua0_avc_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0"))
"cmadua0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x4))
(sequence((DI concat32)) (c-call "check_option_cp" pc)
(set concat32 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat32 0))
(set avccopCCR3 (subword SI concat32 1))
)
())
(dn16i cmsba0_avc_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0"))
"cmsba0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x4))
(sequence((DI concat33)) (c-call "check_option_cp" pc)
(set concat33 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat33 0))
(set avccopCCR3 (subword SI concat33 1))
)
())
(dn16i cmsbua0_avc_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0"))
"cmsbua0 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x4))
(sequence((DI concat34)) (c-call "check_option_cp" pc)
(set concat34 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR2 (subword SI concat34 0))
(set avccopCCR3 (subword SI concat34 1))
)
())
(dn16i cmula1_avc_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1"))
"cmula1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x4))
(sequence((DI concat35)) (c-call "check_option_cp" pc)
(set concat35 (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))
(set avccopCCR4 (subword SI concat35 0))
(set avccopCCR5 (subword SI concat35 1))
)
())
(dn16i cmulua1_avc_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1"))
"cmulua1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x4))
(sequence((DI concat36)) (c-call "check_option_cp" pc)
(set concat36 (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))
(set avccopCCR4 (subword SI concat36 0))
(set avccopCCR5 (subword SI concat36 1))
)
())
(dn16i cnmula1_avc_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1"))
"cnmula1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x4))
(sequence((DI concat37)) (c-call "check_option_cp" pc)
(set concat37 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat37 0))
(set avccopCCR5 (subword SI concat37 1))
)
())
(dn16i cmada1_avc_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1"))
"cmada1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x4))
(sequence((DI concat38)) (c-call "check_option_cp" pc)
(set concat38 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat38 0))
(set avccopCCR5 (subword SI concat38 1))
)
())
(dn16i cmadua1_avc_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1"))
"cmadua1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x4))
(sequence((DI concat39)) (c-call "check_option_cp" pc)
(set concat39 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat39 0))
(set avccopCCR5 (subword SI concat39 1))
)
())
(dn16i cmsba1_avc_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1"))
"cmsba1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x4))
(sequence((DI concat40)) (c-call "check_option_cp" pc)
(set concat40 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat40 0))
(set avccopCCR5 (subword SI concat40 1))
)
())
(dn16i cmsbua1_avc_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1"))
"cmsbua1 $avcv1CRq,$avcv1CRp"
(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x4))
(sequence((DI concat41)) (c-call "check_option_cp" pc)
(set concat41 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp))))
(set avccopCCR4 (subword SI concat41 0))
(set avccopCCR5 (subword SI concat41 1))
)
())
(dn32i cmov1_avc_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1"))
"cmov $avcv3CRn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3CRn avcv3Rm)
)
())
(dn32i cmov2_avc_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2"))
"cmov $avcv3Rm,$avcv3CRn"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CRn (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3Rm avcv3CRn)
)
())
(dn32i cmovi_avc_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi"))
"cmovi $avcv3CRq,$avcv3Imm16s4x24e32"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRq avcv3Imm16s4x24e32 (f-avc-v3sub4u16 #xe))
(sequence() (c-call "check_option_cp" pc)
(set avcv3CRq (ext SI avcv3Imm16s4x24e32))
)
())
(dn32i cmovc1_avc_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1"))
"cmovc $avcv3CCRn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CCRn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3CCRn avcv3Rm)
)
())
(dn32i cmovc2_avc_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2"))
"cmovc $avcv3Rm,$avcv3CCRn"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CCRn (f-avc-v3sub4u28 #x3) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avcv3Rm avcv3CCRn)
)
())
(dn32i xmula0_avc_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0"))
"xmula0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat42)) (c-call "check_option_cp" pc)
(set concat42 (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))
(set avccopCCR2 (subword SI concat42 0))
(set avccopCCR3 (subword SI concat42 1))
)
())
(dn32i xmulua0_avc_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0"))
"xmulua0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat43)) (c-call "check_option_cp" pc)
(set concat43 (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))
(set avccopCCR2 (subword SI concat43 0))
(set avccopCCR3 (subword SI concat43 1))
)
())
(dn32i xnmula0_avc_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0"))
"xnmula0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat44)) (c-call "check_option_cp" pc)
(set concat44 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat44 0))
(set avccopCCR3 (subword SI concat44 1))
)
())
(dn32i xmada0_avc_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0"))
"xmada0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x4) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat45)) (c-call "check_option_cp" pc)
(set concat45 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat45 0))
(set avccopCCR3 (subword SI concat45 1))
)
())
(dn32i xmadua0_avc_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0"))
"xmadua0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x5) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat46)) (c-call "check_option_cp" pc)
(set concat46 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat46 0))
(set avccopCCR3 (subword SI concat46 1))
)
())
(dn32i xmsba0_avc_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0"))
"xmsba0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x6) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat47)) (c-call "check_option_cp" pc)
(set concat47 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat47 0))
(set avccopCCR3 (subword SI concat47 1))
)
())
(dn32i xmsbua0_avc_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0"))
"xmsbua0 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x7) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat48)) (c-call "check_option_cp" pc)
(set concat48 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR2 (subword SI concat48 0))
(set avccopCCR3 (subword SI concat48 1))
)
())
(dn32i xmula1_avc_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1"))
"xmula1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x8) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat49)) (c-call "check_option_cp" pc)
(set concat49 (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))
(set avccopCCR4 (subword SI concat49 0))
(set avccopCCR5 (subword SI concat49 1))
)
())
(dn32i xmulua1_avc_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1"))
"xmulua1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x9) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat50)) (c-call "check_option_cp" pc)
(set concat50 (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))
(set avccopCCR4 (subword SI concat50 0))
(set avccopCCR5 (subword SI concat50 1))
)
())
(dn32i xnmula1_avc_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1"))
"xnmula1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xa) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat51)) (c-call "check_option_cp" pc)
(set concat51 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat51 0))
(set avccopCCR5 (subword SI concat51 1))
)
())
(dn32i xmada1_avc_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1"))
"xmada1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xc) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat52)) (c-call "check_option_cp" pc)
(set concat52 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat52 0))
(set avccopCCR5 (subword SI concat52 1))
)
())
(dn32i xmadua1_avc_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1"))
"xmadua1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xd) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat53)) (c-call "check_option_cp" pc)
(set concat53 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat53 0))
(set avccopCCR5 (subword SI concat53 1))
)
())
(dn32i xmsba1_avc_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1"))
"xmsba1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xe) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat54)) (c-call "check_option_cp" pc)
(set concat54 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat54 0))
(set avccopCCR5 (subword SI concat54 1))
)
())
(dn32i xmsbua1_avc_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1"))
"xmsbua1 $avcv3Rn,$avcv3Rm"
(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xf) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc))
(sequence((DI concat55)) (c-call "check_option_cp" pc)
(set concat55 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm))))
(set avccopCCR4 (subword SI concat55 0))
(set avccopCCR5 (subword SI concat55 1))
)
())
; Toshiba MeP AVC2 Coprocessor description. -*- Scheme -*-
; Copyright (C) 2005 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
;
; This file was customized based upon the output of a2cgen 0.42
;------------------------------------------------------------------------------
; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
; specified below for each ME_MODULE using this coprocessor.
; This coprocessor requires 16 and 32 bit insns.
;------------------------------------------------------------------------------
; begin-isas
(define-pmacro avc2-core-isa () (ISA ext_core1))
(define-pmacro avc2-16-isa () (ISA ext_cop1_16))
(define-pmacro avc2-32-isa () (ISA ext_cop1_32))
(define-pmacro all-avc2-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32))
; end-isas
(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni xname xcomment (.splice (.unsplice xattrs) avc2-core-isa) xsyntax xformat xsemantics xtiming))
(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni xname xcomment (.splice (.unsplice xattrs) avc2-16-isa) xsyntax xformat xsemantics xtiming))
(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni xname xcomment (.splice (.unsplice xattrs) avc2-32-isa) xsyntax xformat xsemantics xtiming))
; register definitions
; ---------------------
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-cr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
(name h-cr-avc2)
(comment "32-bit coprocessor registers for avc2 coprocessor")
(attrs VIRTUAL all-avc2-isas)
(type register SI (32))
(set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
(get (index) (trunc SI (c-call DI "h_cr64_get" index)))
(indices keyword "$c" (.map -reg-pair (.iota 8)))
)
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-ccr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
(name h-ccr-avc2)
(comment "Coprocessor control registers for avc2 coprocessor")
(attrs VIRTUAL all-avc2-isas)
(type register SI (64))
(set (index newval) (c-call VOID "h_ccr_set" index newval))
(get (index) (c-call SI "h_ccr_get" index))
(indices keyword ""
(.splice
($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0)
($cbcr 1)
(.unsplice (.map -ccr-reg-pair (.iota 6)))
)
)
)
(dnop avc2copCCR5 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 5)
(dnop avc2copCCR4 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 4)
(dnop avc2copCCR3 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 3)
(dnop avc2copCCR2 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 2)
(dnop avc2copCCR1 "Audio Copro Branch Condition Register" (all-avc2-isas) h-ccr 1)
(dnop avc2copCCR0 "Audio Copro Shift-Amount Register" (all-avc2-isas) h-ccr 0)
; instruction field and operand definitions
(dnf f-avc2-v3sub4u0 "sub opecode field" (avc2-32-isa) 0 4)
(dnf f-avc2-v1sub4u0 "sub opecode field" (avc2-16-isa) 0 4)
(dnf f-avc2-v3Rn "register field" (avc2-32-isa) 4 4)
(dnop avc2v3Rn "the operand definition" (avc2-32-isa) h-gpr f-avc2-v3Rn)
(dnf f-avc2-v3CCRn "register field" (avc2-32-isa) 4 4)
(define-full-operand avc2v3CCRn "the operand definition" (avc2-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc2-v3CCRn ((parse "avc2_ccr") (print "avc2_ccr")) () ())
(df f-avc2-v3Imm16s4x24e32-hi "split immediate field hi" (avc2-32-isa) 4 8 INT #f #f)
(df f-avc2-v3Imm16s4x24e32-lo "split immediate field lo" (avc2-32-isa) 24 8 UINT #f #f)
(define-multi-ifield
(name f-avc2-v3Imm16s4x24e32)
(comment "split immediate field")
(attrs avc2-32-isa)
(mode INT)
(subfields f-avc2-v3Imm16s4x24e32-hi f-avc2-v3Imm16s4x24e32-lo)
(insert (sequence ()
(set (ifield f-avc2-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc2-v3Imm16s4x24e32) 8))
(set (ifield f-avc2-v3Imm16s4x24e32-lo) (and (ifield f-avc2-v3Imm16s4x24e32) #xff))))
(extract (set (ifield f-avc2-v3Imm16s4x24e32)
(or (sll (ifield f-avc2-v3Imm16s4x24e32-hi) 8) (ifield f-avc2-v3Imm16s4x24e32-lo))))
)
(dnop avc2v3Imm16s4x24e32 "the operand definition" (avc2-32-isa) h-sint f-avc2-v3Imm16s4x24e32)
(dnf f-avc2-v3CRn "register field" (avc2-32-isa) 4 4)
(define-full-operand avc2v3CRn "the operand definition" (avc2-32-isa) h-cr DFLT f-avc2-v3CRn ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-v1CRq "register field" (avc2-16-isa) 4 4)
(define-full-operand avc2v1CRq "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRq ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-v1sub4u4 "sub opecode field" (avc2-16-isa) 4 4)
(dnf f-avc2-c3Rn "register field" (avc2-core-isa) 4 4)
(dnop avc2c3Rn "the operand definition" (avc2-core-isa) h-gpr f-avc2-c3Rn)
(dnf f-avc2-c3CCRn "register field" (avc2-core-isa) 4 4)
(define-full-operand avc2c3CCRn "the operand definition" (avc2-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc2-c3CCRn ((parse "avc2_ccr") (print "avc2_ccr")) () ())
(df f-avc2-c3Imm16s4x24e32-hi "split immediate field hi" (avc2-core-isa) 4 8 INT #f #f)
(df f-avc2-c3Imm16s4x24e32-lo "split immediate field lo" (avc2-core-isa) 24 8 UINT #f #f)
(define-multi-ifield
(name f-avc2-c3Imm16s4x24e32)
(comment "split immediate field")
(attrs avc2-core-isa)
(mode INT)
(subfields f-avc2-c3Imm16s4x24e32-hi f-avc2-c3Imm16s4x24e32-lo)
(insert (sequence ()
(set (ifield f-avc2-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc2-c3Imm16s4x24e32) 8))
(set (ifield f-avc2-c3Imm16s4x24e32-lo) (and (ifield f-avc2-c3Imm16s4x24e32) #xff))))
(extract (set (ifield f-avc2-c3Imm16s4x24e32)
(or (sll (ifield f-avc2-c3Imm16s4x24e32-hi) 8) (ifield f-avc2-c3Imm16s4x24e32-lo))))
)
(dnop avc2c3Imm16s4x24e32 "the operand definition" (avc2-core-isa) h-sint f-avc2-c3Imm16s4x24e32)
(dnf f-avc2-c3CRn "register field" (avc2-core-isa) 4 4)
(define-full-operand avc2c3CRn "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRn ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-c3sub4u4 "sub opecode field" (avc2-core-isa) 4 4)
(dnf f-avc2-v3Rm "register field" (avc2-32-isa) 8 4)
(dnop avc2v3Rm "the operand definition" (avc2-32-isa) h-gpr f-avc2-v3Rm)
(df f-avc2-v1Imm6u8 "immediate field" (avc2-16-isa) 8 6 UINT #f #f)
(dnop avc2v1Imm6u8 "the operand definition" (avc2-16-isa) h-uint f-avc2-v1Imm6u8)
(df f-avc2-v1Imm5u8 "immediate field" (avc2-16-isa) 8 5 UINT #f #f)
(dnop avc2v1Imm5u8 "the operand definition" (avc2-16-isa) h-uint f-avc2-v1Imm5u8)
(df f-avc2-v1Imm6s8 "immediate field" (avc2-16-isa) 8 6 INT #f #f)
(dnop avc2v1Imm6s8 "the operand definition" (avc2-16-isa) h-sint f-avc2-v1Imm6s8)
(df f-avc2-v1Imm8s8 "immediate field" (avc2-16-isa) 8 8 INT #f #f)
(dnop avc2v1Imm8s8 "the operand definition" (avc2-16-isa) h-sint f-avc2-v1Imm8s8)
(dnf f-avc2-v1CRp "register field" (avc2-16-isa) 8 4)
(define-full-operand avc2v1CRp "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRp ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-v1sub4u8 "sub opecode field" (avc2-16-isa) 8 4)
(dnf f-avc2-c3Rm "register field" (avc2-core-isa) 8 4)
(dnop avc2c3Rm "the operand definition" (avc2-core-isa) h-gpr f-avc2-c3Rm)
(dnf f-avc2-c3sub4u8 "sub opecode field" (avc2-core-isa) 8 4)
(dnf f-avc2-v3sub4u12 "sub opecode field" (avc2-32-isa) 12 4)
(dnf f-avc2-v1CRo "register field" (avc2-16-isa) 12 4)
(define-full-operand avc2v1CRo "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRo ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-v1sub4u12 "sub opecode field" (avc2-16-isa) 12 4)
(dnf f-avc2-v1sub3u13 "sub opecode field" (avc2-16-isa) 13 3)
(dnf f-avc2-v1sub2u14 "sub opecode field" (avc2-16-isa) 14 2)
(dnf f-avc2-v3sub4u16 "sub opecode field" (avc2-32-isa) 16 4)
(dnf f-avc2-c3sub4u16 "sub opecode field" (avc2-core-isa) 16 4)
(dnf f-avc2-v3CRq "register field" (avc2-32-isa) 20 4)
(define-full-operand avc2v3CRq "the operand definition" (avc2-32-isa) h-cr DFLT f-avc2-v3CRq ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-v3sub4u20 "sub opecode field" (avc2-32-isa) 20 4)
(dnf f-avc2-c3CRq "register field" (avc2-core-isa) 20 4)
(define-full-operand avc2c3CRq "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRq ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-c3sub4u20 "sub opecode field" (avc2-core-isa) 20 4)
(dnf f-avc2-v3sub4u24 "sub opecode field" (avc2-32-isa) 24 4)
(df f-avc2-c3Imm6u24 "immediate field" (avc2-core-isa) 24 6 UINT #f #f)
(dnop avc2c3Imm6u24 "the operand definition" (avc2-core-isa) h-uint f-avc2-c3Imm6u24)
(df f-avc2-c3Imm5u24 "immediate field" (avc2-core-isa) 24 5 UINT #f #f)
(dnop avc2c3Imm5u24 "the operand definition" (avc2-core-isa) h-uint f-avc2-c3Imm5u24)
(df f-avc2-c3Imm6s24 "immediate field" (avc2-core-isa) 24 6 INT #f #f)
(dnop avc2c3Imm6s24 "the operand definition" (avc2-core-isa) h-sint f-avc2-c3Imm6s24)
(dnf f-avc2-c3CRp "register field" (avc2-core-isa) 24 4)
(define-full-operand avc2c3CRp "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRp ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-c3sub4u24 "sub opecode field" (avc2-core-isa) 24 4)
(dnf f-avc2-v3sub4u28 "sub opecode field" (avc2-32-isa) 28 4)
(dnf f-avc2-c3CRo "register field" (avc2-core-isa) 28 4)
(define-full-operand avc2c3CRo "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRo ((parse "avc2_cr") (print "avc2_cr")) () ())
(dnf f-avc2-c3sub4u28 "sub opecode field" (avc2-core-isa) 28 4)
(dnf f-avc2-c3sub3u29 "sub opecode field" (avc2-core-isa) 29 3)
(dnf f-avc2-c3sub2u30 "sub opecode field" (avc2-core-isa) 30 2)
; instruction definitions
(dncpi cnop_avc2_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop"))
"cnop"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(c-call "check_option_cp" pc)
())
(dncpi cmov1_avc2_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1"))
"cmov $avc2c3CRn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3CRn avc2c3Rm (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRn avc2c3Rm)
)
())
(dncpi cmov2_avc2_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2"))
"cmov $avc2c3Rm,$avc2c3CRn"
(+ MAJ_15 (f-sub4 7) avc2c3Rm avc2c3CRn (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3Rm avc2c3CRn)
)
())
(dncpi cmovi_avc2_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi"))
"cmovi $avc2c3CRq,$avc2c3Imm16s4x24e32"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm16s4x24e32 (f-avc2-c3sub4u16 #xe))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (ext SI avc2c3Imm16s4x24e32))
)
())
(dncpi cmovc1_avc2_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1"))
"cmovc $avc2c3CCRn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3CCRn avc2c3Rm (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CCRn avc2c3Rm)
)
())
(dncpi cmovc2_avc2_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2"))
"cmovc $avc2c3Rm,$avc2c3CCRn"
(+ MAJ_15 (f-sub4 7) avc2c3Rm avc2c3CCRn (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3Rm avc2c3CCRn)
)
())
(dncpi cmov_avc2_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov"))
"cmov $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq avc2c3CRp)
)
())
(dncpi cadd3_avc2_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3"))
"cadd3 $avc2c3CRo,$avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRo avc2c3CRq avc2c3CRp (f-avc2-c3sub4u16 #x3) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRo (add avc2c3CRq avc2c3CRp))
)
())
(dncpi caddi_avc2_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi"))
"caddi $avc2c3CRq,$avc2c3Imm6s24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6s24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (add avc2c3CRq (ext SI avc2c3Imm6s24)))
)
())
(dncpi csub_avc2_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub"))
"csub $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (sub avc2c3CRq avc2c3CRp))
)
())
(dncpi cneg_avc2_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg"))
"cneg $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (neg avc2c3CRp))
)
())
(dncpi cextb_avc2_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb"))
"cextb $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (ext SI (and QI (srl avc2c3CRq 0) #xff)))
)
())
(dncpi cexth_avc2_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth"))
"cexth $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x2) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (ext SI (and HI (srl avc2c3CRq 0) #xffff)))
)
())
(dncpi cextub_avc2_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub"))
"cextub $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x8) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (zext SI (and QI (srl avc2c3CRq 0) #xff)))
)
())
(dncpi cextuh_avc2_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh"))
"cextuh $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #xa) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (zext SI (and HI (srl avc2c3CRq 0) #xffff)))
)
())
(dncpi cscltz_avc2_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz"))
"cscltz $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u24 #xa) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 1) 31) 31)))
(set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
)
)
())
(dncpi cldz_avc2_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz"))
"cldz $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (and avc2c3CRp #x80000000) (set avc2c3CRq 0)
(if (and avc2c3CRp #x40000000) (set avc2c3CRq 1)
(if (and avc2c3CRp #x20000000) (set avc2c3CRq 2)
(if (and avc2c3CRp #x10000000) (set avc2c3CRq 3)
(if (and avc2c3CRp #x8000000) (set avc2c3CRq 4)
(if (and avc2c3CRp #x4000000) (set avc2c3CRq 5)
(if (and avc2c3CRp #x2000000) (set avc2c3CRq 6)
(if (and avc2c3CRp #x1000000) (set avc2c3CRq 7)
(if (and avc2c3CRp #x800000) (set avc2c3CRq 8)
(if (and avc2c3CRp #x400000) (set avc2c3CRq 9)
(if (and avc2c3CRp #x200000) (set avc2c3CRq 10)
(if (and avc2c3CRp #x100000) (set avc2c3CRq 11)
(if (and avc2c3CRp #x80000) (set avc2c3CRq 12)
(if (and avc2c3CRp #x40000) (set avc2c3CRq 13)
(if (and avc2c3CRp #x20000) (set avc2c3CRq 14)
(if (and avc2c3CRp #x10000) (set avc2c3CRq 15)
(if (and avc2c3CRp #x8000) (set avc2c3CRq 16)
(if (and avc2c3CRp #x4000) (set avc2c3CRq 17)
(if (and avc2c3CRp #x2000) (set avc2c3CRq 18)
(if (and avc2c3CRp #x1000) (set avc2c3CRq 19)
(if (and avc2c3CRp #x800) (set avc2c3CRq 20)
(if (and avc2c3CRp #x400) (set avc2c3CRq 21)
(if (and avc2c3CRp #x200) (set avc2c3CRq 22)
(if (and avc2c3CRp #x100) (set avc2c3CRq 23)
(if (and avc2c3CRp #x80) (set avc2c3CRq 24)
(if (and avc2c3CRp #x40) (set avc2c3CRq 25)
(if (and avc2c3CRp #x20) (set avc2c3CRq 26)
(if (and avc2c3CRp #x10) (set avc2c3CRq 27)
(if (and avc2c3CRp #x8) (set avc2c3CRq 28)
(if (and avc2c3CRp #x4) (set avc2c3CRq 29)
(if (and avc2c3CRp #x2) (set avc2c3CRq 30)
(if (and avc2c3CRp #x1) (set avc2c3CRq 31)
(set avc2c3CRq 32)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
())
(dncpi cabs_avc2_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs"))
"cabs $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (abs (ext SI (subword SI (sub avc2c3CRq avc2c3CRp) 1))))
)
())
(dncpi cad1s_avc2_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s"))
"cad1s $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((SI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (subword SI (add avc2c3CRq avc2c3CRp) 1))
(set avc2c3CRq (sra tmp0 1))
)
())
(dncpi csb1s_avc2_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s"))
"csb1s $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((SI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (subword SI (sub avc2c3CRq avc2c3CRp) 1))
(set avc2c3CRq (sra tmp0 1))
)
())
(dncpi cmin_avc2_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin"))
"cmin $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avc2c3CRq) (ext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq)
(set avc2c3CRq avc2c3CRp)
)
)
())
(dncpi cmax_avc2_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax"))
"cmax $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (gt (ext SI avc2c3CRq) (ext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq)
(set avc2c3CRq avc2c3CRp)
)
)
())
(dncpi cminu_avc2_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu"))
"cminu $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (ltu (zext SI avc2c3CRq) (zext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq)
(set avc2c3CRq avc2c3CRp)
)
)
())
(dncpi cmaxu_avc2_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu"))
"cmaxu $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xb) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (gtu (zext SI avc2c3CRq) (zext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq)
(set avc2c3CRq avc2c3CRp)
)
)
())
(dncpi cclipi_avc2_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi"))
"cclipi $avc2c3CRq,$avc2c3Imm5u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x4) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avc2c3Imm5u24) (ext SI 0)) (set avc2c3CRq 0)
(sequence() (set tmp0 (sll 1 (sub avc2c3Imm5u24 1)))
(set tmp1 (sub tmp0 1))
(if (gt (ext SI avc2c3CRq) (ext SI tmp1)) (set avc2c3CRq tmp1)
(if (lt (ext SI avc2c3CRq) (ext SI (neg tmp0))) (set avc2c3CRq (neg tmp0))
(set avc2c3CRq avc2c3CRq)
)
)
)
)
)
())
(dncpi cclipiu_avc2_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu"))
"cclipiu $avc2c3CRq,$avc2c3Imm5u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x5) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((SI tmp0)(SI tmp1)) (c-call "check_option_cp" pc)
(if (eq (zext SI avc2c3Imm5u24) (ext SI 0)) (set avc2c3CRq 0)
(sequence() (set tmp0 (sub (sll 1 avc2c3Imm5u24) 1))
(if (gtu (ext SI avc2c3CRq) (zext SI tmp0)) (set avc2c3CRq tmp0)
(if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2c3CRq 0)
(set avc2c3CRq avc2c3CRq)
)
)
)
)
)
())
(dncpi cor_avc2_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor"))
"cor $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (or avc2c3CRq avc2c3CRp))
)
())
(dncpi cand_avc2_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand"))
"cand $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (and avc2c3CRq avc2c3CRp))
)
())
(dncpi cxor_avc2_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor"))
"cxor $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (xor avc2c3CRq avc2c3CRp))
)
())
(dncpi cnor_avc2_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor"))
"cnor $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (inv (or avc2c3CRq avc2c3CRp)))
)
())
(dncpi csra_avc2_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra"))
"csra $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (sra avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f)))
)
())
(dncpi csrl_avc2_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl"))
"csrl $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (srl avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f)))
)
())
(dncpi csll_avc2_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll"))
"csll $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (sll avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f)))
)
())
(dncpi csrai_avc2_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai"))
"csrai $avc2c3CRq,$avc2c3Imm5u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x2) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (sra avc2c3CRq avc2c3Imm5u24))
)
())
(dncpi csrli_avc2_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli"))
"csrli $avc2c3CRq,$avc2c3Imm5u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x3) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (srl avc2c3CRq avc2c3Imm5u24))
)
())
(dncpi cslli_avc2_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli"))
"cslli $avc2c3CRq,$avc2c3Imm5u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x6) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (sll avc2c3CRq avc2c3Imm5u24))
)
())
(dncpi cfsft_avc2_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft"))
"cfsft $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (subword SI (sll (or (sll (zext DI avc2c3CRq) 32) (zext DI avc2c3CRp)) (and QI (srl avc2copCCR0 0) #x3f)) 0))
)
())
(dncpi cfsfta0_avc2_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0"))
"cfsfta0 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)) 0))
)
())
(dncpi cfsfta1_avc2_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1"))
"cfsfta1 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)) 0))
)
())
(dncpi cmula0_avc2_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0"))
"cmula0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat0)) (c-call "check_option_cp" pc)
(set concat0 (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))
(set avc2copCCR2 (subword SI concat0 0))
(set avc2copCCR3 (subword SI concat0 1))
)
())
(dncpi cmulua0_avc2_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0"))
"cmulua0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat1)) (c-call "check_option_cp" pc)
(set concat1 (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))
(set avc2copCCR2 (subword SI concat1 0))
(set avc2copCCR3 (subword SI concat1 1))
)
())
(dncpi cnmula0_avc2_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0"))
"cnmula0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat2)) (c-call "check_option_cp" pc)
(set concat2 (neg (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))))
(set avc2copCCR2 (subword SI concat2 0))
(set avc2copCCR3 (subword SI concat2 1))
)
())
(dncpi cmada0_avc2_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0"))
"cmada0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat3)) (c-call "check_option_cp" pc)
(set concat3 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))))
(set avc2copCCR2 (subword SI concat3 0))
(set avc2copCCR3 (subword SI concat3 1))
)
())
(dncpi cmadua0_avc2_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0"))
"cmadua0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat4)) (c-call "check_option_cp" pc)
(set concat4 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))))
(set avc2copCCR2 (subword SI concat4 0))
(set avc2copCCR3 (subword SI concat4 1))
)
())
(dncpi cmsba0_avc2_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0"))
"cmsba0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat5)) (c-call "check_option_cp" pc)
(set concat5 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))))
(set avc2copCCR2 (subword SI concat5 0))
(set avc2copCCR3 (subword SI concat5 1))
)
())
(dncpi cmsbua0_avc2_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0"))
"cmsbua0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat6)) (c-call "check_option_cp" pc)
(set concat6 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))))
(set avc2copCCR2 (subword SI concat6 0))
(set avc2copCCR3 (subword SI concat6 1))
)
())
(dncpi cmula1_avc2_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1"))
"cmula1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat7)) (c-call "check_option_cp" pc)
(set concat7 (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))
(set avc2copCCR4 (subword SI concat7 0))
(set avc2copCCR5 (subword SI concat7 1))
)
())
(dncpi cmulua1_avc2_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1"))
"cmulua1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat8)) (c-call "check_option_cp" pc)
(set concat8 (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))
(set avc2copCCR4 (subword SI concat8 0))
(set avc2copCCR5 (subword SI concat8 1))
)
())
(dncpi cnmula1_avc2_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1"))
"cnmula1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat9)) (c-call "check_option_cp" pc)
(set concat9 (neg (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))))
(set avc2copCCR4 (subword SI concat9 0))
(set avc2copCCR5 (subword SI concat9 1))
)
())
(dncpi cmada1_avc2_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1"))
"cmada1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat10)) (c-call "check_option_cp" pc)
(set concat10 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))))
(set avc2copCCR4 (subword SI concat10 0))
(set avc2copCCR5 (subword SI concat10 1))
)
())
(dncpi cmadua1_avc2_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1"))
"cmadua1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat11)) (c-call "check_option_cp" pc)
(set concat11 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))))
(set avc2copCCR4 (subword SI concat11 0))
(set avc2copCCR5 (subword SI concat11 1))
)
())
(dncpi cmsba1_avc2_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1"))
"cmsba1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat12)) (c-call "check_option_cp" pc)
(set concat12 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))))
(set avc2copCCR4 (subword SI concat12 0))
(set avc2copCCR5 (subword SI concat12 1))
)
())
(dncpi cmsbua1_avc2_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1"))
"cmsbua1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat13)) (c-call "check_option_cp" pc)
(set concat13 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))))
(set avc2copCCR4 (subword SI concat13 0))
(set avc2copCCR5 (subword SI concat13 1))
)
())
(dncpi xmula0_avc2_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0"))
"xmula0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat14)) (c-call "check_option_cp" pc)
(set concat14 (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))
(set avc2copCCR2 (subword SI concat14 0))
(set avc2copCCR3 (subword SI concat14 1))
)
())
(dncpi xmulua0_avc2_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0"))
"xmulua0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat15)) (c-call "check_option_cp" pc)
(set concat15 (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))
(set avc2copCCR2 (subword SI concat15 0))
(set avc2copCCR3 (subword SI concat15 1))
)
())
(dncpi xnmula0_avc2_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0"))
"xnmula0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat16)) (c-call "check_option_cp" pc)
(set concat16 (neg (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))))
(set avc2copCCR2 (subword SI concat16 0))
(set avc2copCCR3 (subword SI concat16 1))
)
())
(dncpi xmada0_avc2_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0"))
"xmada0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat17)) (c-call "check_option_cp" pc)
(set concat17 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))))
(set avc2copCCR2 (subword SI concat17 0))
(set avc2copCCR3 (subword SI concat17 1))
)
())
(dncpi xmadua0_avc2_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0"))
"xmadua0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat18)) (c-call "check_option_cp" pc)
(set concat18 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))))
(set avc2copCCR2 (subword SI concat18 0))
(set avc2copCCR3 (subword SI concat18 1))
)
())
(dncpi xmsba0_avc2_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0"))
"xmsba0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat19)) (c-call "check_option_cp" pc)
(set concat19 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))))
(set avc2copCCR2 (subword SI concat19 0))
(set avc2copCCR3 (subword SI concat19 1))
)
())
(dncpi xmsbua0_avc2_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0"))
"xmsbua0 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat20)) (c-call "check_option_cp" pc)
(set concat20 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))))
(set avc2copCCR2 (subword SI concat20 0))
(set avc2copCCR3 (subword SI concat20 1))
)
())
(dncpi xmula1_avc2_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1"))
"xmula1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat21)) (c-call "check_option_cp" pc)
(set concat21 (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))
(set avc2copCCR4 (subword SI concat21 0))
(set avc2copCCR5 (subword SI concat21 1))
)
())
(dncpi xmulua1_avc2_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1"))
"xmulua1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat22)) (c-call "check_option_cp" pc)
(set concat22 (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))
(set avc2copCCR4 (subword SI concat22 0))
(set avc2copCCR5 (subword SI concat22 1))
)
())
(dncpi xnmula1_avc2_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1"))
"xnmula1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat23)) (c-call "check_option_cp" pc)
(set concat23 (neg (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))))
(set avc2copCCR4 (subword SI concat23 0))
(set avc2copCCR5 (subword SI concat23 1))
)
())
(dncpi xmada1_avc2_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1"))
"xmada1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat24)) (c-call "check_option_cp" pc)
(set concat24 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))))
(set avc2copCCR4 (subword SI concat24 0))
(set avc2copCCR5 (subword SI concat24 1))
)
())
(dncpi xmadua1_avc2_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1"))
"xmadua1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat25)) (c-call "check_option_cp" pc)
(set concat25 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))))
(set avc2copCCR4 (subword SI concat25 0))
(set avc2copCCR5 (subword SI concat25 1))
)
())
(dncpi xmsba1_avc2_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1"))
"xmsba1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat26)) (c-call "check_option_cp" pc)
(set concat26 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))))
(set avc2copCCR4 (subword SI concat26 0))
(set avc2copCCR5 (subword SI concat26 1))
)
())
(dncpi xmsbua1_avc2_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1"))
"xmsbua1 $avc2c3Rn,$avc2c3Rm"
(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc))
(sequence((DI concat27)) (c-call "check_option_cp" pc)
(set concat27 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))))
(set avc2copCCR4 (subword SI concat27 0))
(set avc2copCCR5 (subword SI concat27 1))
)
())
(dncpi cclipa0_avc2_c3 "cclipa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipa0"))
"cclipa0 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x6) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc)
(set max #x000000007FFFFFFF)
(set min #xFFFFFFFF80000000)
(if (gt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI max)) (set tmp_rslt max)
(if (lt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI min)) (set tmp_rslt min)
(set tmp_rslt (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))
)
)
(set avc2c3CRq (subword SI tmp_rslt 1))
)
())
(dncpi cclipa1_avc2_c3 "cclipa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipa1"))
"cclipa1 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x6) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc)
(set max #x000000007FFFFFFF)
(set min #xFFFFFFFF80000000)
(if (gt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI max)) (set tmp_rslt max)
(if (lt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI min)) (set tmp_rslt min)
(set tmp_rslt (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)))
)
)
(set avc2c3CRq (subword SI tmp_rslt 1))
)
())
(dncpi cmvsla0i_avc2_c3 "cmvsla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsla0i"))
"cmvsla0i $avc2c3CRq,$avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x2) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat28)) (c-call "check_option_cp" pc)
(set concat28 (sll (ext DI avc2c3CRq) avc2c3Imm6u24))
(set avc2copCCR2 (subword SI concat28 0))
(set avc2copCCR3 (subword SI concat28 1))
)
())
(dncpi cmvsra0i_avc2_c3 "cmvsra0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsra0i"))
"cmvsra0i $avc2c3CRq,$avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat29)) (c-call "check_option_cp" pc)
(set concat29 (sra (ext DI avc2c3CRq) avc2c3Imm6u24))
(set avc2copCCR2 (subword SI concat29 0))
(set avc2copCCR3 (subword SI concat29 1))
)
())
(dncpi cmvsla1i_avc2_c3 "cmvsla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsla1i"))
"cmvsla1i $avc2c3CRq,$avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x3) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat30)) (c-call "check_option_cp" pc)
(set concat30 (sll (ext DI avc2c3CRq) avc2c3Imm6u24))
(set avc2copCCR4 (subword SI concat30 0))
(set avc2copCCR5 (subword SI concat30 1))
)
())
(dncpi cmvsra1i_avc2_c3 "cmvsra1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsra1i"))
"cmvsra1i $avc2c3CRq,$avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat31)) (c-call "check_option_cp" pc)
(set concat31 (sra (ext DI avc2c3CRq) avc2c3Imm6u24))
(set avc2copCCR4 (subword SI concat31 0))
(set avc2copCCR5 (subword SI concat31 1))
)
())
(dncpi csraa0i_avc2_c3 "csraa0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa0i"))
"csraa0i $avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat32)) (c-call "check_option_cp" pc)
(set concat32 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24))
(set avc2copCCR2 (subword SI concat32 0))
(set avc2copCCR3 (subword SI concat32 1))
)
())
(dncpi csraa1i_avc2_c3 "csraa1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa1i"))
"csraa1i $avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat33)) (c-call "check_option_cp" pc)
(set concat33 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24))
(set avc2copCCR4 (subword SI concat33 0))
(set avc2copCCR5 (subword SI concat33 1))
)
())
(dncpi csrla0i_avc2_c3 "csrla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla0i"))
"csrla0i $avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x1) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat34)) (c-call "check_option_cp" pc)
(set concat34 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24))
(set avc2copCCR2 (subword SI concat34 0))
(set avc2copCCR3 (subword SI concat34 1))
)
())
(dncpi csrla1i_avc2_c3 "csrla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla1i"))
"csrla1i $avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x1) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat35)) (c-call "check_option_cp" pc)
(set concat35 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24))
(set avc2copCCR4 (subword SI concat35 0))
(set avc2copCCR5 (subword SI concat35 1))
)
())
(dncpi cslla0i_avc2_c3 "cslla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla0i"))
"cslla0i $avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x3) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat36)) (c-call "check_option_cp" pc)
(set concat36 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24))
(set avc2copCCR2 (subword SI concat36 0))
(set avc2copCCR3 (subword SI concat36 1))
)
())
(dncpi cslla1i_avc2_c3 "cslla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla1i"))
"cslla1i $avc2c3Imm6u24"
(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x3) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat37)) (c-call "check_option_cp" pc)
(set concat37 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24))
(set avc2copCCR4 (subword SI concat37 0))
(set avc2copCCR5 (subword SI concat37 1))
)
())
(dncpi csraa0_avc2_c3 "csraa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa0"))
"csraa0"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xc) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat38)) (c-call "check_option_cp" pc)
(set concat38 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR2 (subword SI concat38 0))
(set avc2copCCR3 (subword SI concat38 1))
)
())
(dncpi csraa1_avc2_c3 "csraa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa1"))
"csraa1"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xc) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat39)) (c-call "check_option_cp" pc)
(set concat39 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR4 (subword SI concat39 0))
(set avc2copCCR5 (subword SI concat39 1))
)
())
(dncpi csrla0_avc2_c3 "csrla0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla0"))
"csrla0"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xd) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat40)) (c-call "check_option_cp" pc)
(set concat40 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR2 (subword SI concat40 0))
(set avc2copCCR3 (subword SI concat40 1))
)
())
(dncpi csrla1_avc2_c3 "csrla1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla1"))
"csrla1"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xd) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat41)) (c-call "check_option_cp" pc)
(set concat41 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR4 (subword SI concat41 0))
(set avc2copCCR5 (subword SI concat41 1))
)
())
(dncpi cslla0_avc2_c3 "cslla0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla0"))
"cslla0"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xf) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat42)) (c-call "check_option_cp" pc)
(set concat42 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR2 (subword SI concat42 0))
(set avc2copCCR3 (subword SI concat42 1))
)
())
(dncpi cslla1_avc2_c3 "cslla1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla1"))
"cslla1"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xf) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat43)) (c-call "check_option_cp" pc)
(set concat43 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR4 (subword SI concat43 0))
(set avc2copCCR5 (subword SI concat43 1))
)
())
(dncpi cadda0_avc2_c3 "cadda0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadda0"))
"cadda0 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat44)) (c-call "check_option_cp" pc)
(set concat44 (add (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2c3CRq)))
(set avc2copCCR2 (subword SI concat44 0))
(set avc2copCCR3 (subword SI concat44 1))
)
())
(dncpi cadda1_avc2_c3 "cadda1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadda1"))
"cadda1 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat45)) (c-call "check_option_cp" pc)
(set concat45 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2c3CRq)))
(set avc2copCCR4 (subword SI concat45 0))
(set avc2copCCR5 (subword SI concat45 1))
)
())
(dncpi csuba0_avc2_c3 "csuba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csuba0"))
"csuba0 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat46)) (c-call "check_option_cp" pc)
(set concat46 (sub (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2c3CRq)))
(set avc2copCCR2 (subword SI concat46 0))
(set avc2copCCR3 (subword SI concat46 1))
)
())
(dncpi csuba1_avc2_c3 "csuba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csuba1"))
"csuba1 $avc2c3CRq"
(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat47)) (c-call "check_option_cp" pc)
(set concat47 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2c3CRq)))
(set avc2copCCR4 (subword SI concat47 0))
(set avc2copCCR5 (subword SI concat47 1))
)
())
(dncpi cadd2a0_avc2_c3 "cadd2a0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd2a0"))
"cadd2a0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat48)) (c-call "check_option_cp" pc)
(set concat48 (add (ext DI avc2c3CRq) (ext DI avc2c3CRp)))
(set avc2copCCR2 (subword SI concat48 0))
(set avc2copCCR3 (subword SI concat48 1))
)
())
(dncpi cadd2a1_avc2_c3 "cadd2a1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd2a1"))
"cadd2a1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat49)) (c-call "check_option_cp" pc)
(set concat49 (add (ext DI avc2c3CRq) (ext DI avc2c3CRp)))
(set avc2copCCR4 (subword SI concat49 0))
(set avc2copCCR5 (subword SI concat49 1))
)
())
(dncpi csub2a0_avc2_c3 "csub2a0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub2a0"))
"csub2a0 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat50)) (c-call "check_option_cp" pc)
(set concat50 (sub (ext DI avc2c3CRq) (ext DI avc2c3CRp)))
(set avc2copCCR2 (subword SI concat50 0))
(set avc2copCCR3 (subword SI concat50 1))
)
())
(dncpi csub2a1_avc2_c3 "csub2a1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub2a1"))
"csub2a1 $avc2c3CRq,$avc2c3CRp"
(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xb) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat51)) (c-call "check_option_cp" pc)
(set concat51 (sub (ext DI avc2c3CRq) (ext DI avc2c3CRp)))
(set avc2copCCR4 (subword SI concat51 0))
(set avc2copCCR5 (subword SI concat51 1))
)
())
(dncpi caddaa0_avc2_c3 "caddaa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddaa0"))
"caddaa0"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat52)) (c-call "check_option_cp" pc)
(set concat52 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR2 (subword SI concat52 0))
(set avc2copCCR3 (subword SI concat52 1))
)
())
(dncpi caddaa1_avc2_c3 "caddaa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddaa1"))
"caddaa1"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat53)) (c-call "check_option_cp" pc)
(set concat53 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR4 (subword SI concat53 0))
(set avc2copCCR5 (subword SI concat53 1))
)
())
(dncpi csubaa0_avc2_c3 "csubaa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csubaa0"))
"csubaa0"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat54)) (c-call "check_option_cp" pc)
(set concat54 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR2 (subword SI concat54 0))
(set avc2copCCR3 (subword SI concat54 1))
)
())
(dncpi csubaa1_avc2_c3 "csubaa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csubaa1"))
"csubaa1"
(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0))
(sequence((DI concat55)) (c-call "check_option_cp" pc)
(set concat55 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR4 (subword SI concat55 0))
(set avc2copCCR5 (subword SI concat55 1))
)
())
(dn16i cnop_avc2_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop"))
"cnop"
(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x0))
(c-call "check_option_cp" pc)
())
(dnmi cpnop16_avc2_v1 "cpnop16"
(avc2-16-isa NO-DIS)
"cpnop16"
(emit cnop_avc2_v1)
)
(dn16i cmov_avc2_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov"))
"cmov $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq avc2v1CRp)
)
())
(dn16i cmovi_avc2_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi"))
"cmovi $avc2v1CRq,$avc2v1Imm8s8"
(+ avc2v1CRq avc2v1Imm8s8 (f-avc2-v1sub4u0 #x2))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (ext SI avc2v1Imm8s8))
)
())
(dn16i cadd3_avc2_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3"))
"cadd3 $avc2v1CRo,$avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRo avc2v1CRq avc2v1CRp (f-avc2-v1sub4u0 #x3))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRo (add avc2v1CRq avc2v1CRp))
)
())
(dn16i caddi_avc2_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi"))
"caddi $avc2v1CRq,$avc2v1Imm6s8"
(+ avc2v1CRq avc2v1Imm6s8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (add avc2v1CRq (ext SI avc2v1Imm6s8)))
)
())
(dn16i csub_avc2_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub"))
"csub $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (sub avc2v1CRq avc2v1CRp))
)
())
(dn16i cneg_avc2_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg"))
"cneg $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (neg avc2v1CRp))
)
())
(dn16i cextb_avc2_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb"))
"cextb $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (ext SI (and QI (srl avc2v1CRq 0) #xff)))
)
())
(dn16i cexth_avc2_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth"))
"cexth $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x2) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (ext SI (and HI (srl avc2v1CRq 0) #xffff)))
)
())
(dn16i cextub_avc2_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub"))
"cextub $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x8) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (zext SI (and QI (srl avc2v1CRq 0) #xff)))
)
())
(dn16i cextuh_avc2_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh"))
"cextuh $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #xa) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (zext SI (and HI (srl avc2v1CRq 0) #xffff)))
)
())
(dn16i cscltz_avc2_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz"))
"cscltz $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u8 #xa) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avc2v1CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 1) 31) 31)))
(set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31)))
)
)
())
(dn16i cldz_avc2_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz"))
"cldz $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (and avc2v1CRp #x80000000) (set avc2v1CRq 0)
(if (and avc2v1CRp #x40000000) (set avc2v1CRq 1)
(if (and avc2v1CRp #x20000000) (set avc2v1CRq 2)
(if (and avc2v1CRp #x10000000) (set avc2v1CRq 3)
(if (and avc2v1CRp #x8000000) (set avc2v1CRq 4)
(if (and avc2v1CRp #x4000000) (set avc2v1CRq 5)
(if (and avc2v1CRp #x2000000) (set avc2v1CRq 6)
(if (and avc2v1CRp #x1000000) (set avc2v1CRq 7)
(if (and avc2v1CRp #x800000) (set avc2v1CRq 8)
(if (and avc2v1CRp #x400000) (set avc2v1CRq 9)
(if (and avc2v1CRp #x200000) (set avc2v1CRq 10)
(if (and avc2v1CRp #x100000) (set avc2v1CRq 11)
(if (and avc2v1CRp #x80000) (set avc2v1CRq 12)
(if (and avc2v1CRp #x40000) (set avc2v1CRq 13)
(if (and avc2v1CRp #x20000) (set avc2v1CRq 14)
(if (and avc2v1CRp #x10000) (set avc2v1CRq 15)
(if (and avc2v1CRp #x8000) (set avc2v1CRq 16)
(if (and avc2v1CRp #x4000) (set avc2v1CRq 17)
(if (and avc2v1CRp #x2000) (set avc2v1CRq 18)
(if (and avc2v1CRp #x1000) (set avc2v1CRq 19)
(if (and avc2v1CRp #x800) (set avc2v1CRq 20)
(if (and avc2v1CRp #x400) (set avc2v1CRq 21)
(if (and avc2v1CRp #x200) (set avc2v1CRq 22)
(if (and avc2v1CRp #x100) (set avc2v1CRq 23)
(if (and avc2v1CRp #x80) (set avc2v1CRq 24)
(if (and avc2v1CRp #x40) (set avc2v1CRq 25)
(if (and avc2v1CRp #x20) (set avc2v1CRq 26)
(if (and avc2v1CRp #x10) (set avc2v1CRq 27)
(if (and avc2v1CRp #x8) (set avc2v1CRq 28)
(if (and avc2v1CRp #x4) (set avc2v1CRq 29)
(if (and avc2v1CRp #x2) (set avc2v1CRq 30)
(if (and avc2v1CRp #x1) (set avc2v1CRq 31)
(set avc2v1CRq 32)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
())
(dn16i cabs_avc2_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs"))
"cabs $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (abs (ext SI (subword SI (sub avc2v1CRq avc2v1CRp) 1))))
)
())
(dn16i cad1s_avc2_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s"))
"cad1s $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x5))
(sequence((SI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (subword SI (add avc2v1CRq avc2v1CRp) 1))
(set avc2v1CRq (sra tmp0 1))
)
())
(dn16i csb1s_avc2_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s"))
"csb1s $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x5))
(sequence((SI tmp0)) (c-call "check_option_cp" pc)
(set tmp0 (subword SI (sub avc2v1CRq avc2v1CRp) 1))
(set avc2v1CRq (sra tmp0 1))
)
())
(dn16i cmin_avc2_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin"))
"cmin $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (lt (ext SI avc2v1CRq) (ext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq)
(set avc2v1CRq avc2v1CRp)
)
)
())
(dn16i cmax_avc2_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax"))
"cmax $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (gt (ext SI avc2v1CRq) (ext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq)
(set avc2v1CRq avc2v1CRp)
)
)
())
(dn16i cminu_avc2_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu"))
"cminu $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (ltu (zext SI avc2v1CRq) (zext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq)
(set avc2v1CRq avc2v1CRp)
)
)
())
(dn16i cmaxu_avc2_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu"))
"cmaxu $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xb) (f-avc2-v1sub4u0 #x5))
(sequence() (c-call "check_option_cp" pc)
(if (gtu (zext SI avc2v1CRq) (zext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq)
(set avc2v1CRq avc2v1CRp)
)
)
())
(dn16i cclipi_avc2_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi"))
"cclipi $avc2v1CRq,$avc2v1Imm5u8"
(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x4) (f-avc2-v1sub4u0 #x5))
(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avc2v1Imm5u8) (ext SI 0)) (set avc2v1CRq 0)
(sequence() (set tmp0 (sll 1 (sub avc2v1Imm5u8 1)))
(set tmp1 (sub tmp0 1))
(if (gt (ext SI avc2v1CRq) (ext SI tmp1)) (set avc2v1CRq tmp1)
(if (lt (ext SI avc2v1CRq) (ext SI (neg tmp0))) (set avc2v1CRq (neg tmp0))
(set avc2v1CRq avc2v1CRq)
)
)
)
)
)
())
(dn16i cclipiu_avc2_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu"))
"cclipiu $avc2v1CRq,$avc2v1Imm5u8"
(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x5) (f-avc2-v1sub4u0 #x5))
(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc)
(if (eq (zext SI avc2v1Imm5u8) (ext SI 0)) (set avc2v1CRq 0)
(sequence() (set tmp0 (sub (sll 1 avc2v1Imm5u8) 1))
(if (gtu (ext SI avc2v1CRq) (zext SI tmp0)) (set avc2v1CRq tmp0)
(if (lt (ext SI avc2v1CRq) (ext SI 0)) (set avc2v1CRq 0)
(set avc2v1CRq avc2v1CRq)
)
)
)
)
)
())
(dn16i cor_avc2_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor"))
"cor $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x4) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (or avc2v1CRq avc2v1CRp))
)
())
(dn16i cand_avc2_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand"))
"cand $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x5) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (and avc2v1CRq avc2v1CRp))
)
())
(dn16i cxor_avc2_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor"))
"cxor $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x6) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (xor avc2v1CRq avc2v1CRp))
)
())
(dn16i cnor_avc2_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor"))
"cnor $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (inv (or avc2v1CRq avc2v1CRp)))
)
())
(dn16i csra_avc2_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra"))
"csra $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xc) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (sra avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f)))
)
())
(dn16i csrl_avc2_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl"))
"csrl $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xd) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (srl avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f)))
)
())
(dn16i csll_avc2_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll"))
"csll $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xe) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (sll avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f)))
)
())
(dn16i csrai_avc2_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai"))
"csrai $avc2v1CRq,$avc2v1Imm5u8"
(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x2) (f-avc2-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (sra avc2v1CRq avc2v1Imm5u8))
)
())
(dn16i csrli_avc2_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli"))
"csrli $avc2v1CRq,$avc2v1Imm5u8"
(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x3) (f-avc2-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (srl avc2v1CRq avc2v1Imm5u8))
)
())
(dn16i cslli_avc2_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli"))
"cslli $avc2v1CRq,$avc2v1Imm5u8"
(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x6) (f-avc2-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (sll avc2v1CRq avc2v1Imm5u8))
)
())
(dn16i cfsft_avc2_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft"))
"cfsft $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u0 #x0))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2v1CRq)) 32) (zext DI avc2v1CRp)) (and QI (srl avc2copCCR0 0) #x3f)) 0))
)
())
(dn16i cfsfta0_avc2_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0"))
"cfsfta0 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)) 0))
)
())
(dn16i cfsfta1_avc2_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1"))
"cfsfta1 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x1))
(sequence() (c-call "check_option_cp" pc)
(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)) 0))
)
())
(dn16i cmula0_avc2_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0"))
"cmula0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat56)) (c-call "check_option_cp" pc)
(set concat56 (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))
(set avc2copCCR2 (subword SI concat56 0))
(set avc2copCCR3 (subword SI concat56 1))
)
())
(dn16i cmulua0_avc2_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0"))
"cmulua0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat57)) (c-call "check_option_cp" pc)
(set concat57 (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))
(set avc2copCCR2 (subword SI concat57 0))
(set avc2copCCR3 (subword SI concat57 1))
)
())
(dn16i cnmula0_avc2_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0"))
"cnmula0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat58)) (c-call "check_option_cp" pc)
(set concat58 (neg (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))))
(set avc2copCCR2 (subword SI concat58 0))
(set avc2copCCR3 (subword SI concat58 1))
)
())
(dn16i cmada0_avc2_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0"))
"cmada0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x4) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat59)) (c-call "check_option_cp" pc)
(set concat59 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))))
(set avc2copCCR2 (subword SI concat59 0))
(set avc2copCCR3 (subword SI concat59 1))
)
())
(dn16i cmadua0_avc2_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0"))
"cmadua0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x5) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat60)) (c-call "check_option_cp" pc)
(set concat60 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))))
(set avc2copCCR2 (subword SI concat60 0))
(set avc2copCCR3 (subword SI concat60 1))
)
())
(dn16i cmsba0_avc2_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0"))
"cmsba0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x6) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat61)) (c-call "check_option_cp" pc)
(set concat61 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))))
(set avc2copCCR2 (subword SI concat61 0))
(set avc2copCCR3 (subword SI concat61 1))
)
())
(dn16i cmsbua0_avc2_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0"))
"cmsbua0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat62)) (c-call "check_option_cp" pc)
(set concat62 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))))
(set avc2copCCR2 (subword SI concat62 0))
(set avc2copCCR3 (subword SI concat62 1))
)
())
(dn16i cmula1_avc2_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1"))
"cmula1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat63)) (c-call "check_option_cp" pc)
(set concat63 (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))
(set avc2copCCR4 (subword SI concat63 0))
(set avc2copCCR5 (subword SI concat63 1))
)
())
(dn16i cmulua1_avc2_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1"))
"cmulua1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat64)) (c-call "check_option_cp" pc)
(set concat64 (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))
(set avc2copCCR4 (subword SI concat64 0))
(set avc2copCCR5 (subword SI concat64 1))
)
())
(dn16i cnmula1_avc2_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1"))
"cnmula1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat65)) (c-call "check_option_cp" pc)
(set concat65 (neg (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))))
(set avc2copCCR4 (subword SI concat65 0))
(set avc2copCCR5 (subword SI concat65 1))
)
())
(dn16i cmada1_avc2_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1"))
"cmada1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xc) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat66)) (c-call "check_option_cp" pc)
(set concat66 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))))
(set avc2copCCR4 (subword SI concat66 0))
(set avc2copCCR5 (subword SI concat66 1))
)
())
(dn16i cmadua1_avc2_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1"))
"cmadua1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xd) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat67)) (c-call "check_option_cp" pc)
(set concat67 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))))
(set avc2copCCR4 (subword SI concat67 0))
(set avc2copCCR5 (subword SI concat67 1))
)
())
(dn16i cmsba1_avc2_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1"))
"cmsba1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xe) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat68)) (c-call "check_option_cp" pc)
(set concat68 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))))
(set avc2copCCR4 (subword SI concat68 0))
(set avc2copCCR5 (subword SI concat68 1))
)
())
(dn16i cmsbua1_avc2_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1"))
"cmsbua1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u0 #x4))
(sequence((DI concat69)) (c-call "check_option_cp" pc)
(set concat69 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))))
(set avc2copCCR4 (subword SI concat69 0))
(set avc2copCCR5 (subword SI concat69 1))
)
())
(dn16i cclipa0_avc2_v1 "cclipa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipa0"))
"cclipa0 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x6))
(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc)
(set max #x000000007FFFFFFF)
(set min #xFFFFFFFF80000000)
(if (gt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI max)) (set tmp_rslt max)
(if (lt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI min)) (set tmp_rslt min)
(set tmp_rslt (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))
)
)
(set avc2v1CRq (subword SI tmp_rslt 1))
)
())
(dn16i cclipa1_avc2_v1 "cclipa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipa1"))
"cclipa1 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x6))
(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc)
(set max #x000000007FFFFFFF)
(set min #xFFFFFFFF80000000)
(if (gt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI max)) (set tmp_rslt max)
(if (lt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI min)) (set tmp_rslt min)
(set tmp_rslt (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)))
)
)
(set avc2v1CRq (subword SI tmp_rslt 1))
)
())
(dn16i cmvsla0i_avc2_v1 "cmvsla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsla0i"))
"cmvsla0i $avc2v1CRq,$avc2v1Imm6u8"
(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x2) (f-avc2-v1sub4u0 #xb))
(sequence((DI concat70)) (c-call "check_option_cp" pc)
(set concat70 (sll (ext DI avc2v1CRq) avc2v1Imm6u8))
(set avc2copCCR2 (subword SI concat70 0))
(set avc2copCCR3 (subword SI concat70 1))
)
())
(dn16i cmvsra0i_avc2_v1 "cmvsra0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsra0i"))
"cmvsra0i $avc2v1CRq,$avc2v1Imm6u8"
(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u0 #xb))
(sequence((DI concat71)) (c-call "check_option_cp" pc)
(set concat71 (sra (ext DI avc2v1CRq) avc2v1Imm6u8))
(set avc2copCCR2 (subword SI concat71 0))
(set avc2copCCR3 (subword SI concat71 1))
)
())
(dn16i cmvsla1i_avc2_v1 "cmvsla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsla1i"))
"cmvsla1i $avc2v1CRq,$avc2v1Imm6u8"
(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x3) (f-avc2-v1sub4u0 #xb))
(sequence((DI concat72)) (c-call "check_option_cp" pc)
(set concat72 (sll (ext DI avc2v1CRq) avc2v1Imm6u8))
(set avc2copCCR4 (subword SI concat72 0))
(set avc2copCCR5 (subword SI concat72 1))
)
())
(dn16i cmvsra1i_avc2_v1 "cmvsra1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsra1i"))
"cmvsra1i $avc2v1CRq,$avc2v1Imm6u8"
(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u0 #xb))
(sequence((DI concat73)) (c-call "check_option_cp" pc)
(set concat73 (sra (ext DI avc2v1CRq) avc2v1Imm6u8))
(set avc2copCCR4 (subword SI concat73 0))
(set avc2copCCR5 (subword SI concat73 1))
)
())
(dn16i csraa0i_avc2_v1 "csraa0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa0i"))
"csraa0i $avc2v1Imm6u8"
(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat74)) (c-call "check_option_cp" pc)
(set concat74 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8))
(set avc2copCCR2 (subword SI concat74 0))
(set avc2copCCR3 (subword SI concat74 1))
)
())
(dn16i csraa1i_avc2_v1 "csraa1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa1i"))
"csraa1i $avc2v1Imm6u8"
(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat75)) (c-call "check_option_cp" pc)
(set concat75 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8))
(set avc2copCCR4 (subword SI concat75 0))
(set avc2copCCR5 (subword SI concat75 1))
)
())
(dn16i csrla0i_avc2_v1 "csrla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla0i"))
"csrla0i $avc2v1Imm6u8"
(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x1) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat76)) (c-call "check_option_cp" pc)
(set concat76 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8))
(set avc2copCCR2 (subword SI concat76 0))
(set avc2copCCR3 (subword SI concat76 1))
)
())
(dn16i csrla1i_avc2_v1 "csrla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla1i"))
"csrla1i $avc2v1Imm6u8"
(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x1) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat77)) (c-call "check_option_cp" pc)
(set concat77 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8))
(set avc2copCCR4 (subword SI concat77 0))
(set avc2copCCR5 (subword SI concat77 1))
)
())
(dn16i cslla0i_avc2_v1 "cslla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla0i"))
"cslla0i $avc2v1Imm6u8"
(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x3) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat78)) (c-call "check_option_cp" pc)
(set concat78 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8))
(set avc2copCCR2 (subword SI concat78 0))
(set avc2copCCR3 (subword SI concat78 1))
)
())
(dn16i cslla1i_avc2_v1 "cslla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla1i"))
"cslla1i $avc2v1Imm6u8"
(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x3) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat79)) (c-call "check_option_cp" pc)
(set concat79 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8))
(set avc2copCCR4 (subword SI concat79 0))
(set avc2copCCR5 (subword SI concat79 1))
)
())
(dn16i csraa0_avc2_v1 "csraa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa0"))
"csraa0"
(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xc) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat80)) (c-call "check_option_cp" pc)
(set concat80 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR2 (subword SI concat80 0))
(set avc2copCCR3 (subword SI concat80 1))
)
())
(dn16i csraa1_avc2_v1 "csraa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa1"))
"csraa1"
(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xc) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat81)) (c-call "check_option_cp" pc)
(set concat81 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR4 (subword SI concat81 0))
(set avc2copCCR5 (subword SI concat81 1))
)
())
(dn16i csrla0_avc2_v1 "csrla0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla0"))
"csrla0"
(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xd) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat82)) (c-call "check_option_cp" pc)
(set concat82 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR2 (subword SI concat82 0))
(set avc2copCCR3 (subword SI concat82 1))
)
())
(dn16i csrla1_avc2_v1 "csrla1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla1"))
"csrla1"
(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xd) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat83)) (c-call "check_option_cp" pc)
(set concat83 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR4 (subword SI concat83 0))
(set avc2copCCR5 (subword SI concat83 1))
)
())
(dn16i cslla0_avc2_v1 "cslla0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla0"))
"cslla0"
(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xf) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat84)) (c-call "check_option_cp" pc)
(set concat84 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR2 (subword SI concat84 0))
(set avc2copCCR3 (subword SI concat84 1))
)
())
(dn16i cslla1_avc2_v1 "cslla1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla1"))
"cslla1"
(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xf) (f-avc2-v1sub4u0 #x9))
(sequence((DI concat85)) (c-call "check_option_cp" pc)
(set concat85 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)))
(set avc2copCCR4 (subword SI concat85 0))
(set avc2copCCR5 (subword SI concat85 1))
)
())
(dn16i cadda0_avc2_v1 "cadda0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadda0"))
"cadda0 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat86)) (c-call "check_option_cp" pc)
(set concat86 (add (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2v1CRq)))
(set avc2copCCR2 (subword SI concat86 0))
(set avc2copCCR3 (subword SI concat86 1))
)
())
(dn16i cadda1_avc2_v1 "cadda1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadda1"))
"cadda1 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat87)) (c-call "check_option_cp" pc)
(set concat87 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2v1CRq)))
(set avc2copCCR4 (subword SI concat87 0))
(set avc2copCCR5 (subword SI concat87 1))
)
())
(dn16i csuba0_avc2_v1 "csuba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csuba0"))
"csuba0 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat88)) (c-call "check_option_cp" pc)
(set concat88 (sub (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2v1CRq)))
(set avc2copCCR2 (subword SI concat88 0))
(set avc2copCCR3 (subword SI concat88 1))
)
())
(dn16i csuba1_avc2_v1 "csuba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csuba1"))
"csuba1 $avc2v1CRq"
(+ avc2v1CRq (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat89)) (c-call "check_option_cp" pc)
(set concat89 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2v1CRq)))
(set avc2copCCR4 (subword SI concat89 0))
(set avc2copCCR5 (subword SI concat89 1))
)
())
(dn16i cadd2a0_avc2_v1 "cadd2a0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd2a0"))
"cadd2a0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat90)) (c-call "check_option_cp" pc)
(set concat90 (add (ext DI avc2v1CRq) (ext DI avc2v1CRp)))
(set avc2copCCR2 (subword SI concat90 0))
(set avc2copCCR3 (subword SI concat90 1))
)
())
(dn16i cadd2a1_avc2_v1 "cadd2a1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd2a1"))
"cadd2a1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat91)) (c-call "check_option_cp" pc)
(set concat91 (add (ext DI avc2v1CRq) (ext DI avc2v1CRp)))
(set avc2copCCR4 (subword SI concat91 0))
(set avc2copCCR5 (subword SI concat91 1))
)
())
(dn16i csub2a0_avc2_v1 "csub2a0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub2a0"))
"csub2a0 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat92)) (c-call "check_option_cp" pc)
(set concat92 (sub (ext DI avc2v1CRq) (ext DI avc2v1CRp)))
(set avc2copCCR2 (subword SI concat92 0))
(set avc2copCCR3 (subword SI concat92 1))
)
())
(dn16i csub2a1_avc2_v1 "csub2a1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub2a1"))
"csub2a1 $avc2v1CRq,$avc2v1CRp"
(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xb) (f-avc2-v1sub4u0 #x8))
(sequence((DI concat93)) (c-call "check_option_cp" pc)
(set concat93 (sub (ext DI avc2v1CRq) (ext DI avc2v1CRp)))
(set avc2copCCR4 (subword SI concat93 0))
(set avc2copCCR5 (subword SI concat93 1))
)
())
(dn16i caddaa0_avc2_v1 "caddaa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddaa0"))
"caddaa0"
(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa))
(sequence((DI concat94)) (c-call "check_option_cp" pc)
(set concat94 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR2 (subword SI concat94 0))
(set avc2copCCR3 (subword SI concat94 1))
)
())
(dn16i caddaa1_avc2_v1 "caddaa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddaa1"))
"caddaa1"
(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa))
(sequence((DI concat95)) (c-call "check_option_cp" pc)
(set concat95 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR4 (subword SI concat95 0))
(set avc2copCCR5 (subword SI concat95 1))
)
())
(dn16i csubaa0_avc2_v1 "csubaa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csubaa0"))
"csubaa0"
(+ (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa))
(sequence((DI concat96)) (c-call "check_option_cp" pc)
(set concat96 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR2 (subword SI concat96 0))
(set avc2copCCR3 (subword SI concat96 1))
)
())
(dn16i csubaa1_avc2_v1 "csubaa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csubaa1"))
"csubaa1"
(+ (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa))
(sequence((DI concat97)) (c-call "check_option_cp" pc)
(set concat97 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))))
(set avc2copCCR4 (subword SI concat97 0))
(set avc2copCCR5 (subword SI concat97 1))
)
())
(dn32i cmov1_avc2_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1"))
"cmov $avc2v3CRn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CRn avc2v3Rm (f-avc2-v3sub4u28 #x0) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2v3CRn avc2v3Rm)
)
())
(dn32i cmov2_avc2_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2"))
"cmov $avc2v3Rm,$avc2v3CRn"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rm avc2v3CRn (f-avc2-v3sub4u28 #x1) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2v3Rm avc2v3CRn)
)
())
(dn32i cmovi_avc2_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi"))
"cmovi $avc2v3CRq,$avc2v3Imm16s4x24e32"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CRq avc2v3Imm16s4x24e32 (f-avc2-v3sub4u16 #xe))
(sequence() (c-call "check_option_cp" pc)
(set avc2v3CRq (ext SI avc2v3Imm16s4x24e32))
)
())
(dn32i cmovc1_avc2_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1"))
"cmovc $avc2v3CCRn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CCRn avc2v3Rm (f-avc2-v3sub4u28 #x2) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2v3CCRn avc2v3Rm)
)
())
(dn32i cmovc2_avc2_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2"))
"cmovc $avc2v3Rm,$avc2v3CCRn"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rm avc2v3CCRn (f-avc2-v3sub4u28 #x3) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf))
(sequence() (c-call "check_option_cp" pc)
(set avc2v3Rm avc2v3CCRn)
)
())
(dn32i xmula0_avc2_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0"))
"xmula0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x0) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat98)) (c-call "check_option_cp" pc)
(set concat98 (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))
(set avc2copCCR2 (subword SI concat98 0))
(set avc2copCCR3 (subword SI concat98 1))
)
())
(dn32i xmulua0_avc2_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0"))
"xmulua0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x1) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat99)) (c-call "check_option_cp" pc)
(set concat99 (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))
(set avc2copCCR2 (subword SI concat99 0))
(set avc2copCCR3 (subword SI concat99 1))
)
())
(dn32i xnmula0_avc2_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0"))
"xnmula0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x2) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat100)) (c-call "check_option_cp" pc)
(set concat100 (neg (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))))
(set avc2copCCR2 (subword SI concat100 0))
(set avc2copCCR3 (subword SI concat100 1))
)
())
(dn32i xmada0_avc2_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0"))
"xmada0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x4) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat101)) (c-call "check_option_cp" pc)
(set concat101 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))))
(set avc2copCCR2 (subword SI concat101 0))
(set avc2copCCR3 (subword SI concat101 1))
)
())
(dn32i xmadua0_avc2_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0"))
"xmadua0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x5) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat102)) (c-call "check_option_cp" pc)
(set concat102 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))))
(set avc2copCCR2 (subword SI concat102 0))
(set avc2copCCR3 (subword SI concat102 1))
)
())
(dn32i xmsba0_avc2_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0"))
"xmsba0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x6) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat103)) (c-call "check_option_cp" pc)
(set concat103 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))))
(set avc2copCCR2 (subword SI concat103 0))
(set avc2copCCR3 (subword SI concat103 1))
)
())
(dn32i xmsbua0_avc2_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0"))
"xmsbua0 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x7) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat104)) (c-call "check_option_cp" pc)
(set concat104 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))))
(set avc2copCCR2 (subword SI concat104 0))
(set avc2copCCR3 (subword SI concat104 1))
)
())
(dn32i xmula1_avc2_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1"))
"xmula1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x8) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat105)) (c-call "check_option_cp" pc)
(set concat105 (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))
(set avc2copCCR4 (subword SI concat105 0))
(set avc2copCCR5 (subword SI concat105 1))
)
())
(dn32i xmulua1_avc2_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1"))
"xmulua1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x9) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat106)) (c-call "check_option_cp" pc)
(set concat106 (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))
(set avc2copCCR4 (subword SI concat106 0))
(set avc2copCCR5 (subword SI concat106 1))
)
())
(dn32i xnmula1_avc2_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1"))
"xnmula1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xa) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat107)) (c-call "check_option_cp" pc)
(set concat107 (neg (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))))
(set avc2copCCR4 (subword SI concat107 0))
(set avc2copCCR5 (subword SI concat107 1))
)
())
(dn32i xmada1_avc2_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1"))
"xmada1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xc) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat108)) (c-call "check_option_cp" pc)
(set concat108 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))))
(set avc2copCCR4 (subword SI concat108 0))
(set avc2copCCR5 (subword SI concat108 1))
)
())
(dn32i xmadua1_avc2_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1"))
"xmadua1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xd) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat109)) (c-call "check_option_cp" pc)
(set concat109 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))))
(set avc2copCCR4 (subword SI concat109 0))
(set avc2copCCR5 (subword SI concat109 1))
)
())
(dn32i xmsba1_avc2_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1"))
"xmsba1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xe) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat110)) (c-call "check_option_cp" pc)
(set concat110 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))))
(set avc2copCCR4 (subword SI concat110 0))
(set avc2copCCR5 (subword SI concat110 1))
)
())
(dn32i xmsbua1_avc2_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1"))
"xmsbua1 $avc2v3Rn,$avc2v3Rm"
(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xf) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc))
(sequence((DI concat111)) (c-call "check_option_cp" pc)
(set concat111 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))))
(set avc2copCCR4 (subword SI concat111 0))
(set avc2copCCR5 (subword SI concat111 1))
)
())
; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
; Copyright (C) 2001, 2002, 2003, 2004, 2005 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
(include "simplify.inc")
(define-pmacro isa-enum ()
(isas mep
; begin-isa-enum
ext_core1
ext_core2 ext_cop2_16 ext_cop2_32 ext_cop2_48 ext_cop2_64
; end-isa-enum
)
)
(define-arch
(name mep)
(comment "Toshiba MeP Media Engine")
(insn-lsb0? #f) ;; work around cgen limitation
(machs mep h1)
isa-enum
)
(define-isa
(name mep)
(comment "MeP core instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
; begin-isas
(define-isa
(name ext_core1)
(comment "MeP core extension instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_core2)
(comment "MeP core extension instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop2_16)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop2_32)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop2_48)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-isa
(name ext_cop2_64)
(comment "MeP coprocessor instruction set")
(default-insn-word-bitsize 32)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
)
(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_core2,ext_cop2_16,ext_cop2_32,ext_cop2_48,ext_cop2_64))
(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_core2))
(define-pmacro all-core-isa-list () mep,ext_core1,ext_core2)
; end-isas
(define-cpu
(name mepf)
(comment "MeP family")
(endian either)
(insn-chunk-bitsize 16)
(word-bitsize 32)
)
(define-mach
(name mep)
(comment "MeP media engine")
(cpu mepf)
isa-enum
)
(define-mach
(name h1)
(comment "H1 media engine")
(cpu mepf)
isa-enum
)
(define-model
(name mep)
(comment "MeP media engine processor")
(mach mep) ; mach gets changed by MeP-Integrator
(unit u-exec "execution unit" ()
1 1 ; issue done
() () () ())
; Branch unit
(unit u-branch "Branch Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((pc)) ; outputs
() ; profile action (default)
)
; Multiply unit
(unit u-multiply "Multiply Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Divide unit
(unit u-divide "Divide Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Stcb unit
(unit u-stcb "stcb Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Ldcb unit
(unit u-ldcb "ldcb Unit" ()
0 0 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Load gpr unit
(unit u-load-gpr "Load into GPR Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((loadreg INT -1)) ; outputs
() ; profile action (default)
)
(unit u-ldcb-gpr "Ldcb into GPR Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((loadreg INT -1)) ; outputs
() ; profile action (default)
)
; Multiply into GPR unit
(unit u-mul-gpr "Multiply into GPR Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((resultreg INT -1)) ; outputs
() ; profile action (default)
)
; Use gpr unit -- stalls if GPR not ready
(unit u-use-gpr "Use GPR Unit" ()
0 0 ; issue done
() ; state
((usereg INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Use ctrl-reg unit -- stalls if CTRL-REG not ready
(unit u-use-ctrl-reg "Use CTRL-REG Unit" ()
0 0 ; issue done
() ; state
((usereg INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Store ctrl-reg unit -- stalls if CTRL-REG not ready
(unit u-store-ctrl-reg "Store CTRL-REG Unit" ()
0 0 ; issue done
() ; state
() ; inputs
((storereg INT -1)) ; outputs
() ; profile action (default)
)
)
; Hardware elements.
(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ())
(define-hardware
(name h-gpr)
(comment "General purpose registers")
(attrs all-mep-isas CACHE-ADDR PROFILE)
(type register SI (16))
(indices keyword "$"
(("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5)
("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
; "$8" is the preferred name for register 8, but "$tp", "$gp"
; and "$sp" are preferred for their respective registers.
(fp 8) (tp 13) (gp 14) (sp 15)
("12" 12) ("13" 13) ("14" 14) ("15" 15)))
)
(define-hardware
(name h-csr)
(comment "Control/special registers")
(attrs all-mep-isas PROFILE)
(type register SI (32))
(indices keyword "$"
((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6)
(hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15)
(psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21)
(npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28)
; begin-extra-csr-registers
; end-extra-csr-registers
))
(get (index) (c-call SI "cgen_get_csr_value" index))
(set (index newval) (c-call VOID "cgen_set_csr_value" index newval))
)
(define-pmacro (-reg-pair n) ((.sym n) n))
(define-hardware
(name h-cr64)
(comment "64-bit coprocessor registers")
(attrs all-mep-isas)
; This assumes that the data path of the co-pro is 64 bits.
(type register DI (32))
(indices keyword "$c" (.map -reg-pair (.iota 32)))
)
(define-hardware
(name h-cr)
(comment "32-bit coprocessor registers")
(attrs all-mep-isas VIRTUAL)
(type register SI (32))
(indices keyword "$c" (.map -reg-pair (.iota 32)))
(set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
(get (index) (trunc SI (c-call DI "h_cr64_get" index)))
)
;; Given a coprocessor control register number N, expand to a
;; name/index pair: ($ccrN N)
(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n))
(define-hardware
(name h-ccr)
(comment "Coprocessor control registers")
(attrs all-mep-isas)
(type register SI (64))
(indices keyword "" (.map -ccr-reg-pair (.iota 64)))
(set (index newval) (c-call VOID "cgen_set_ccr_value" index newval))
)
; Instruction fields. Bit numbering reversed.
; Conventions:
;
; N = number of bits in value
; A = alignment (2 or 4, omit for 1)
; B = leftmost (i.e. closest to zero) bit position
;
; -- Generic Fields (f-*) --
; N number of bits in *value* (1-24)
; [us] signed vs unsigned
; B position of left-most bit (4-16)
; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc)
; n opt. for noncontiguous fields
; f-foo-{hi,lo} msb/lsb parts of field f-foo
;
; -- Operands --
; pcrelNaA PC-relative branch target (signed)
; pcabsNaA Absolute branch target (unsigned)
;
; [us]dispNaA [un]signed displacement
; [us]immN [un]signed immediate value
; addrNaA absolute address (unsigned)
;
; Additional prefixes may be used for special cases.
(dnf f-major "major opcode" (all-mep-core-isas) 0 4)
(dnf f-rn "register n" (all-mep-core-isas) 4 4)
(dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3)
(dnf f-rm "register m" (all-mep-core-isas) 8 4)
(dnf f-rl "register l" (all-mep-core-isas) 12 4)
(dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2)
(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3)
(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4)
(dnf f-ext "extended field" (all-mep-core-isas) 16 8)
(dnf f-crn "copro register n" (all-mep-core-isas) 4 4)
(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
(df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f)
(define-multi-ifield
(name f-csrn)
(comment "control reg")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-csrn-hi f-csrn-lo)
(insert (sequence ()
(set (ifield f-csrn-lo) (and (ifield f-csrn) #xf))
(set (ifield f-csrn-hi) (srl (ifield f-csrn) 4))))
(extract (set (ifield f-csrn)
(or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo))))
)
(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f)
(df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)
(define-multi-ifield
(name f-crnx)
(comment "copro register n (0-31)")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-crnx-hi f-crnx-lo)
(insert (sequence ()
(set (ifield f-crnx-lo) (and (ifield f-crnx) #xf))
(set (ifield f-crnx-hi) (srl (ifield f-crnx) 4))))
(extract (set (ifield f-crnx)
(or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo))))
)
; Miscellaneous fields.
(define-pmacro (dnfb n)
(dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1))
; Define small fields used throughout the instruction set description.
; Each field (eg. `f-N') is at single bit field at position N.
(dnfb 0)
(dnfb 1)
(dnfb 2)
(dnfb 3)
(dnfb 4)
(dnfb 5)
(dnfb 6)
(dnfb 7)
(dnfb 8)
(dnfb 9)
(dnfb 10)
(dnfb 11)
(dnfb 12)
(dnfb 13)
(dnfb 14)
(dnfb 15)
(dnfb 16)
(dnfb 17)
(dnfb 18)
(dnfb 19)
(dnfb 20)
(dnfb 21)
(dnfb 22)
(dnfb 23)
(dnfb 24)
(dnfb 25)
(dnfb 26)
(dnfb 27)
(dnfb 28)
(dnfb 29)
(dnfb 30)
(dnfb 31)
; Branch/Jump target addresses
(df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT
((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc)))
(df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT
((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc)))
(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT
((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc)))
(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f)
(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f)
(define-multi-ifield
(name f-24s5a2n)
(comment "pc-rel addr (24 bits align 2)")
(attrs all-mep-core-isas PCREL-ADDR)
(mode INT)
(subfields f-24s5a2n-hi f-24s5a2n-lo)
(insert (sequence ()
(set (ifield f-24s5a2n)
(sub (ifield f-24s5a2n) pc))
(set (ifield f-24s5a2n-lo)
(srl (and (ifield f-24s5a2n) #xfe) 1))
(set (ifield f-24s5a2n-hi)
(sra INT (ifield f-24s5a2n) 8))))
(extract (set (ifield f-24s5a2n)
(add SI (or (sll (ifield f-24s5a2n-hi) 8)
(sll (ifield f-24s5a2n-lo) 1))
pc)))
)
(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f)
(define-multi-ifield
(name f-24u5a2n)
(comment "abs jump target (24 bits, alignment 2)")
(attrs all-mep-core-isas ABS-ADDR)
(mode UINT)
(subfields f-24u5a2n-hi f-24u5a2n-lo)
(insert (sequence ()
(set (ifield f-24u5a2n-lo)
(srl (and (ifield f-24u5a2n) #xff) 1))
(set (ifield f-24u5a2n-hi)
(srl (ifield f-24u5a2n) 8))
))
(extract (set (ifield f-24u5a2n)
(or (sll (ifield f-24u5a2n-hi) 8)
(sll (ifield f-24u5a2n-lo) 1))))
)
; Displacement fields.
(df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f)
(df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f)
(df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT
((value pc) (srl SI value 1))
((value pc) (sll SI value 1)))
(df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT
((value pc) (srl SI value 2))
((value pc) (sll SI value 2)))
(df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f)
; Immediate fields.
(df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f)
(df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f)
(df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f)
(df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f)
(df f-5u24 "clip immediate (5 bits)" (all-mep-core-isas) 24 5 UINT #f #f)
(df f-6s8 "add immediate (6 bits)" (all-mep-core-isas) 8 6 INT #f #f)
(df f-8s8 "add imm (8 bits)" (all-mep-core-isas) 8 8 INT #f #f)
(df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f)
(df f-3u29 "cmov fixed 2" (all-mep-core-isas) 29 3 UINT #f #f)
; These are all for the coprocessor opcodes
(df f-8s24 "copro b-offset (8 bits)" (all-mep-core-isas) 24 8 INT #f #f)
(df f-8s24a2 "copro h-offset (8 bits)" (all-mep-core-isas) 24 7 INT
((value pc) (sra SI value 1))
((value pc) (sll SI value 1)))
(df f-8s24a4 "copro w-offset (8 bits)" (all-mep-core-isas) 24 6 INT
((value pc) (sra SI value 2))
((value pc) (sll SI value 2)))
(df f-8s24a8 "copro m-offset (8 bits)" (all-mep-core-isas) 24 5 INT
((value pc) (sra SI value 3))
((value pc) (sll SI value 3)))
; Non-contiguous fields.
(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas) 8 6 UINT #f #f)
(define-multi-ifield
(name f-24u8a4n)
(comment "absolute 24-bit address")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-24u8a4n-hi f-24u8a4n-lo)
(insert (sequence ()
(set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8))
(set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2))))
(extract (set (ifield f-24u8a4n)
(or (sll (ifield f-24u8a4n-hi) 8)
(sll (ifield f-24u8a4n-lo) 2))))
)
(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(df f-24u8n-lo "24u8n lo 8u8" (all-mep-core-isas) 8 8 UINT #f #f)
(define-multi-ifield
(name f-24u8n)
(comment "24-bit constant")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-24u8n-hi f-24u8n-lo)
(insert (sequence ()
(set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8))
(set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff))))
(extract (set (ifield f-24u8n)
(or (sll (ifield f-24u8n-hi) 8)
(ifield f-24u8n-lo))))
)
(df f-24u4n-hi "24u4n hi 8u4" (all-mep-core-isas) 4 8 UINT #f #f)
(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
(define-multi-ifield
(name f-24u4n)
(comment "coprocessor code")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-24u4n-hi f-24u4n-lo)
(insert (sequence ()
(set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16))
(set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff))))
(extract (set (ifield f-24u4n)
(or (sll (ifield f-24u4n-hi) 16)
(ifield f-24u4n-lo))))
)
(define-multi-ifield
(name f-callnum)
(comment "system call number field")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-5 f-6 f-7 f-11)
(insert (sequence ()
(set (ifield f-5) (and (srl (ifield f-callnum) 3) 1))
(set (ifield f-6) (and (srl (ifield f-callnum) 2) 1))
(set (ifield f-7) (and (srl (ifield f-callnum) 1) 1))
(set (ifield f-11) (and (ifield f-callnum) 1))))
(extract (set (ifield f-callnum)
(or (sll (ifield f-5) 3)
(or (sll (ifield f-6) 2)
(or (sll (ifield f-7) 1)
(ifield f-11))))))
)
(df f-ccrn-hi "ccrn hi 2u28" (all-mep-core-isas) 28 2 UINT #f #f)
(df f-ccrn-lo "ccrn lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f)
(define-multi-ifield
(name f-ccrn)
(comment "Coprocessor register number field")
(attrs all-mep-core-isas)
(mode UINT)
(subfields f-ccrn-hi f-ccrn-lo)
(insert (sequence ()
(set (ifield f-ccrn-hi) (and (srl (ifield f-ccrn) 4) #x3))
(set (ifield f-ccrn-lo) (and (ifield f-ccrn) #xf))))
(extract (set (ifield f-ccrn)
(or (sll (ifield f-ccrn-hi) 4)
(ifield f-ccrn-lo))))
)
; Operands.
;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct
;; operation. The others are mostly kept for backwards compatibility,
;; although they do affect the dummy prototypes in
;; gcc/config/mep/intrinsics.h.
(define-attr
(type enum)
(for operand)
(name CDATA)
(comment "datatype to use for C intrinsics mapping")
(values LABEL REGNUM FMAX_FLOAT FMAX_INT
POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT)
(default LONG))
(define-attr
(type integer)
(for operand)
(name ALIGN)
(comment "alignment of immediate operands")
(default 1))
(define-attr
(for operand)
(type boolean)
(name RELOC_IMPLIES_OVERFLOW)
(comment "Operand should not be considered as a candidate for relocs"))
(define-attr
(for hardware)
(type boolean)
(name IS_FLOAT)
(comment "Register contains a floating point value"))
(define-pmacro (dpop name commment attrib hwr field func)
(define-full-operand name comment attrib
hwr DFLT field ((parse func)) () ()))
(define-pmacro (dprp name commment attrib hwr field pafunc prfunc)
(define-full-operand name comment attrib
hwr DFLT field ((parse pafunc) (print prfunc)) () ()))
(dnop r0 "register 0" (all-mep-core-isas) h-gpr 0)
(dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn)
(dnop rm "register Rm" (all-mep-core-isas) h-gpr f-rm)
(dnop rl "register Rl" (all-mep-core-isas) h-gpr f-rl)
(dnop rn3 "register 0-7" (all-mep-core-isas) h-gpr f-rn3)
;; Variants of RM/RN with different CDATA attributes. See comment above
;; CDATA for more details.
(dnop rma "register Rm holding pointer" (all-mep-core-isas (CDATA POINTER)) h-gpr f-rm)
(dnop rnc "register Rn holding char" (all-mep-core-isas (CDATA CHAR)) h-gpr f-rn)
(dnop rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA UCHAR)) h-gpr f-rn)
(dnop rns "register Rn holding short" (all-mep-core-isas (CDATA SHORT)) h-gpr f-rn)
(dnop rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA USHORT)) h-gpr f-rn)
(dnop rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn)
(dnop rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn)
(dnop rn3c "register 0-7 holding unsigned char" (all-mep-core-isas (CDATA CHAR)) h-gpr f-rn3)
(dnop rn3uc "register 0-7 holding byte" (all-mep-core-isas (CDATA UCHAR)) h-gpr f-rn3)
(dnop rn3s "register 0-7 holding unsigned short" (all-mep-core-isas (CDATA SHORT)) h-gpr f-rn3)
(dnop rn3us "register 0-7 holding short" (all-mep-core-isas (CDATA USHORT)) h-gpr f-rn3)
(dnop rn3l "register 0-7 holding unsigned long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3)
(dnop rn3ul "register 0-7 holding long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn3)
(dnop lp "link pointer" (all-mep-core-isas) h-csr 1)
(dnop sar "shift amount register" (all-mep-core-isas) h-csr 2)
(dnop hi "high result" (all-mep-core-isas) h-csr 7)
(dnop lo "low result" (all-mep-core-isas) h-csr 8)
(dnop mb0 "modulo begin register 0" (all-mep-core-isas) h-csr 12)
(dnop me0 "modulo end register 0" (all-mep-core-isas) h-csr 13)
(dnop mb1 "modulo begin register 1" (all-mep-core-isas) h-csr 14)
(dnop me1 "modulo end register 1" (all-mep-core-isas) h-csr 15)
(dnop psw "program status word" (all-mep-core-isas) h-csr 16)
(dnop epc "exception prog counter" (all-mep-core-isas) h-csr 19)
(dnop exc "exception cause" (all-mep-core-isas) h-csr 20)
(dnop npc "nmi program counter" (all-mep-core-isas) h-csr 23)
(dnop dbg "debug register" (all-mep-core-isas) h-csr 24)
(dnop depc "debug exception pc" (all-mep-core-isas) h-csr 25)
(dnop opt "option register" (all-mep-core-isas) h-csr 26)
(dnop r1 "register 1" (all-mep-core-isas) h-gpr 1)
(dnop tp "tiny data area pointer" (all-mep-core-isas) h-gpr 13)
(dnop sp "stack pointer" (all-mep-core-isas) h-gpr 15)
(dprp tpr "TP register" (all-mep-core-isas) h-gpr 13 "tpreg" "tpreg")
(dprp spr "SP register" (all-mep-core-isas) h-gpr 15 "spreg" "spreg")
(define-full-operand
csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr
DFLT f-csrn ((parse "csrn")) () ()
)
(dnop csrn-idx "control/special reg idx" (all-mep-core-isas) h-uint f-csrn)
(dnop crn64 "copro Rn (64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crn)
(dnop crn "copro Rn (32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crn)
(dnop crnx64 "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crnx)
(dnop crnx "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crnx)
(dnop ccrn "copro control reg CCRn" (all-mep-core-isas (CDATA REGNUM)) h-ccr f-ccrn)
(dnop cccc "copro flags" (all-mep-core-isas) h-uint f-rm)
(dprp pcrel8a2 "pc-rel addr (8 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-8s8a2 "mep_align" "address")
(dprp pcrel12a2 "pc-rel addr (12 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-12s4a2 "mep_align" "address")
(dprp pcrel17a2 "pc-rel addr (17 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-17s16a2 "mep_align" "address")
(dprp pcrel24a2 "pc-rel addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-sint f-24s5a2n "mep_align" "address")
(dprp pcabs24a2 "pc-abs addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-uint f-24u5a2n "mep_alignu" "address")
(dpop sdisp16 "displacement (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16")
(dpop simm16 "signed imm (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16")
(dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16")
(dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16)
(dnop udisp2 "SSARB addend (2 bits)" (all-mep-core-isas) h-sint f-2u6)
(dnop uimm2 "interrupt (2 bits)" (all-mep-core-isas) h-uint f-2u10)
(dnop simm6 "add const (6 bits)" (all-mep-core-isas) h-sint f-6s8)
(dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW)
h-sint f-8s8)
(dpop addr24a4 "sw/lw addr (24 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-24u8a4n "mep_alignu")
(dnop code24 "coprocessor code" (all-mep-core-isas) h-uint f-24u4n)
(dnop callnum "system call number" (all-mep-core-isas) h-uint f-callnum)
(dnop uimm3 "bit immediate (3 bits)" (all-mep-core-isas) h-uint f-3u5)
(dnop uimm4 "bCC const (4 bits)" (all-mep-core-isas) h-uint f-4u8)
(dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8)
(dpop udisp7 "tp-rel b (7 bits)" (all-mep-core-isas) h-uint f-7u9 "unsigned7")
(dpop udisp7a2 "tp-rel h (7 bits)" (all-mep-core-isas (ALIGN 2)) h-uint f-7u9a2 "unsigned7")
(dpop udisp7a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "unsigned7")
(dpop uimm7a4 "sp w-addend (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "mep_alignu")
(dnop uimm24 "immediate (24 bits)" (all-mep-core-isas) h-uint f-24u8n)
(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn)
(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24)
(dnop cdisp8 "copro addend (8 bits)" (all-mep-core-isas) h-sint f-8s24)
(dpop cdisp8a2 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 2)) h-sint f-8s24a2 "mep_align")
(dpop cdisp8a4 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 4)) h-sint f-8s24a4 "mep_align")
(dpop cdisp8a8 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 8)) h-sint f-8s24a8 "mep_align")
; Special operand representing the various ways that the literal zero can be
; specified.
(define-full-operand
zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil
((parse "zero")) () ()
)
; Attributes.
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_BIT_INSN)
(comment "optional bit manipulation instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_MUL_INSN)
(comment "optional 32-bit multiply instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_DIV_INSN)
(comment "optional 32-bit divide instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_DEBUG_INSN)
(comment "optional debug instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_LDZ_INSN)
(comment "optional leading zeroes instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_ABS_INSN)
(comment "optional absolute difference instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_AVE_INSN)
(comment "optional average instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_MINMAX_INSN)
(comment "optional min/max instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_CLIP_INSN)
(comment "optional clipping instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_SAT_INSN)
(comment "optional saturation instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_UCI_INSN)
(comment "optional UCI instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_DSP_INSN)
(comment "optional DSP instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_CP_INSN)
(comment "optional coprocessor-related instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_CP64_INSN)
(comment "optional coprocessor-related 64 data bit instruction"))
(define-attr
(for insn)
(type boolean)
(name OPTIONAL_VLIW64)
(comment "optional vliw64 mode (vliw32 is default)"))
(define-attr
(for insn)
(type enum)
(name STALL)
(attrs META)
(values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET
ADVCK MUL MULR DIV)
(default NONE)
(comment "gcc stall attribute"))
(define-attr
(for insn)
(type string)
(name INTRINSIC)
(attrs META)
(comment "gcc intrinsic name"))
(define-attr
(for insn)
(type enum)
(name SLOT)
(attrs META)
(values NONE C3 V1 V3)
(default NONE)
(comment "coprocessor slot type"))
(define-attr
(for insn)
(type boolean)
(name MAY_TRAP)
(comment "instruction may generate an exception"))
; Attributes for scheduling restrictions in vliw mode
(define-attr
(for insn)
(type boolean)
(name VLIW_ALONE)
(comment "instruction can be scheduled alone in vliw mode"))
(define-attr
(for insn)
(type boolean)
(name VLIW_NO_CORE_NOP)
(comment "there is no corresponding nop core instruction"))
(define-attr
(for insn)
(type boolean)
(name VLIW_NO_COP_NOP)
(comment "there is no corresponding nop coprocessor instruction"))
(define-attr
(for insn)
(type boolean)
(name VLIW64_NO_MATCHING_NOP)
(comment "there is no corresponding nop coprocessor instruction"))
(define-attr
(for insn)
(type boolean)
(name VLIW32_NO_MATCHING_NOP)
(comment "there is no corresponding nop coprocessor instruction"))
(define-attr
(for insn)
(type boolean)
(name VOLATILE)
(comment "Insn is volatile."))
(define-attr
(for insn)
(type integer)
(name LATENCY)
(comment "The latency of this insn, used for scheduling as an intrinsic in gcc")
(default 0))
; The MeP config tool will edit this.
(define-attr
(type enum)
(for insn)
(name CONFIG)
(values NONE ; config-attr-start
simple
fmax
) ; config-attr-end
)
; Enumerations.
(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_
f-major
(.map .str (.iota 16))
)
(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa)
(define-insn
(name xname)
(comment xcomment)
(.splice attrs (.unsplice xattrs) (ISA isa))
(syntax xsyntax)
(format xformat)
(semantics xsemantics)
(.splice timing (.unsplice xtiming))
)
)
(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa)
(dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit)
)
; For making profiling calls and dynamic configuration
(define-pmacro (cg-profile caller callee)
(c-call "cg_profile" caller callee)
)
; For dynamic configuration only
(define-pmacro (cg-profile-jump caller callee)
(c-call "cg_profile_jump" caller callee)
)
; For defining Core Instructions
(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming)
(dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list)
)
(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit)
(dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list)
)
; For defining Coprocessor Instructions
;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop)
;)
;; flag setting macro
(define-pmacro (set-bit xop xbitnum xval)
(set xop (or
(and xop (inv (sll 1 xbitnum)))
(and (sll 1 xbitnum) (sll xval xbitnum)))))
;; some flags we commonly use in vliw reasoning / mode-switching etc.
(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1))
(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1))
(define-pmacro (get-rm.lsb) (and rm 1))
(define-pmacro (get-psw.om) (and (srl psw 12) 1))
(define-pmacro (get-psw.nmi) (and (srl psw 9) 1))
(define-pmacro (get-psw.iep) (and (srl psw 1) 1))
(define-pmacro (get-psw.ump) (and (srl psw 3) 1))
(define-pmacro (get-epc.etom) (and epc 1))
(define-pmacro (get-npc.ntom) (and npc 1))
(define-pmacro (get-lp.ltom) (and lp 1))
(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval))
(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval))
(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval))
(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval))
(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval))
;; the "3 way switch" depending on our current operating mode and vliw status flags
(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl)
(cond
((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl)
((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl)
(else core-rtl)))
;; the varying-pcrel idiom
(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc)
(core-vliw-switch (set xtarg (add pc xa))
(set xtarg (add pc xb))
(set xtarg (add pc xc))))
;; the increasing-alignment idiom in branch displacements
(define-pmacro (set-vliw-alignment-modified xtarg zaddr)
(core-vliw-switch (set xtarg (and zaddr (inv 1)))
(set xtarg (and zaddr (inv 3)))
(set xtarg (and zaddr (inv 7)))))
;; the increasing-alignment idiom in option-only form
(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr)
(if (get-opt.vliw32)
(set xtarg (and zaddr (inv 3)))
(set xtarg (and zaddr (inv 7)))))
; Instructions.
; A pmacro for use in semantic bodies of unimplemented insns.
(define-pmacro (unimp mnemonic) (nop))
; Core specific instructions
; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
; Load/store instructions.
(dnci sb "store byte (register indirect)" ((STALL STORE))
"sb $rnc,($rma)"
(+ MAJ_0 rnc rma (f-sub4 8))
(sequence ()
(c-call VOID "check_write_to_text" rma)
(set (mem UQI rma) (and rnc #xff)))
((mep (unit u-use-gpr (in usereg rnc))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sh "store half-word (register indirect)" ((STALL STORE))
"sh $rns,($rma)"
(+ MAJ_0 rns rma (f-sub4 9))
(sequence ()
(c-call VOID "check_write_to_text" (and rma (inv 1)))
(set (mem UHI (and rma (inv 1))) (and rns #xffff)))
((mep (unit u-use-gpr (in usereg rns))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sw "store word (register indirect)" ((STALL STORE))
"sw $rnl,($rma)"
(+ MAJ_0 rnl rma (f-sub4 10))
(sequence ()
(c-call VOID "check_write_to_text" (and rma (inv 3)))
(set (mem USI (and rma (inv 3))) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2))
"lb $rnc,($rma)"
(+ MAJ_0 rnc rma (f-sub4 12))
(set rnc (ext SI (mem QI rma)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnc)))))
(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
"lh $rns,($rma)"
(+ MAJ_0 rns rma (f-sub4 13))
(set rns (ext SI (mem HI (and rma (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rns)))))
(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,($rma)"
(+ MAJ_0 rnl rma (f-sub4 14))
(set rnl (mem SI (and rma (inv 3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2))
"lbu $rnuc,($rma)"
(+ MAJ_0 rnuc rma (f-sub4 11))
(set rnuc (zext SI (mem UQI rma)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnuc)))))
(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
"lhu $rnus,($rma)"
(+ MAJ_0 rnus rma (f-sub4 15))
(set rnus (zext SI (mem UHI (and rma (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnus)))))
(dnci sw-sp "store word (sp relative)" ((STALL STORE))
"sw $rnl,$udisp7a4($spr)"
(+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2))
(sequence ()
(c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3)))
(set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-use-gpr (in usereg sp))
(unit u-exec))))
(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,$udisp7a4($spr)"
(+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3))
(set rnl (mem SI (and (add udisp7a4 sp) (inv 3))))
((mep (unit u-use-gpr (in usereg sp))
(unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
(dnci sb-tp "store byte (tp relative)" ((STALL STORE))
"sb $rn3c,$udisp7($tpr)"
(+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7)
(sequence ()
(c-call VOID "check_write_to_text" (add (zext SI udisp7) tp))
(set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff)))
((mep (unit u-use-gpr (in usereg rn3c))
(unit u-use-gpr (in usereg tp))
(unit u-exec))))
(dnci sh-tp "store half-word (tp relative)" ((STALL STORE))
"sh $rn3s,$udisp7a2($tpr)"
(+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0))
(sequence ()
(c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1)))
(set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff)))
((mep (unit u-use-gpr (in usereg rn3s))
(unit u-use-gpr (in usereg tp))
(unit u-exec))))
(dnci sw-tp "store word (tp relative)" ((STALL STORE))
"sw $rn3l,$udisp7a4($tpr)"
(+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2))
(sequence ()
(c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3)))
(set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l))
((mep (unit u-use-gpr (in usereg rn3l))
(unit u-use-gpr (in usereg tp))
(unit u-exec))))
(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2))
"lb $rn3c,$udisp7($tpr)"
(+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7)
(set rn3c (ext SI (mem QI (add (zext SI udisp7) tp))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3c)))))
(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
"lh $rn3s,$udisp7a2($tpr)"
(+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0))
(set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3s)))))
(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2))
"lw $rn3l,$udisp7a4($tpr)"
(+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3))
(set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3l)))))
(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2))
"lbu $rn3uc,$udisp7($tpr)"
(+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7)
(set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3uc)))))
(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
"lhu $rn3us,$udisp7a2($tpr)"
(+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1))
(set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
((mep (unit u-use-gpr (in usereg tp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn3us)))))
(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE))
"sb $rnc,$sdisp16($rma)"
(+ MAJ_12 rnc rma (f-sub4 8) sdisp16)
(sequence ()
(c-call VOID "check_write_to_text" (add rma (ext SI sdisp16)))
(set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff)))
((mep (unit u-use-gpr (in usereg rnc))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE))
"sh $rns,$sdisp16($rma)"
(+ MAJ_12 rns rma (f-sub4 9) sdisp16)
(sequence ()
(c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1)))
(set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff)))
((mep (unit u-use-gpr (in usereg rns))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sw16 "store word (16 bit displacement)" ((STALL STORE))
"sw $rnl,$sdisp16($rma)"
(+ MAJ_12 rnl rma (f-sub4 10) sdisp16)
(sequence ()
(c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3)))
(set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lb $rnc,$sdisp16($rma)"
(+ MAJ_12 rnc rma (f-sub4 12) sdisp16)
(set rnc (ext SI (mem QI (add rma (ext SI sdisp16)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnc)))))
(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lh $rns,$sdisp16($rma)"
(+ MAJ_12 rns rma (f-sub4 13) sdisp16)
(set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rns)))))
(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,$sdisp16($rma)"
(+ MAJ_12 rnl rma (f-sub4 14) sdisp16)
(set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lbu $rnuc,$sdisp16($rma)"
(+ MAJ_12 rnuc rma (f-sub4 11) sdisp16)
(set rnuc (zext SI (mem QI (add rma (ext SI sdisp16)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnuc)))))
(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
"lhu $rnus,$sdisp16($rma)"
(+ MAJ_12 rnus rma (f-sub4 15) sdisp16)
(set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-load-gpr (out loadreg rnus)))))
(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE))
"sw $rnl,($addr24a4)"
(+ MAJ_14 rnl addr24a4 (f-sub2 2))
(sequence ()
(c-call VOID "check_write_to_text" (zext SI addr24a4))
(set (mem SI (zext SI addr24a4)) rnl))
((mep (unit u-use-gpr (in usereg rnl))
(unit u-exec))))
(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2))
"lw $rnl,($addr24a4)"
(+ MAJ_14 rnl addr24a4 (f-sub2 3))
(set rnl (mem SI (zext SI addr24a4)))
((mep (unit u-exec)
(unit u-load-gpr (out loadreg rnl)))))
; Extension instructions.
(dnci extb "sign extend byte" ()
"extb $rn"
(+ MAJ_1 rn (f-rm 0) (f-sub4 13))
(set rn (ext SI (and QI rn #xff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci exth "sign extend half-word" ()
"exth $rn"
(+ MAJ_1 rn (f-rm 2) (f-sub4 13))
(set rn (ext SI (and HI rn #xffff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci extub "zero extend byte" ()
"extub $rn"
(+ MAJ_1 rn (f-rm 8) (f-sub4 13))
(set rn (zext SI (and rn #xff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci extuh "zero extend half-word" ()
"extuh $rn"
(+ MAJ_1 rn (f-rm 10) (f-sub4 13))
(set rn (zext SI (and rn #xffff)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Shift amount manipulation instructions.
(dnci ssarb "set sar to bytes" ((STALL SSARB))
"ssarb $udisp2($rm)"
(+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12))
(if (c-call BI "big_endian_p")
(set sar (zext SI (mul (and (add udisp2 rm) 3) 8)))
(set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8)))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Move instructions.
(dnci mov "move" ()
"mov $rn,$rm"
(+ MAJ_0 rn rm (f-sub4 0))
(set rn rm)
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci movi8 "move 8-bit immediate" ()
"mov $rn,$simm8"
(+ MAJ_5 rn simm8)
(set rn (ext SI simm8))
())
(dnci movi16 "move 16-bit immediate" ()
"mov $rn,$simm16"
(+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16)
(set rn (ext SI simm16))
())
(dnci movu24 "move 24-bit unsigned immediate" ()
"movu $rn3,$uimm24"
(+ MAJ_13 (f-4 0) rn3 uimm24)
(set rn3 (zext SI uimm24))
())
(dnci movu16 "move 16-bit unsigned immediate" ()
"movu $rn,$uimm16"
(+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16)
(set rn (zext SI uimm16))
())
(dnci movh "move high 16-bit immediate" ()
"movh $rn,$uimm16"
(+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16)
(set rn (sll uimm16 16))
())
; Arithmetic instructions.
(dnci add3 "add three registers" ()
"add3 $rl,$rn,$rm"
(+ MAJ_9 rn rm rl)
(set rl (add rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci add "add" ()
"add $rn,$simm6"
(+ MAJ_6 rn simm6 (f-sub2 0))
(set rn (add rn (ext SI simm6)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci add3i "add two registers and immediate" ()
"add3 $rn,$spr,$uimm7a4"
(+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0))
(set rn (add sp (zext SI uimm7a4)))
((mep (unit u-use-gpr (in usereg sp))
(unit u-exec))))
(dnci advck3 "add overflow check" ((STALL ADVCK))
"advck3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 7))
(if (add-oflag rn rm 0)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sub "subtract" ()
"sub $rn,$rm"
(+ MAJ_0 rn rm (f-sub4 4))
(set rn (sub rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm)))))
(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK))
"sbvck3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 5))
(if (sub-oflag rn rm 0)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci neg "negate" ()
"neg $rn,$rm"
(+ MAJ_0 rn rm (f-sub4 1))
(set rn (neg rm))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci slt3 "set if less than" ()
"slt3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 2))
(if (lt rn rm)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sltu3 "set less than unsigned" ()
"sltu3 \\$0,$rn,$rm"
(+ MAJ_0 rn rm (f-sub4 3))
(if (ltu rn rm)
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci slt3i "set if less than immediate" ()
"slt3 \\$0,$rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 1))
(if (lt rn (zext SI uimm5))
(set r0 1)
(set r0 0))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci sltu3i "set if less than unsigned immediate" ()
"sltu3 \\$0,$rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 5))
(if (ltu rn (zext SI uimm5))
(set r0 1)
(set r0 0))
())
(dnci sl1ad3 "shift left one and add" ((STALL INT2))
"sl1ad3 \\$0,$rn,$rm"
(+ MAJ_2 rn rm (f-sub4 6))
(set r0 (add (sll rn 1) rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sl2ad3 "shift left two and add" ((STALL INT2))
"sl2ad3 \\$0,$rn,$rm"
(+ MAJ_2 rn rm (f-sub4 7))
(set r0 (add (sll rn 2) rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci add3x "three operand add (extended)" ()
"add3 $rn,$rm,$simm16"
(+ MAJ_12 rn rm (f-sub4 0) simm16)
(set rn (add rm (ext SI simm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci slt3x "set if less than (extended)" ()
"slt3 $rn,$rm,$simm16"
(+ MAJ_12 rn rm (f-sub4 2) simm16)
(if (lt rm (ext SI simm16))
(set rn 1)
(set rn 0))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sltu3x "set if less than unsigned (extended)" ()
"sltu3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 3) uimm16)
(if (ltu rm (zext SI uimm16))
(set rn 1)
(set rn 0))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Logical instructions.
(dnci or "bitwise or" ()
"or $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 0))
(set rn (or rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci and "bitwise and" ()
"and $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 1))
(set rn (and rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci xor "bitwise exclusive or" ()
"xor $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 2))
(set rn (xor rn rm))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci nor "bitwise negated or" ()
"nor $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 3))
(set rn (inv (or rn rm)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci or3 "or three operand" ()
"or3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 4) uimm16)
(set rn (or rm (zext SI uimm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci and3 "and three operand" ()
"and3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 5) uimm16)
(set rn (and rm (zext SI uimm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci xor3 "exclusive or three operand" ()
"xor3 $rn,$rm,$uimm16"
(+ MAJ_12 rn rm (f-sub4 6) uimm16)
(set rn (xor rm (zext SI uimm16)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Shift instructions.
(dnci sra "shift right arithmetic" ((STALL INT2))
"sra $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 13))
(set rn (sra rn (and rm #x1f)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci srl "shift right logical" ((STALL INT2))
"srl $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 12))
(set rn (srl rn (and rm #x1f)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci sll "shift left logical" ((STALL INT2))
"sll $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 14))
(set rn (sll rn (and rm #x1f)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI))
"sra $rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 3))
(set rn (sra rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci srli "shift right logical (immediate)" ((STALL SHIFTI))
"srl $rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 2))
(set rn (srl rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci slli "shift left logical (immediate)" ((STALL SHIFTI))
"sll $rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 6))
(set rn (sll rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci sll3 "three-register shift left logical" ((STALL INT2))
"sll3 \\$0,$rn,$uimm5"
(+ MAJ_6 rn uimm5 (f-sub3 7))
(set r0 (sll rn uimm5))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci fsft "field shift" ((STALL FSFT))
"fsft $rn,$rm"
(+ MAJ_2 rn rm (f-sub4 15))
(sequence ((DI temp) (QI shamt))
(set shamt (and sar #x3f))
(set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt))
(set rn (subword SI (srl temp 32) 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Branch/jump instructions.
(dnci bra "branch" (RELAXABLE)
"bra $pcrel12a2"
(+ MAJ_11 pcrel12a2 (f-15 0))
(set-vliw-alignment-modified pc pcrel12a2)
((mep (unit u-branch)
(unit u-exec))))
(dnci beqz "branch if equal zero" (RELAXABLE)
"beqz $rn,$pcrel8a2"
(+ MAJ_10 rn pcrel8a2 (f-15 0))
(if (eq rn 0)
(set-vliw-alignment-modified pc pcrel8a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci bnez "branch if not equal zero" (RELAXABLE)
"bnez $rn,$pcrel8a2"
(+ MAJ_10 rn pcrel8a2 (f-15 1))
(if (ne rn 0)
(set-vliw-alignment-modified pc pcrel8a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci beqi "branch equal immediate" (RELAXABLE)
"beqi $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2)
(if (eq rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci bnei "branch not equal immediate" (RELAXABLE)
"bnei $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2)
(if (ne rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci blti "branch less than immediate" (RELAXABLE)
"blti $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2)
(if (lt rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci bgei "branch greater than immediate" (RELAXABLE)
"bgei $rn,$uimm4,$pcrel17a2"
(+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2)
(if (ge rn (zext SI uimm4))
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-branch))))
(dnci beq "branch equal" ()
"beq $rn,$rm,$pcrel17a2"
(+ MAJ_14 rn rm (f-sub4 1) pcrel17a2)
(if (eq rn rm)
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci bne "branch not equal" ()
"bne $rn,$rm,$pcrel17a2"
(+ MAJ_14 rn rm (f-sub4 5) pcrel17a2)
(if (ne rn rm)
(set-vliw-alignment-modified pc pcrel17a2))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE)
"bsr $pcrel12a2"
(+ MAJ_11 pcrel12a2 (f-15 1))
(sequence ()
(cg-profile pc pcrel12a2)
(set-vliw-modified-pcrel-offset lp 2 4 8)
(set-vliw-alignment-modified pc pcrel12a2))
((mep (unit u-exec)
(unit u-branch))))
(dnci bsr24 "branch to subroutine (24 bit displacement)" ()
"bsr $pcrel24a2"
(+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2)
(sequence ()
(cg-profile pc pcrel24a2)
(set-vliw-modified-pcrel-offset lp 4 4 8)
(set-vliw-alignment-modified pc pcrel24a2))
((mep (unit u-exec)
(unit u-branch))))
(dnci jmp "jump" ()
"jmp $rm"
(+ MAJ_1 (f-rn 0) rm (f-sub4 14))
(sequence ()
(if (eq (get-psw.om) 0)
;; core mode
(if (get-rm.lsb)
(sequence ()
(set-psw.om 1) ;; enter VLIW mode
(set-vliw-aliignment-modified-by-option pc rm))
(set pc (and rm (inv 1))))
;; VLIW mode
(if (get-rm.lsb)
(sequence ()
(set-psw.om 0) ;; enter core mode
(set pc (and rm (inv 1))))
(set-vliw-aliignment-modified-by-option pc rm)))
(cg-profile-jump pc rm))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci jmp24 "jump (24 bit target)" ()
"jmp $pcabs24a2"
(+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2)
(sequence ()
(set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2))
(cg-profile-jump pc pcabs24a2))
((mep (unit u-exec)
(unit u-branch))))
(dnci jsr "jump to subroutine" ()
"jsr $rm"
(+ MAJ_1 (f-rn 0) rm (f-sub4 15))
(sequence ()
(cg-profile pc rm)
(set-vliw-modified-pcrel-offset lp 2 4 8)
(set-vliw-alignment-modified pc rm))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci ret "return from subroutine" ((STALL RET))
"ret"
(+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2))
(sequence ()
(if (eq (get-psw.om) 0)
;; core mode
(if (get-lp.ltom) ;; link-pointer "toggle mode" bit
(sequence ()
(set-psw.om 1) ;; enter VLIW mode
(set-vliw-aliignment-modified-by-option pc lp))
(set pc (and lp (inv 1))))
;; VLIW mode
(if (get-lp.ltom) ;; link-pointer "toggle mode" bit
(sequence ()
(set-psw.om 0) ;; enter VLIW mode
(set pc (and lp (inv 1))))
(set-vliw-aliignment-modified-by-option pc lp)))
(c-call VOID "notify_ret" pc))
((mep (unit u-exec)
(unit u-branch))))
; Repeat instructions.
(dnci repeat "repeat specified repeat block" ()
"repeat $rn,$pcrel17a2"
(+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2)
(sequence ()
(set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
(set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
(set (reg h-csr 6) rn))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci erepeat "endless repeat" ()
"erepeat $pcrel17a2"
(+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2)
(sequence ()
(set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
(set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
(set-rpe.elr 1)
; rpc may be undefined for erepeat
; use 1 to trigger repeat logic in the sim's main loop
(set (reg h-csr 6) 1))
())
; Control instructions.
;; special store variants
(dnci stc_lp "store to control register lp" ((STALL STC))
"stc $rn,\\$lp"
(+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
(set lp rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg lp))
(unit u-exec))))
(dnci stc_hi "store to control register hi" ((STALL STC))
"stc $rn,\\$hi"
(+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
(set hi rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg hi))
(unit u-exec))))
(dnci stc_lo "store to control register lo" ((STALL STC))
"stc $rn,\\$lo"
(+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
(set lo rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg lo))
(unit u-exec))))
;; general store
(dnci stc "store to control register" (VOLATILE (STALL STC))
"stc $rn,$csrn"
(+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0))
(set csrn rn)
((mep (unit u-use-gpr (in usereg rn))
(unit u-store-ctrl-reg (out storereg csrn))
(unit u-exec))))
;; special load variants
(dnci ldc_lp "load from control register lp" ((STALL LDC))
"ldc $rn,\\$lp"
(+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
(set rn lp)
((mep (unit u-use-ctrl-reg (in usereg lp))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
(dnci ldc_hi "load from control register hi" ((STALL LDC))
"ldc $rn,\\$hi"
(+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
(set rn hi)
((mep (unit u-use-ctrl-reg (in usereg hi))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
(dnci ldc_lo "load from control register lo" ((STALL LDC))
"ldc $rn,\\$lo"
(+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
(set rn lo)
((mep (unit u-use-ctrl-reg (in usereg lo))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
;; general load
(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2))
"ldc $rn,$csrn"
(+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1))
(if (eq (ifield f-csrn) 0)
;; loading from the pc
(set-vliw-modified-pcrel-offset rn 2 4 8)
;; loading from something else
(set rn csrn))
((mep (unit u-use-ctrl-reg (in usereg csrn))
(unit u-exec)
(unit u-load-gpr (out loadreg rn)))))
(dnci di "disable interrupt" (VOLATILE)
"di"
(+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0))
; clear psw.iec
(set psw (sll (srl psw 1) 1))
())
(dnci ei "enable interrupt" (VOLATILE)
"ei"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0))
; set psw.iec
(set psw (or psw 1))
())
(dnci reti "return from interrupt" ((STALL RET))
"reti"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2))
(if (eq (get-psw.om) 0)
;; core operation mode
(if (get-psw.nmi)
;; return from NMI
(if (get-npc.ntom)
;; return in VLIW operation mode
(sequence ()
(set-psw.om 1)
(set-vliw-aliignment-modified-by-option pc npc)
(set-psw.nmi 0))
;; return in core mode
(sequence ()
(set pc (and npc (inv 1)))
(set-psw.nmi 0)))
;; return from non-NMI
(if (get-epc.etom)
;; return in VLIW mode
(sequence ()
(set-psw.om 1)
(set-vliw-aliignment-modified-by-option pc epc)
(set-psw.umc (get-psw.ump))
(set-psw.iec (get-psw.iep)))
;; return in core mode
(sequence ()
(set pc (and epc (inv 1)))
(set-psw.umc (get-psw.ump))
(set-psw.iec (get-psw.iep)))))
;; VLIW operation mode
;; xxx undefined
(nop))
((mep (unit u-exec)
(unit u-branch))))
(dnci halt "halt pipeline" (VOLATILE)
"halt"
(+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2))
; set psw.halt
(set (raw-reg h-csr 16) (or psw (sll 1 11)))
())
(dnci sleep "sleep pipeline" (VOLATILE)
"sleep"
(+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2))
(c-call VOID "do_sleep")
())
(dnci swi "software interrupt" (MAY_TRAP VOLATILE)
"swi $uimm2"
(+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6))
(cond
((eq uimm2 0) (set exc (or exc (sll 1 4))))
((eq uimm2 1) (set exc (or exc (sll 1 5))))
((eq uimm2 2) (set exc (or exc (sll 1 6))))
((eq uimm2 3) (set exc (or exc (sll 1 7)))))
())
(dnci break "break exception" (MAY_TRAP VOLATILE)
"break"
(+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2))
(set pc (c-call USI "break_exception" pc))
((mep (unit u-exec)
(unit u-branch))))
(dnci syncm "synchronise with memory" (VOLATILE)
"syncm"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1))
(unimp "syncm")
())
(dnci stcb "store in control bus space" (VOLATILE (STALL STCB))
"stcb $rn,$uimm16"
(+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16)
(c-call VOID "do_stcb" rn uimm16)
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec)
(unit u-stcb))))
(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3))
"ldcb $rn,$uimm16"
(+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16)
(set rn (c-call SI "do_ldcb" uimm16))
((mep (unit u-ldcb)
(unit u-exec)
(unit u-ldcb-gpr (out loadreg rn)))))
; Bit manipulation instructions.
; The following instructions become the reserved instruction when the
; bit manipulation option is off.
(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN)
"bsetm ($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0))
(sequence ()
(c-call "check_option_bit" pc)
(set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN)
"bclrm ($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1))
(sequence ()
(c-call "check_option_bit" pc)
(set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN)
"bnotm ($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2))
(sequence ()
(c-call "check_option_bit" pc)
(set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN)
"btstm \\$0,($rma),$uimm3"
(+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3))
(sequence ()
(c-call "check_option_bit" pc)
(set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci tas "test and set" (OPTIONAL_BIT_INSN)
"tas $rn,($rma)"
(+ MAJ_2 rn rma (f-sub4 4))
(sequence ((SI result))
(c-call "check_option_bit" pc)
(set result (zext SI (mem UQI rma)))
(set (mem UQI rma) 1)
(set rn result))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
; Data cache instruction.
(dnci cache "cache operations" (VOLATILE)
"cache $cimm4,($rma)"
(+ MAJ_7 cimm4 rma (f-sub4 4))
(c-call VOID "do_cache" cimm4 rma pc)
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
; Multiply instructions.
; These instructions become the RI when the 32-bit multiply
; instruction option is off.
(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL))
"mul $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 4))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (ext DI rn) (ext DI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
"mulu $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 5))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (zext UDI rn) (zext UDI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"mulr $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 6))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (ext DI rn) (ext DI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"mulru $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 7))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (mul (zext UDI rn) (zext UDI rm)))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL))
"madd $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (ext DI rn) (ext DI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
"maddu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (zext UDI rn) (zext UDI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply))))
(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"maddr $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (ext DI rn) (ext DI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
"maddru $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007))
(sequence ((DI result))
(c-call "check_option_mul" pc)
(set result (or (sll (zext DI hi) 32) (zext DI lo)))
(set result (add result (mul (zext UDI rn) (zext UDI rm))))
(set hi (subword SI result 0))
(set lo (subword SI result 1))
(set rn (subword SI result 1)))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-multiply)
(unit u-mul-gpr (out resultreg rn)))))
; Divide instructions.
; These instructions become the RI when the 32-bit divide instruction
; option is off.
(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
"div $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 8))
(sequence ()
(c-call "check_option_div" pc)
(if (eq rm 0)
(set pc (c-call USI "zdiv_exception" pc))
; Special case described on p. 76.
(if (and (eq rn #x80000000)
(eq rm #xffffffff))
(sequence ()
(set lo #x80000000)
(set hi 0))
(sequence ()
(set lo (div rn rm))
(set hi (mod rn rm))))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-divide)
(unit u-branch))))
(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
"divu $rn,$rm"
(+ MAJ_1 rn rm (f-sub4 9))
(sequence ()
(c-call "check_option_div" pc)
(if (eq rm 0)
(set pc (c-call USI "zdiv_exception" pc))
(sequence ()
(set lo (udiv rn rm))
(set hi (umod rn rm)))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-divide)
(unit u-branch))))
; Debug functions.
; These instructions become the RI when the debug function option is
; off.
(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN)
"dret"
(+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3))
(sequence ()
(c-call "check_option_debug" pc)
; set DBG.DM.
(set dbg (and dbg (inv (sll SI 1 15))))
(set pc depc))
((mep (unit u-exec)
(unit u-branch))))
(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE)
"dbreak"
(+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3))
(sequence ()
(c-call "check_option_debug" pc)
; set DBG.DPB.
(set dbg (or dbg 1)))
())
; Leading zero instruction.
(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2))
"ldz $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0))
(sequence ()
(c-call "check_option_ldz" pc)
(set rn (c-call SI "do_ldz" rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec))))
; Absolute difference instruction.
(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2))
"abs $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3))
(sequence ()
(c-call "check_option_abs" pc)
(set rn (abs (sub rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Average instruction.
(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2))
"ave $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2))
(sequence ()
(c-call "check_option_ave" pc)
(set rn (sra (add (add rn rm) 1) 1)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; MIN/MAX instructions.
(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2))
"min $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4))
(sequence ()
(c-call "check_option_minmax" pc)
(if (gt rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2))
"max $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5))
(sequence ()
(c-call "check_option_minmax" pc)
(if (lt rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
"minu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6))
(sequence ()
(c-call "check_option_minmax" pc)
(if (gtu rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
"maxu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7))
(sequence ()
(c-call "check_option_minmax" pc)
(if (ltu rn rm)
(set rn rm)))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Clipping instruction.
(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2))
"clip $rn,$cimm5"
(+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0))
(sequence ((SI min) (SI max))
(c-call "check_option_clip" pc)
(set max (sub (sll 1 (sub cimm5 1)) 1))
(set min (neg (sll 1 (sub cimm5 1))))
(cond
((eq cimm5 0) (set rn 0))
((gt rn max) (set rn max))
((lt rn min) (set rn min))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2))
"clipu $rn,$cimm5"
(+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1))
(sequence ((SI max))
(c-call "check_option_clip" pc)
(set max (sub (sll 1 cimm5) 1))
(cond
((eq cimm5 0) (set rn 0))
((gt rn max) (set rn max))
((lt rn 0) (set rn 0))))
((mep (unit u-use-gpr (in usereg rn))
(unit u-exec))))
; Saturation instructions.
(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2))
"sadd $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8))
(sequence ()
(c-call "check_option_sat" pc)
(if (add-oflag rn rm 0)
(if (nflag rn)
; underflow
(set rn (neg (sll 1 31)))
; overflow
(set rn (sub (sll 1 31) 1)))
(set rn (add rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
"ssub $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10))
(sequence ()
(c-call "check_option_sat" pc)
(if (sub-oflag rn rm 0)
(if (nflag rn)
; underflow
(set rn (neg (sll 1 31)))
; overflow
(set rn (sub (sll 1 31) 1)))
(set rn (sub rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2))
"saddu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9))
(sequence ()
(c-call "check_option_sat" pc)
(if (add-cflag rn rm 0)
(set rn (inv 0))
(set rn (add rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
"ssubu $rn,$rm"
(+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11))
(sequence ()
(c-call "check_option_sat" pc)
(if (sub-cflag rn rm 0)
(set rn 0)
(set rn (sub rn rm))))
((mep (unit u-use-gpr (in usereg rm))
(unit u-use-gpr (in usereg rn))
(unit u-exec))))
; UCI and DSP options are defined in an external file.
; See `mep-sample-ucidsp.cpu' for a sample.
; Coprocessor instructions.
(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"swcp $crn,($rma)"
(+ MAJ_3 crn rma (f-sub4 8))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcp $crn,($rma)"
(+ MAJ_3 crn rma (f-sub4 9))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcp $crn64,($rma)"
(+ MAJ_3 crn64 rma (f-sub4 10))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcp" rma crn64 pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcp $crn64,($rma)"
(+ MAJ_3 crn64 rma (f-sub4 11))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE))
"swcpi $crn,($rma+)"
(+ MAJ_3 crn rma (f-sub4 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (add rma 4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcpi $crn,($rma+)"
(+ MAJ_3 crn rma (f-sub4 1))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
(set rma (add rma 4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcpi $crn64,($rma+)"
(+ MAJ_3 crn64 rma (f-sub4 2))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcpi" (index-of rma) crn64 pc)
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcpi $crn64,($rma+)"
(+ MAJ_3 crn64 rma (f-sub4 3))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcpi" (index-of rma) pc))
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE))
"swcp $crn,$sdisp16($rma)"
(+ MAJ_15 crn rma (f-sub4 12) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(set (mem SI (and (add rma sdisp16) (inv SI 3))) crn))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcp $crn,$sdisp16($rma)"
(+ MAJ_15 crn rma (f-sub4 13) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and (add rma sdisp16) (inv SI 3)))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcp $crn64,$sdisp16($rma)"
(+ MAJ_15 crn64 rma (f-sub4 14) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call "do_smcp16" rma sdisp16 crn64 pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcp $crn64,$sdisp16($rma)"
(+ MAJ_15 crn64 rma (f-sub4 15) sdisp16)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"sbcpa $crn,($rma+),$cdisp8"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext 0) cdisp8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
(set rma (add rma (ext SI cdisp8))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lbcpa $crn,($rma+),$cdisp8"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x40) cdisp8)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
(set rma (add rma (ext SI cdisp8))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"shcpa $crn,($rma+),$cdisp8a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x10) cdisp8a2 (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
(set rma (add rma (ext SI cdisp8a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lhcpa $crn,($rma+),$cdisp8a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x50) cdisp8a2 (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
(set rma (add rma (ext SI cdisp8a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
"swcpa $crn,($rma+),$cdisp8a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x20) cdisp8a4 (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (add rma (ext SI cdisp8a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
"lwcpa $crn,($rma+),$cdisp8a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x60) cdisp8a4 (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
(set rma (add rma (ext SI cdisp8a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
"smcpa $crn64,($rma+),$cdisp8a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x30) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcpa" (index-of rma) cdisp8a8 crn64 pc)
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
"lmcpa $crn64,($rma+),$cdisp8a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x70) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp8a8 pc))
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
; pmacros needed for coprocessor modulo addressing.
; Taken from supplement ``The operation of the modulo addressing'' in
; Toshiba documentation rev 2.2, p. 34.
(define-pmacro (compute-mask0)
(sequence SI ((SI temp))
(set temp (or mb0 me0))
(srl (const SI -1) (c-call SI "do_ldz" temp))))
(define-pmacro (mod0 immed)
(sequence SI ((SI modulo-mask))
(set modulo-mask (compute-mask0))
(if SI (eq (and rma modulo-mask) me0)
(or (and rma (inv modulo-mask)) mb0)
(add rma (ext SI immed)))))
(define-pmacro (compute-mask1)
(sequence SI ((SI temp))
(set temp (or mb1 me1))
(srl (const SI -1) (c-call SI "do_ldz" temp))))
(define-pmacro (mod1 immed)
(sequence SI ((SI modulo-mask))
(set modulo-mask (compute-mask1))
(if SI (eq (and rma modulo-mask) me1)
(or (and rma (inv modulo-mask)) mb1)
(add rma (ext SI immed)))))
(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
"sbcpm0 $crn,($rma+),$cdisp8"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x08) cdisp8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
(set rma (mod0 cdisp8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
"lbcpm0 $crn,($rma+),$cdisp8"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x48) cdisp8)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
(set rma (mod0 cdisp8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
"shcpm0 $crn,($rma+),$cdisp8a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x18) cdisp8a2 (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
(set rma (mod0 cdisp8a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
"lhcpm0 $crn,($rma+),$cdisp8a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x58) cdisp8a2 (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
(set rma (mod0 cdisp8a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
"swcpm0 $crn,($rma+),$cdisp8a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x28) cdisp8a4 (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (mod0 cdisp8a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
"lwcpm0 $crn,($rma+),$cdisp8a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x68) cdisp8a4 (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
(set rma (mod0 cdisp8a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"smcpm0 $crn64,($rma+),$cdisp8a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x38) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcp" rma crn64 pc)
(set rma (mod0 cdisp8a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"lmcpm0 $crn64,($rma+),$cdisp8a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x78) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
(set rma (mod0 cdisp8a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
"sbcpm1 $crn,($rma+),$cdisp8"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x0c) cdisp8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
(set rma (mod1 cdisp8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
"lbcpm1 $crn,($rma+),$cdisp8"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x4c) cdisp8)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
(set rma (mod1 cdisp8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
"shcpm1 $crn,($rma+),$cdisp8a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x1c) cdisp8a2 (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
(set rma (mod1 cdisp8a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
"lhcpm1 $crn,($rma+),$cdisp8a2"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x5c) cdisp8a2 (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
(set rma (mod1 cdisp8a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
"swcpm1 $crn,($rma+),$cdisp8a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x2c) cdisp8a4 (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
(set rma (mod1 cdisp8a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
"lwcpm1 $crn,($rma+),$cdisp8a4"
(+ MAJ_15 crn rma (f-sub4 5) (f-ext #x6c) cdisp8a4 (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem SI (and rma (inv SI 3)))))
(set rma (mod1 cdisp8a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"smcpm1 $crn64,($rma+),$cdisp8a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x3c) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call "do_smcp" rma crn64 pc)
(c-call VOID "check_write_to_text" rma)
(set rma (mod1 cdisp8a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
"lmcpm1 $crn64,($rma+),$cdisp8a8"
(+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x7c) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
(set rma (mod1 cdisp8a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnop cp_flag "branch condition register" (all-mep-isas) h-ccr 1)
(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE)
"bcpeq $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (eq (xor cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE)
"bcpne $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (ne (xor cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE)
"bcpat $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (ne (and cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE)
"bcpaf $cccc,$pcrel17a2"
(+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2)
(sequence ()
(c-call "check_option_cp" pc)
(if (eq (and cccc cp_flag) 0)
(set-vliw-alignment-modified pc pcrel17a2)))
())
(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN)
"synccp"
(+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1))
(sequence ()
(c-call "check_option_cp" pc)
(unimp "synccp"))
())
(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN)
"jsrv $rm"
(+ MAJ_1 (f-rn 8) rm (f-sub4 15))
(sequence ()
(cg-profile pc rm)
(c-call "check_option_cp" pc)
(core-vliw-switch
;; in core operating mode
(sequence ()
(set lp (or (add pc 2) 1))
(set-vliw-aliignment-modified-by-option pc rm)
(set-psw.om 1)) ;; to VLIW operation mode
;; in VLIW32 operating mode
(sequence ()
(set lp (or (add pc 4) 1))
(set pc (and rm (inv 1)))
(set-psw.om 0)) ;; to core operation mode
;; in VLIW64 operating mode
(sequence ()
(set lp (or (add pc 8) 1))
(set pc (and rm (inv 1)))
(set-psw.om 0)))) ;; to core operation mode
((mep (unit u-use-gpr (in usereg rm))
(unit u-exec)
(unit u-branch))))
(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN)
"bsrv $pcrel24a2"
(+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2)
(sequence ()
(cg-profile pc pcrel24a2)
(c-call "check_option_cp" pc)
(core-vliw-switch
;; in core operating mode
(sequence ()
(set lp (or (add pc 4) 1))
(set-vliw-aliignment-modified-by-option pc pcrel24a2)
(set-psw.om 1)) ;; to VLIW operation mode
;; in VLIW32 operating mode
(sequence ()
(set lp (or (add pc 4) 1))
(set pc (and pcrel24a2 (inv 1)))
(set-psw.om 0)) ;; to core operation mode
;; in VLIW64 operating mode
(sequence ()
(set lp (or (add pc 8) 1))
(set pc (and pcrel24a2 (inv 1)))
(set-psw.om 0)))) ;; to core operation mode
((mep (unit u-exec)
(unit u-branch))))
; An instruction for test instrumentation.
; Using a reserved opcode.
(dnci sim-syscall "simulator system call" ()
"--unused--"
(+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0))
(c-call "do_syscall" pc callnum)
())
(define-pmacro (dnri n major minor)
(dnci (.sym ri- n) "reserved instruction" ()
"--reserved--"
(+ major rn rm (f-sub4 minor))
(set pc (c-call USI "ri_exception" pc))
((mep (unit u-exec)
(unit u-branch)))))
(dnri 0 MAJ_0 6)
(dnri 1 MAJ_1 10)
(dnri 2 MAJ_1 11)
(dnri 3 MAJ_2 5)
(dnri 4 MAJ_2 8)
(dnri 5 MAJ_2 9)
(dnri 6 MAJ_2 10)
(dnri 7 MAJ_2 11)
(dnri 8 MAJ_3 4)
(dnri 9 MAJ_3 5)
(dnri 10 MAJ_3 6)
(dnri 11 MAJ_3 7)
(dnri 12 MAJ_3 12)
(dnri 13 MAJ_3 13)
(dnri 14 MAJ_3 14)
(dnri 15 MAJ_3 15)
(dnri 17 MAJ_7 7)
(dnri 20 MAJ_7 14)
(dnri 21 MAJ_7 15)
(dnri 22 MAJ_12 7)
(dnri 23 MAJ_14 13)
(dnri 24 MAJ_15 3)
(dnri 25 MAJ_15 6)
(dnri 26 MAJ_15 8)
; begin non-mep-h1 reserved insns
(dnri 16 MAJ_7 5)
(dnri 18 MAJ_7 12)
(dnri 19 MAJ_7 13)
; end non-mep-h1 reserved insns
; Macro instructions.
(dnmi nop "nop"
()
"nop"
(emit mov (rn 0) (rm 0)))
; Emit the 16 bit form of these 32 bit insns when the displacement is zero.
;
(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS)
"sb $rnc,$zero($rma)"
(emit sb rnc rma))
(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS)
"sh $rns,$zero($rma)"
(emit sh rns rma))
(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS)
"sw $rnl,$zero($rma)"
(emit sw rnl rma))
(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS)
"lb $rnc,$zero($rma)"
(emit lb rnc rma))
(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS)
"lh $rns,$zero($rma)"
(emit lh rns rma))
(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS)
"lw $rnl,$zero($rma)"
(emit lw rnl rma))
(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS)
"lbu $rnuc,$zero($rma)"
(emit lbu rnuc rma))
(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS)
"lhu $rnus,$zero($rma)"
(emit lhu rnus rma))
(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
"swcp $crn,$zero($rma)"
(emit swcp crn rma))
(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
"lwcp $crn,$zero($rma)"
(emit lwcp crn rma))
(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
"smcp $crn64,$zero($rma)"
(emit smcp crn64 rma))
(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
"lmcp $crn64,$zero($rma)"
(emit lmcp crn64 rma))
; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
; Copyright (C) 2001 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
; This file serves as a wrapper to bring in the core description plus
; sample implementations of the UCI and DSP instructions.
(include "mep-core.cpu")
(include "mep-ext-cop.cpu")
; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
; Copyright (C) 2003 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
;; begin-user-isa-includes
(include "mep-fmax.cpu")
;; end-user-isa-includes
; Toshiba MeP FMAX Coprocessor description. -*- Scheme -*-
; Copyright (C) 2005 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
;------------------------------------------------------------------------------
; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
; specified below for each ME_MODULE using this coprocessor.
; This coprocessor requires only the 32 bit insns in the core.
;------------------------------------------------------------------------------
; begin-isas
(define-pmacro fmax-core-isa () (ISA ext_core2))
(define-pmacro all-fmax-isas () (ISA ext_core2))
; end-isas
;******************************************************************************
; ifields
;------------------------------------------------------------------------------
; opcodes
(dnf f-fmax-0-4 "opcode" (all-fmax-isas) 0 4)
(dnf f-fmax-4-4 "opcode" (all-fmax-isas) 4 4)
(dnf f-fmax-8-4 "opcode" (all-fmax-isas) 8 4)
(dnf f-fmax-12-4 "opcode" (all-fmax-isas) 12 4)
(dnf f-fmax-16-4 "opcode" (all-fmax-isas) 16 4)
(dnf f-fmax-20-4 "opcode" (all-fmax-isas) 20 4)
(dnf f-fmax-24-4 "opcode" (all-fmax-isas) 24 4)
(dnf f-fmax-28-1 "opcode" (all-fmax-isas) 28 1)
(dnf f-fmax-29-1 "opcode" (all-fmax-isas) 29 1)
(dnf f-fmax-30-1 "opcode" (all-fmax-isas) 30 1)
(dnf f-fmax-31-1 "opcode" (all-fmax-isas) 31 1)
;------------------------------------------------------------------------------
; FR registers
(define-multi-ifield
(name f-fmax-frd)
(comment "FRd register")
(attrs all-fmax-isas)
(mode UINT)
(subfields f-fmax-28-1 f-fmax-4-4)
(insert (sequence ()
(set (ifield f-fmax-4-4) (and (ifield f-fmax-frd) #xf))
(set (ifield f-fmax-28-1) (srl (ifield f-fmax-frd) 4))))
(extract (set (ifield f-fmax-frd)
(or (sll (ifield f-fmax-28-1) 4) (ifield f-fmax-4-4))))
)
(define-multi-ifield
(name f-fmax-frn)
(comment "FRn register")
(attrs all-fmax-isas)
(mode UINT)
(subfields f-fmax-29-1 f-fmax-20-4)
(insert (sequence ()
(set (ifield f-fmax-20-4) (and (ifield f-fmax-frn) #xf))
(set (ifield f-fmax-29-1) (srl (ifield f-fmax-frn) 4))))
(extract (set (ifield f-fmax-frn)
(or (sll (ifield f-fmax-29-1) 4) (ifield f-fmax-20-4))))
)
(define-multi-ifield
(name f-fmax-frm)
(comment "FRm register")
(attrs all-fmax-isas)
(mode UINT)
(subfields f-fmax-30-1 f-fmax-24-4)
(insert (sequence ()
(set (ifield f-fmax-24-4) (and (ifield f-fmax-frm) #xf))
(set (ifield f-fmax-30-1) (srl (ifield f-fmax-frm) 4))))
(extract (set (ifield f-fmax-frm)
(or (sll (ifield f-fmax-30-1) 4) (ifield f-fmax-24-4))))
)
;------------------------------------------------------------------------------
; Core General registers
(dnf f-fmax-rm "opcode" (all-fmax-isas) 8 4)
;------------------------------------------------------------------------------
; Condition opcodes enum
(define-normal-insn-enum fmax-cond "condition opcode enum" (all-fmax-isas) FMAX_ f-fmax-8-4
("f" "u" "e" "ue" "l" "ul" "le" "ule"
"fi" "ui" "ei" "uei" "li" "uli" "lei" "ulei")
)
;******************************************************************************
; Hardware
;------------------------------------------------------------------------------
; FR registers
; Given a coprocessor register number N, expand to a
; name/index pair: ($frN N)
(define-pmacro (-fmax-fr-reg-pair n) ((.sym "fr" n) n))
(define-pmacro (-fmax-cr-reg-pair n) ((.sym "c" n) n))
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-cr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
(name h-cr-fmax)
(comment "Floating point registers")
(attrs all-fmax-isas VIRTUAL IS_FLOAT)
(type register SF (32))
(indices keyword "$"
(.splice (.unsplice (.map -fmax-fr-reg-pair (.iota 32)))
(.unsplice (.map -fmax-cr-reg-pair (.iota 32))))
)
(get (index) (c-call SF "fmax_fr_get_handler" index))
(set (index newval) (c-call VOID "fmax_fr_set_handler" index newval))
)
;------------------------------------------------------------------------------
; Control registers
; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
; GDB will use the hardware table generated from this declaration. The operands use h-ccr
; from mep-core.cpu so that SID's semantic trace will be consistent between
; the core and the coprocessor but use parse/print handlers which reference the hardware table
; generated from this declarations
(define-hardware
(name h-ccr-fmax)
(comment "Coprocessor Identifier and Revision Register")
(attrs all-fmax-isas VIRTUAL)
(type register USI (16))
(indices keyword "$" (
("cirr" 0) ("fcr0" 0) ("ccr0" 0)
("cbcr" 1) ("fcr1" 1) ("ccr1" 1)
("cerr" 15) ("fcr15" 15) ("ccr15" 15)
)
)
(set (index newval) (c-call VOID "h_ccr_set" index newval))
(get (index) (c-call SI "h_ccr_get" index))
)
;------------------------------------------------------------------------------
; Misc
(define-hardware
(name h-fmax-compare-i-p)
(comment "flag")
(attrs all-fmax-isas)
(type register USI)
)
;******************************************************************************
; Operands
;------------------------------------------------------------------------------
; FR Registers
(define-full-operand fmax-FRd "FRd" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
(define-full-operand fmax-FRn "FRn" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
(define-full-operand fmax-FRm "FRm" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frm ((parse "fmax_cr") (print "fmax_cr")) () ())
(define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
(define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
;------------------------------------------------------------------------------
; Control registers
(define-full-operand fmax-CCRn "CCRn" (all-fmax-isas (CDATA REGNUM)) h-ccr DFLT f-fmax-4-4 ((parse "fmax_ccr") (print "fmax_ccr")) () ())
(dnop fmax-CIRR "CIRR" (all-fmax-isas SEM-ONLY) h-ccr 0)
(dnop fmax-CBCR "CBCR" (all-fmax-isas SEM-ONLY) h-ccr 1)
(dnop fmax-CERR "CERR" (all-fmax-isas SEM-ONLY) h-ccr 15)
;------------------------------------------------------------------------------
; Core General Registers
(dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
;------------------------------------------------------------------------------
; misc
(dnop fmax-Compare-i-p "flag" (all-fmax-isas SEM-ONLY) h-fmax-compare-i-p f-nil)
;******************************************************************************
; Instructions
;------------------------------------------------------------------------------
; Binary Arithmetic
(define-pmacro (fmax-binary-arith op opc sem)
(dni op
(.str op " FRd,FRn,FRm")
(all-fmax-isas MAY_TRAP)
(.str op " ${fmax-FRd},${fmax-FRn},${fmax-FRm}")
(+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) (f-fmax-16-4 0)
fmax-FRn fmax-FRm (f-fmax-31-1 0))
sem
()
)
)
(fmax-binary-arith fadds #x0 (set fmax-FRd (add fmax-FRn fmax-FRm)))
(fmax-binary-arith fsubs #x1 (set fmax-FRd (sub fmax-FRn fmax-FRm)))
(fmax-binary-arith fmuls #x2 (set fmax-FRd (mul fmax-FRn fmax-FRm)))
(fmax-binary-arith fdivs #x3 (set fmax-FRd (div fmax-FRn fmax-FRm)))
;------------------------------------------------------------------------------
; Unary Arithmetic
(define-pmacro (fmax-unary-arith op opc sem)
(dni op
(.str op " FRd,FRn")
(all-fmax-isas MAY_TRAP)
(.str op " ${fmax-FRd},${fmax-FRn}")
(+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7)
(f-fmax-16-4 0) fmax-FRn (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
sem
()
)
)
(fmax-unary-arith fsqrts #x4 (set fmax-FRd (sqrt fmax-FRn)))
(fmax-unary-arith fabss #x5 (set fmax-FRd (abs fmax-FRn)))
(fmax-unary-arith fnegs #x7 (set fmax-FRd (neg fmax-FRn)))
(fmax-unary-arith fmovs #x6 (set fmax-FRd fmax-FRn))
;------------------------------------------------------------------------------
; Conversions
(define-pmacro (fmax-conv op opc1 opc2 opnd1 opnd2 sem)
(dni op
(.str op " FRd,FRn")
(all-fmax-isas MAY_TRAP)
(.str op " ${" opnd1 "},${" opnd2 "}")
(+ (f-fmax-0-4 #xF) opnd1 (f-fmax-8-4 opc1) (f-fmax-12-4 #x7)
(f-fmax-16-4 opc2) opnd2 (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
sem
()
)
)
(fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_froundws" fmax-FRn)))
(fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ftruncws" fmax-FRn)))
(fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn)))
(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn)))
(fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn)))
(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF fmax-FRn-int)))
;------------------------------------------------------------------------------
; Comparisons
;
; Comparison with no exceptions
(define-pmacro (fmax-f-sem x y) (andif (gt x y) (lt x y))) ; do this to get exception detection
(define-pmacro (fmax-u-sem x y) (not (orif (lt x y) (orif (eq x y) (gt x y)))))
(define-pmacro (fmax-e-sem x y) (eq x y))
(define-pmacro (fmax-ue-sem x y) (not (orif (lt x y) (gt x y))))
(define-pmacro (fmax-l-sem x y) (lt x y))
(define-pmacro (fmax-ul-sem x y) (not (orif (gt x y) (eq x y))))
(define-pmacro (fmax-le-sem x y) (orif (lt x y) (eq x y)))
(define-pmacro (fmax-ule-sem x y) (not (gt x y)))
(define-pmacro (fmax-comp cond suffix exceptions)
(dni (.sym fcmp cond suffix s)
(.str "fcmp" cond suffix "s FRn,FRm")
;; Even though the instruction doesn't really trap if EXCEPTIONS
;; is zero, we don't want gcc to put it in a repeat or erepeat
;; block because of the hazards between fcmp instructions and
;; anything that reads CBCR.
(all-fmax-isas MAY_TRAP)
(.str "fcmp" cond suffix "s ${fmax-FRn},${fmax-FRm}")
(+ (f-fmax-0-4 #xF) (f-fmax-4-4 0) (.sym FMAX_ cond suffix) (f-fmax-12-4 #x7)
(f-fmax-16-4 #x2) (f-fmax-28-1 0) fmax-FRn fmax-FRm (f-fmax-31-1 0))
(sequence ()
(set fmax-Compare-i-p exceptions)
(set fmax-CBCR ((.sym fmax- cond -sem) fmax-FRn fmax-FRm))
(set fmax-Compare-i-p 0)
)
()
)
)
; Comparison with no exceptions
(fmax-comp f "" 0)
(fmax-comp u "" 0)
(fmax-comp e "" 0)
(fmax-comp ue "" 0)
(fmax-comp l "" 0)
(fmax-comp ul "" 0)
(fmax-comp le "" 0)
(fmax-comp ule "" 0)
; Comparison with exceptions
(fmax-comp f i 1)
(fmax-comp u i 1)
(fmax-comp e i 1)
(fmax-comp ue i 1)
(fmax-comp l i 1)
(fmax-comp ul i 1)
(fmax-comp le i 1)
(fmax-comp ule i 1)
;------------------------------------------------------------------------------
; Move to/from core registers
(dni cmov-frn-rm
"cmov FRn,Rm"
(all-fmax-isas (INTRINSIC "cmov1"))
"cmov ${fmax-FRd-int},${fmax-Rm}"
(+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
(f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
(set fmax-FRd-int fmax-Rm)
()
)
(dni cmov-rm-frn
"cmov Rm,FRn"
(all-fmax-isas (INTRINSIC "cmov2"))
"cmov ${fmax-Rm},${fmax-FRd-int}"
(+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
(f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 1))
(set fmax-Rm fmax-FRd-int)
()
)
(dni cmovc-ccrn-rm
"cmovc CCRn,Rm"
(all-fmax-isas (INTRINSIC "cmovc1"))
"cmovc ${fmax-CCRn},${fmax-Rm}"
(+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
(f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 0))
(set fmax-CCRn fmax-Rm)
()
)
(dni cmovc-rm-ccrn
"cmovc Rm,CCRn"
(all-fmax-isas (INTRINSIC "cmovc2"))
"cmovc ${fmax-Rm},${fmax-CCRn}"
(+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
(f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 1))
(set fmax-Rm fmax-CCRn)
()
)
; Insns introduced for the MeP-h1 core
;
(dnci stcb_r "store in control bus space" (VOLATILE (MACH h1))
"stcb $rn,($rma)"
(+ MAJ_7 rn rma (f-sub4 12))
(c-call VOID "do_stcb" rn (and rma #xffff))
((mep (unit u-use-gpr (in usereg rn))
(unit u-use-gpr (in usereg rma))
(unit u-exec)
(unit u-stcb))))
(dnci ldcb_r "load from control bus space" (VOLATILE (MACH h1) (LATENCY 3))
"ldcb $rn,($rma)"
(+ MAJ_7 rn rma (f-sub4 13))
(set rn (c-call SI "do_ldcb" (and rma #xffff)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-ldcb)
(unit u-exec)
(unit u-ldcb-gpr (out loadreg rn)))))
(dnci pref "cache prefetch" ((MACH h1) VOLATILE)
"pref $cimm4,($rma)"
(+ MAJ_7 cimm4 rma (f-sub4 5))
(sequence ()
(c-call VOID "check_option_dcache" pc)
(c-call VOID "do_cache_prefetch" cimm4 rma pc))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
;; This coprocessor definition is being used to verify vliw mode behaviour.
;; This is a mock-up done by Red Hat and is in no way supposed to represent
;; a real coprocessor. The hardware is defined in mep-core.cpu.
; Coprocessor registers
(define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
(define-hardware
(name h-cr64-rh-1)
(comment "64-bit coprocessor registers for rh coprocessor for core 1")
(attrs VIRTUAL rh-isa-1)
(type register DI (32))
(set (index newval) (c-call VOID "h_cr64_set" index newval))
(get (index) (c-call DI "h_cr64_get" index))
(indices keyword "$c" (.map -reg-pair (.iota 32)))
)
(define-hardware
(name h-cr-rh-1)
(comment "32-bit coprocessor registers for rh coprocessor for core 1")
(attrs VIRTUAL rh-isa-1)
(type register SI (32))
(set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
(get (index) (trunc SI (c-call DI "h_cr64_get" index)))
(indices keyword "$c" (.map -reg-pair (.iota 32)))
)
(define-hardware
(name h-ccr-rh-1)
(comment "Coprocessor control registers for rh coprocessor for core 1")
(attrs VIRTUAL rh-isa-1)
(type register SI (64))
(set (index newval) (c-call VOID "h_ccr_set" index newval))
(get (index) (c-call DI "h_ccr_get" index))
(indices keyword "" (.map -ccr-reg-pair (.iota 64)))
)
; ifields For 16-bit insns
(dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4)
(dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5)
(dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5)
(dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2)
(dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3)
(dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4)
; ifields For 32-bit insns (some of the above are used too)
; Notes:
;
; f-alone: A value of 0111 means that the insn can run alone in
; one of the vliw modes.
;
; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit
; f-seg32-a: insns to be defined.
(dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3)
(dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4)
(dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3)
(dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8)
(dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5)
; ifields for 48-bit insns
; Note: Part of f-uu12 can be broken off later to enumerate
; any 48-bit insns that may be added.
(dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12)
(dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16)
(dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16)
; ifields for 64-bit insns
(dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8)
(dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8)
(dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8)
(dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16)
(dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5)
(dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4)
(dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23)
(dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4)
(dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4)
(dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24)
; Operands for 16-bit insns
(dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn)
(dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm)
(dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm)
; Additional operands for 32-bit insns
(dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8)
; Operands for 48-bit insns
(dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a)
(dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b)
; Additional operands for 64-bit insns
(dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c)
(dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64)
(dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64)
(dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64)
(dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64)
(dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23)
(dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24)
; 16- and 32-bit nops can be defined as normal instructions without
; any problems. nops take no operands, so nops longer than 32
; bits cannot be defined as normal insns since that would result in
; decodable bits beyond cgen's 32-bit boundary. As a result, we
; have to use macros and other real insns to create 48- and 64-bit nops.
;
; In addition, since the names of the nops that will be created as part
; of future insn sets are not known at this time, the assembler needs a
; fixed set of nop names that it can use for automatic nop insertion.
; The idea is that no matter what those insns are called, we don't want
; to have to change the C code in the assemblers vliw grouping validation
; and nop insertion routines. We therefore have to create macros for
; all nops to map the macro names which are known to the assembler to the
; names of the real nop insns.
;
; These emitted insns in these macros will need to be modified when
; new nops are defined in new coprocessor insn sets.
; A real 16-bit nop insn exists
(dnmi cpnop16 "cpnop16"
((ISA ext_cop1_16))
"cpnop16"
(emit cp16nop)
)
; A real 32-bit nop insn exists
(dnmi cpnop32 "cpnop32"
((ISA ext_cop1_32))
"cpnop32"
(emit cp32nop)
)
; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop.
(dnmi cpnop48 "cpnop48"
((ISA ext_cop1_48))
"cpnop48"
(emit cpf1nop (code16a 0) (code16b 0))
)
; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop.
(dnmi cpnop64 "cpnop64"
((ISA ext_cop1_64))
"cpnop64"
(emit cpf3nop (code16b 0) (code16c 0))
)
(define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16))
(define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32))
(define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48))
(define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64))
; 16-Bit Insns
(dncp116i movcp16 "16-bit coprocessor move insn"
(VLIW64_NO_MATCHING_NOP)
"movcp16 $cpcrn,$cpcrm"
(+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm)
(set cpcrn cpcrm)
()
)
(dncp116i movcp16a "16-bit coprocessor move insn"
(VLIW64_NO_MATCHING_NOP)
"movcp16a $cpcrn,$cprm"
(+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm)
(set cpcrn (zext DI cprm))
()
)
(dncp116i movcp16b "16-bit coprocessor move insn"
(VLIW64_NO_MATCHING_NOP)
"movcp16b $cprm,$cpcrn"
(+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm)
(set cprm (subword SI cpcrn 1))
()
)
(dncp116i cp16nop "16-bit coprocessor nop"
(VLIW64_NO_MATCHING_NOP)
"cp16nop"
(+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0))
(unimp "cp16nop")
()
)
; 32-Bit Insns
(dncp132i cp32nop "32-bit coprocessor nop"
(VLIW64_NO_MATCHING_NOP)
"cp32nop"
(+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
(f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0))
(unimp "cpnop32")
()
)
(dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests "
(VLIW64_NO_MATCHING_NOP)
"cpf2 $code8"
(+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
(f-cpcrm-32 0) (f-seg32-a 1) code8)
(unimp "cpf2")
()
)
; 48-Bit Insns
(dncp148i cpf1 "48-bit coprocessor helper insn"
()
"cpf1 $code16a,$code16b"
(+ (f-cphigh4 4) (f-uu12 0) code16a code16b)
(sequence ((HI result))
(if (eq code16a 0)
(set pc (c-call USI "cop_exception" pc))
; Set branch condition flags to value of code16a[0:3]
; Branch condition flags do not exist yet.
(nop)
)
)
()
)
(dncp148i cpf1nop "48-bit coprocessor nop insn"
()
"cpf1nop $code16a,$code16b"
(+ (f-cphigh4 5) (f-uu12 0) code16a code16b)
(sequence ((HI result))
(set result (add code16a code16b))
)
()
)
; 64-Bit Insns
(dncp164i cpf3 "64-bit coprocessor helper insn"
()
"cpf3 $code16b,$code16c"
(+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 0) code16b code16c)
(sequence ((HI result))
(set result (add code16b code16c))
)
()
)
(dncp164i cpf3nop "64-bit coprocessor helper insn"
()
"cpf3nop $code16b,$code16c"
(+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 7) code16b code16c)
(sequence ((HI result))
(set result (add code16b code16c))
)
()
)
(dncp164i cmov64a "64-bit cmov"
()
"cmov64a $cpcrn64,$cpcrm64,$cpcode23"
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 1) cpcrn64 cpcrm64 cpcode23)
(sequence ((SI dummy))
(set dummy cpcode23)
(set cpcrn64 (zext DI cpcrm64)))
()
)
(dncp164i cmov64b "64-bit cmov"
()
"cmov64b $cpcrm64,$cpcrn64,$cpcode23"
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 2) cpcrn64 cpcrm64 cpcode23)
(sequence ((SI dummy))
(set dummy cpcode23)
(set cpcrm64 (subword SI cpcrn64 1)))
()
)
(dncp164i cmovh64a "64-bit cmovh"
()
"cmovh64a $cpcrn64,$cpcrm64,$cpcode23"
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 3) cpcrn64 cpcrm64 cpcode23)
(sequence ((SI dummy))
(set dummy cpcode23)
(set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1)))))
()
)
(dncp164i cmovh64b "64-bit cmovh"
()
"cmovh64b $cpcrm64,$cpcrn64,$cpcode23"
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 4) cpcrn64 cpcrm64 cpcode23)
(sequence ((SI dummy))
(set dummy cpcode23)
(set cpcrm64 (subword SI cpcrn64 0)))
()
)
(dncp164i cmovc64a "64-bit cmovc"
()
"cmovc64a $cpccrn64,$cpccrm64,$cpcode24"
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 5) cpccrn64 cpccrm64 cpcode24)
(sequence ((SI dummy))
(set dummy cpcode24)
(set cpccrn64 cpccrm64))
()
)
(dncp164i cmovc64b "64-bit cmovc"
()
"cmovc64b $cpccrm64,$cpccrn64,$cpcode24"
(+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
(f-seg64 6) cpccrn64 cpccrm64 cpcode24)
(sequence ((SI dummy))
(set dummy cpcode24)
(set cpccrm64 cpccrn64))
()
)
; Toshiba MeP Media Engine architecture description. -*- Scheme -*-
; Copyright (C) 2001, 2002 Red Hat, Inc.
; This file is part of CGEN.
; See file COPYING.CGEN for details.
; This file provides sample definitions for the UCI and DSP
; instructions. It is incorporated into the overall description by
; including it from a top-level file that includes all of the required
; option files.
; UCI option.
(define-pmacro mep-ext1-isa () (ISA ext_core1))
; uci instructions for ELFextension test
; uci.elfext.1 $simm16
; 1111_IIII_0000_0010 0001_iiii_iiii_iiii
; simm16 = I[4:7]||i[20:31]
; uci.elfext.2 $uimm16
; 1111_IIII_0000_0010 0010_iiii_iiii_iiii
; uimm16 = I[4:7]||i[20:31]
; define simm16
(df f-uci_elfext_1-hi "uci_elfext_1 simm16 hi 4s7" (mep-ext1-isa) 4 4 INT #f #f)
(df f-uci_elfext_1-lo "uci_elfext_1 simm16 lo 20s31" (mep-ext1-isa) 20 12 UINT #f #f)
(define-multi-ifield
(name f-uci_elfext_1)
(comment "16-bits uci_elfext_ signed constant")
(attrs mep-ext1-isa)
(mode INT)
(subfields f-uci_elfext_1-hi f-uci_elfext_1-lo)
(insert (sequence ()
(set (ifield f-uci_elfext_1-hi) (srl (ifield f-uci_elfext_1) 12))
(set (ifield f-uci_elfext_1-lo) (and (ifield f-uci_elfext_1) #xfff))))
(extract (set (ifield f-uci_elfext_1)
(or (sll (ifield f-uci_elfext_1-hi) 12)
(ifield f-uci_elfext_1-lo))))
)
(dpop uci_elfext_1simm16 "signed imm (16 bits)" (mep-ext1-isa) h-sint f-uci_elfext_1 "signed16")
; define uimm16
(df f-uci_elfext_2-hi "uci_elfext_2 uimm16 hi 4u7" (mep-ext1-isa) 4 4 UINT #f #f)
(df f-uci_elfext_2-lo "uci_elfext_2 uimm16 lo 20u31" (mep-ext1-isa) 20 12 UINT #f #f)
(define-multi-ifield
(name f-uci_elfext_2)
(comment "16-bits uci_elfext_ unsigned constant")
(attrs mep-ext1-isa)
(mode UINT)
(subfields f-uci_elfext_2-hi f-uci_elfext_2-lo)
(insert (sequence ()
(set (ifield f-uci_elfext_2-hi) (srl (ifield f-uci_elfext_2) 12))
(set (ifield f-uci_elfext_2-lo) (and (ifield f-uci_elfext_2) #xfff))))
(extract (set (ifield f-uci_elfext_2)
(or (sll (ifield f-uci_elfext_2-hi) 12)
(ifield f-uci_elfext_2-lo))))
)
(dpop uci_elfext_2uimm16 "unsigned imm (16 bits)" (mep-ext1-isa) h-uint f-uci_elfext_2 "unsigned16")
; define sub-opcode
(df f-uci_elfext-sub "sub-opcode for uci_elfext instructions" (mep-ext1-isa) 16 4 UINT #f #f)
; define instruction
(dni uci.elfext.1 "uci_elfext instruction 1" (OPTIONAL_UCI_INSN VOLATILE mep-ext1-isa)
"uci.elfext.1 $uci_elfext_1simm16"
(+ MAJ_15 (f-rm 0) (f-sub4 2) (f-uci_elfext-sub 1) uci_elfext_1simm16)
(c-call "check_option_uci" pc)
()
)
; define instruction
(dni uci.elfext.2 "uci_elfext instruction 1" (OPTIONAL_UCI_INSN VOLATILE mep-ext1-isa)
"uci.elfext.2 $uci_elfext_2uimm16"
(+ MAJ_15 (f-rm 0) (f-sub4 2) (f-uci_elfext-sub 2) uci_elfext_2uimm16)
(c-call "check_option_uci" pc)
()
)
;; some general samples
; UCI option.
(dni uci "user defined instruction" (OPTIONAL_UCI_INSN mep-ext1-isa)
"uci $rn,$rm,$code16"
(+ MAJ_15 rn rm (f-sub4 2) code16)
(sequence ()
(c-call "check_option_uci" pc)
(unimp "uci"))
())
; DSP option.
(dni dsp "dsp instruction" (OPTIONAL_DSP_INSN mep-ext1-isa)
"dsp $rn,$rm,$code16"
(+ MAJ_15 rn rm (f-sub4 0) code16)
(sequence ()
(c-call "check_option_dsp" pc)
(set pc (c-call USI "dsp_exception" pc)))
())
(include "mep-default.cpu")
/* MeP opcode support. -*- C -*-
Copyright (C) 2001, 2002, 2003, 2004, 2005 Red Hat, Inc.
This file is part of CGEN.
This file is copyrighted with the GNU General Public License.
See file COPYING for details. */
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 1
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, insn) 0
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
typedef struct
{
char * name;
int config_enum;
unsigned cpu_flag;
int big_endian;
int vliw_bits;
CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa;
CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa;
CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa;
CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa;
CGEN_ATTR_VALUE_BITSET_TYPE cop_isa;
CGEN_ATTR_VALUE_BITSET_TYPE core_isa;
unsigned int option_mask;
} mep_config_map_struct;
extern mep_config_map_struct mep_config_map[];
extern int mep_config_index;
extern void init_mep_all_core_isas_mask (void);
extern void init_mep_all_cop_isas_mask (void);
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void);
#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum)
#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag)
#define MEP_OMASK (mep_config_map[mep_config_index].option_mask)
#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0)
#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32)
#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64)
#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa)
#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa)
#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa)
#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa)
#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa)
#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa)
extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *);
/* A mask for all ISAs executed by the core. */
#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask;
#define MEP_INSN_CORE_P(insn) ( \
init_mep_all_core_isas_mask (), \
mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \
)
/* A mask for all ISAs executed by a VLIW coprocessor. */
#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask;
#define MEP_INSN_COP_P(insn) ( \
init_mep_all_cop_isas_mask (), \
mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \
)
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
#define CGEN_VALIDATE_INSN_SUPPORTED
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *);
const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *);
static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *);
static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *);
static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long);
static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *);
static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *);
const char *
parse_csrn (CGEN_CPU_DESC cd, const char **strp,
CGEN_KEYWORD *keyword_table, long *field)
{
const char *err;
unsigned long value;
err = cgen_parse_keyword (cd, strp, keyword_table, field);
if (!err)
return NULL;
err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value);
if (err)
return err;
*field = value;
return NULL;
}
/* begin-cop-ip-parse-handlers */
static const char *
parse_fmax_cr (CGEN_CPU_DESC cd,
const char **strp,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long *field)
{
return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_fmax, field);
}
static const char *
parse_fmax_ccr (CGEN_CPU_DESC cd,
const char **strp,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long *field)
{
return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_fmax, field);
}
/* end-cop-ip-parse-handlers */
const char *
parse_tpreg (CGEN_CPU_DESC cd, const char ** strp,
CGEN_KEYWORD *keyword_table, long *field)
{
const char *err;
err = cgen_parse_keyword (cd, strp, keyword_table, field);
if (err)
return err;
if (*field != 13)
return _("Only $tp or $13 allowed for this opcode");
return NULL;
}
const char *
parse_spreg (CGEN_CPU_DESC cd, const char ** strp,
CGEN_KEYWORD *keyword_table, long *field)
{
const char *err;
err = cgen_parse_keyword (cd, strp, keyword_table, field);
if (err)
return err;
if (*field != 15)
return _("Only $sp or $15 allowed for this opcode");
return NULL;
}
const char *
parse_mep_align (CGEN_CPU_DESC cd, const char ** strp,
enum cgen_operand_type type, long *field)
{
long lsbs = 0;
const char *err;
switch (type)
{
case MEP_OPERAND_PCREL8A2:
case MEP_OPERAND_PCREL12A2:
case MEP_OPERAND_PCREL17A2:
case MEP_OPERAND_PCREL24A2:
case MEP_OPERAND_CDISP8A2:
case MEP_OPERAND_CDISP8A4:
case MEP_OPERAND_CDISP8A8:
err = cgen_parse_signed_integer (cd, strp, type, field);
break;
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_UDISP7:
case MEP_OPERAND_UDISP7A2:
case MEP_OPERAND_UDISP7A4:
case MEP_OPERAND_UIMM7A4:
case MEP_OPERAND_ADDR24A4:
err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field);
break;
default:
abort();
}
if (err)
return err;
switch (type)
{
case MEP_OPERAND_UDISP7:
lsbs = 0;
break;
case MEP_OPERAND_PCREL8A2:
case MEP_OPERAND_PCREL12A2:
case MEP_OPERAND_PCREL17A2:
case MEP_OPERAND_PCREL24A2:
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_UDISP7A2:
case MEP_OPERAND_CDISP8A2:
lsbs = *field & 1;
break;
case MEP_OPERAND_UDISP7A4:
case MEP_OPERAND_UIMM7A4:
case MEP_OPERAND_ADDR24A4:
case MEP_OPERAND_CDISP8A4:
lsbs = *field & 3;
break;
case MEP_OPERAND_CDISP8A8:
lsbs = *field & 7;
break;
default:
/* Safe assumption? */
abort ();
}
if (lsbs)
return "Value is not aligned enough";
return NULL;
}
const char *
parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp,
enum cgen_operand_type type, unsigned long *field)
{
return parse_mep_align (cd, strp, type, (long *) field);
}
/* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed
constants in a signed context. */
static const char *
parse_signed16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
return parse_lo16 (cd, strp, opindex, valuep, 1);
}
static const char *
parse_lo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep,
long signedp)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16,
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
if (signedp)
*valuep = (long)(short) value;
else
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%hi(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S,
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = (value + 0x8000) >> 16;
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%uhi(", 5) == 0)
{
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U,
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value = value >> 16;
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%sdaoff(", 8) == 0)
{
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL,
NULL, & value);
if (**strp != ')')
return _("missing `)'");
++*strp;
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%tpoff(", 7) == 0)
{
*strp += 7;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL,
NULL, & value);
if (**strp != ')')
return _("missing `)'");
++*strp;
*valuep = value;
return errmsg;
}
if (**strp == '%')
return _("invalid %function() here");
return cgen_parse_signed_integer (cd, strp, opindex, valuep);
}
static const char *
parse_unsigned16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_lo16 (cd, strp, opindex, (long *) valuep, 0);
}
/* A special case of parse_signed16 which accepts only the value zero. */
static const char *
parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
/*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/
/* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'.
It will fail and cause ry to be listed as an undefined symbol in the
listing. */
if (strncmp (*strp, "($", 2) == 0)
return "not zero"; /* any string will do -- will never be seen. */
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0))
return "not zero"; /* any string will do -- will never be seen. */
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%hi(", 4) == 0)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0))
return "not zero"; /* any string will do -- will never be seen. */
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%uhi(", 5) == 0)
{
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0))
return "not zero"; /* any string will do -- will never be seen. */
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%sdaoff(", 8) == 0)
{
*strp += 8;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0))
return "not zero"; /* any string will do -- will never be seen. */
*valuep = value;
return errmsg;
}
if (strncasecmp (*strp, "%tpoff(", 7) == 0)
{
*strp += 7;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL,
&result_type, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
if (errmsg == NULL
&& (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0))
return "not zero"; /* any string will do -- will never be seen. */
*valuep = value;
return errmsg;
}
if (**strp == '%')
return "invalid %function() here";
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE,
&result_type, &value);
if (errmsg == NULL
&& (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0))
return "not zero"; /* any string will do -- will never be seen. */
return errmsg;
}
static const char *
parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp,
enum cgen_operand_type opindex, unsigned long *valuep)
{
const char *errmsg;
bfd_vma value;
/* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */
if (strncasecmp (*strp, "%tpoff(", 7) == 0)
{
int reloc;
*strp += 7;
switch (opindex)
{
case MEP_OPERAND_UDISP7:
reloc = BFD_RELOC_MEP_TPREL7;
break;
case MEP_OPERAND_UDISP7A2:
reloc = BFD_RELOC_MEP_TPREL7A2;
break;
case MEP_OPERAND_UDISP7A4:
reloc = BFD_RELOC_MEP_TPREL7A4;
break;
default:
/* Safe assumption? */
abort ();
}
errmsg = cgen_parse_address (cd, strp, opindex, reloc,
NULL, &value);
if (**strp != ')')
return "missing `)'";
++*strp;
*valuep = value;
return errmsg;
}
if (**strp == '%')
return _("invalid %function() here");
return parse_mep_alignu (cd, strp, opindex, valuep);
}
/* BEGIN LIGHTWEIGHT MACRO PROCESSOR. */
#define MAXARGS 9
typedef struct
{
char *name;
char *expansion;
} macro;
typedef struct
{
const char *start;
int len;
} arg;
macro macros[] =
{
{ "sizeof", "(`1.end + (- `1))"},
{ "startof", "(`1 | 0)" },
{ "align4", "(`1&(~3))"},
/*{ "hi", "(((`1+0x8000)>>16) & 0xffff)" }, */
/*{ "lo", "(`1 & 0xffff)" }, */
/*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */
/*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */
{ 0,0 }
};
static char * expand_string (const char *, int);
static const char *
mep_cgen_expand_macros_and_parse_operand
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
static char *
str_append (char *dest, const char *input, int len)
{
char *new_dest;
int oldlen;
if (len == 0)
return dest;
/* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */
oldlen = (dest ? strlen(dest) : 0);
new_dest = realloc (dest, oldlen + len + 1);
memset (new_dest + oldlen, 0, len + 1);
return strncat (new_dest, input, len);
}
static macro *
lookup_macro (const char *name)
{
macro *m;
for (m = macros; m->name; ++m)
if (strncmp (m->name, name, strlen(m->name)) == 0)
return m;
return 0;
}
static char *
expand_macro (arg *args, int narg, macro *mac)
{
char *result = 0, *rescanned_result = 0;
char *e = mac->expansion;
char *mark = e;
int arg = 0;
/* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */
while (*e)
{
if (*e == '`' &&
(*e+1) &&
((*(e + 1) - '1') <= MAXARGS) &&
((*(e + 1) - '1') <= narg))
{
result = str_append (result, mark, e - mark);
arg = (*(e + 1) - '1');
/* printf("replacing `%d with %s\n", arg+1, args[arg].start); */
result = str_append (result, args[arg].start, args[arg].len);
++e;
mark = e+1;
}
++e;
}
if (mark != e)
result = str_append (result, mark, e - mark);
if (result)
{
rescanned_result = expand_string (result, 0);
free (result);
return rescanned_result;
}
else
return result;
}
#define IN_TEXT 0
#define IN_ARGS 1
static char *
expand_string (const char *in, int first_only)
{
int num_expansions = 0;
int depth = 0;
int narg = -1;
arg args[MAXARGS];
int state = IN_TEXT;
const char *mark = in;
macro *macro = 0;
char *expansion = 0;
char *result = 0;
while (*in)
{
switch (state)
{
case IN_TEXT:
if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0))
{
macro = lookup_macro (in + 1);
if (macro)
{
/* printf("entering state %d at '%s'...\n", state, in); */
result = str_append (result, mark, in - mark);
mark = in;
in += 1 + strlen (macro->name);
while (*in == ' ') ++in;
if (*in != '(')
{
state = IN_TEXT;
macro = 0;
}
else
{
state = IN_ARGS;
narg = 0;
args[narg].start = in + 1;
args[narg].len = 0;
mark = in + 1;
}
}
}
break;
case IN_ARGS:
if (depth == 0)
{
switch (*in)
{
case ',':
narg++;
args[narg].start = (in + 1);
args[narg].len = 0;
break;
case ')':
state = IN_TEXT;
/* printf("entering state %d at '%s'...\n", state, in); */
if (macro)
{
expansion = 0;
expansion = expand_macro (args, narg, macro);
num_expansions++;
if (expansion)
{
result = str_append (result, expansion, strlen (expansion));
free (expansion);
}
}
else
{
result = str_append (result, mark, in - mark);
}
macro = 0;
mark = in + 1;
break;
case '(':
depth++;
default:
args[narg].len++;
break;
}
}
else
{
if (*in == ')')
depth--;
if (narg > -1)
args[narg].len++;
}
}
++in;
}
if (mark != in)
result = str_append (result, mark, in - mark);
return result;
}
#undef IN_ARGS
#undef IN_TEXT
#undef MAXARGS
/* END LIGHTWEIGHT MACRO PROCESSOR. */
const char * mep_cgen_parse_operand
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
const char *
mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex,
const char ** strp_in, CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
char *str = 0, *hold = 0;
const char **strp = 0;
/* Set up a new pointer to macro-expanded string. */
str = expand_string (*strp_in, 1);
/* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */
hold = str;
strp = (const char **)(&str);
errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields);
/* Now work out the advance. */
if (strlen (str) == 0)
*strp_in += strlen (*strp_in);
else
{
if (strstr (*strp_in, str))
/* A macro-expansion was pulled off the front. */
*strp_in = strstr (*strp_in, str);
else
/* A non-macro-expansion was pulled off the front. */
*strp_in += (str - hold);
}
if (hold)
free (hold);
return errmsg;
}
#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand);
/* -- dis.c */
#include "elf/mep.h"
#include "elf-bfd.h"
#define CGEN_VALIDATE_INSN_SUPPORTED
static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
static void
print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "$tp");
}
static void
print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "$sp");
}
/* begin-cop-ip-print-handlers */
static void
print_fmax_cr (CGEN_CPU_DESC cd,
void *dis_info,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long value,
unsigned int attrs)
{
print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_fmax, value, attrs);
}
static void
print_fmax_ccr (CGEN_CPU_DESC cd,
void *dis_info,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long value,
unsigned int attrs)
{
print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_fmax, value, attrs);
}
/* end-cop-ip-print-handlers */
/************************************************************\
*********************** Experimental *************************
\************************************************************/
#undef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN mep_print_insn
static int
mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
bfd_byte *buf, int corelength, int copro1length,
int copro2length ATTRIBUTE_UNUSED)
{
int i;
int status = 0;
/* char insnbuf[CGEN_MAX_INSN_SIZE]; */
bfd_byte insnbuf[64];
/* If corelength > 0 then there is a core insn present. It
will be at the beginning of the buffer. After printing
the core insn, we need to print the + on the next line. */
if (corelength > 0)
{
int my_status = 0;
for (i = 0; i < corelength; i++ )
insnbuf[i] = buf[i];
cd->isas = & MEP_CORE_ISA;
my_status = print_insn (cd, pc, info, insnbuf, corelength);
if (my_status != corelength)
{
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
my_status = corelength;
}
status += my_status;
/* Print the + to indicate that the following copro insn is */
/* part of a vliw group. */
if (copro1length > 0)
(*info->fprintf_func) (info->stream, " + ");
}
/* Now all that is left to be processed is the coprocessor insns
In vliw mode, there will always be one. Its positioning will
be from byte corelength to byte corelength+copro1length -1.
No need to check for existence. Also, the first vliw insn,
will, as spec'd, always be at least as long as the core insn
so we don't need to flush the buffer. */
if (copro1length > 0)
{
int my_status = 0;
for (i = corelength; i < corelength + copro1length; i++ )
insnbuf[i - corelength] = buf[i];
switch (copro1length)
{
case 0:
break;
case 2:
cd->isas = & MEP_COP16_ISA;
break;
case 4:
cd->isas = & MEP_COP32_ISA;
break;
case 6:
cd->isas = & MEP_COP48_ISA;
break;
case 8:
cd->isas = & MEP_COP64_ISA;
break;
default:
/* Shouldn't be anything but 16,32,48,64. */
break;
}
my_status = print_insn (cd, pc, info, insnbuf, copro1length);
if (my_status != copro1length)
{
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
my_status = copro1length;
}
status += my_status;
}
#if 0
/* Now we need to process the second copro insn if it exists. We
have no guarantee that the second copro insn will be longer
than the first, so we have to flush the buffer if we are have
a second copro insn to process. If present, this insn will
be in the position from byte corelength+copro1length to byte
corelength+copro1length+copro2length-1 (which better equal 8
or else we're in big trouble. */
if (copro2length > 0)
{
int my_status = 0;
for (i = 0; i < 64 ; i++)
insnbuf[i] = 0;
for (i = corelength + copro1length; i < 64; i++)
insnbuf[i - (corelength + copro1length)] = buf[i];
switch (copro2length)
{
case 2:
cd->isas = 1 << ISA_EXT_COP1_16;
break;
case 4:
cd->isas = 1 << ISA_EXT_COP1_32;
break;
case 6:
cd->isas = 1 << ISA_EXT_COP1_48;
break;
case 8:
cd->isas = 1 << ISA_EXT_COP1_64;
break;
default:
/* Shouldn't be anything but 16,32,48,64. */
break;
}
my_status = print_insn (cd, pc, info, insnbuf, copro2length);
if (my_status != copro2length)
{
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
my_status = copro2length;
}
status += my_status;
}
#endif
/* Status should now be the number of bytes that were printed
which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */
if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8)))
return -1;
else
return status;
}
/* The two functions mep_examine_vliw[32,64]_insns are used find out
which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
with 32 bit copro, etc.) is present. Later on, when internally
parallel coprocessors are handled, only these functions should
need to be changed.
At this time only the following combinations are supported:
VLIW32 Mode:
16 bit core insn (core) and 16 bit coprocessor insn (cop1)
32 bit core insn (core)
32 bit coprocessor insn (cop1)
Note: As of this time, I do not believe we have enough information
to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
no 16 bit coprocessor insns have been specified.
VLIW64 Mode:
16 bit core insn (core) and 48 bit coprocessor insn (cop1)
32 bit core insn (core) and 32 bit coprocessor insn (cop1)
64 bit coprocessor insn (cop1)
The framework for an internally parallel coprocessor is also
present (2nd coprocessor insn is cop2), but at this time it
is not used. This only appears to be valid in VLIW64 mode. */
static int
mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
int status;
int buflength;
int corebuflength;
int cop1buflength;
int cop2buflength;
bfd_byte buf[CGEN_MAX_INSN_SIZE];
char indicator16[1];
char indicatorcop32[2];
/* At this time we're not supporting internally parallel coprocessors,
so cop2buflength will always be 0. */
cop2buflength = 0;
/* Read in 32 bits. */
buflength = 4; /* VLIW insn spans 4 bytes. */
status = (*info->read_memory_func) (pc, buf, buflength, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
/* Put the big endian representation of the bytes to be examined
in the temporary buffers for examination. */
if (info->endian == BFD_ENDIAN_BIG)
{
indicator16[0] = buf[0];
indicatorcop32[0] = buf[0];
indicatorcop32[1] = buf[1];
}
else
{
indicator16[0] = buf[1];
indicatorcop32[0] = buf[1];
indicatorcop32[1] = buf[0];
}
/* If the two high order bits are 00, 01 or 10, we have a 16 bit
core insn and a 48 bit copro insn. */
if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
{
if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
{
/* We have a 32 bit copro insn. */
corebuflength = 0;
/* All 4 4ytes are one copro insn. */
cop1buflength = 4;
}
else
{
/* We have a 32 bit core. */
corebuflength = 4;
cop1buflength = 0;
}
}
else
{
/* We have a 16 bit core insn and a 16 bit copro insn. */
corebuflength = 2;
cop1buflength = 2;
}
/* Now we have the distrubution set. Print them out. */
status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
cop1buflength, cop2buflength);
return status;
}
static int
mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
int status;
int buflength;
int corebuflength;
int cop1buflength;
int cop2buflength;
bfd_byte buf[CGEN_MAX_INSN_SIZE];
char indicator16[1];
char indicator64[4];
/* At this time we're not supporting internally parallel
coprocessors, so cop2buflength will always be 0. */
cop2buflength = 0;
/* Read in 64 bits. */
buflength = 8; /* VLIW insn spans 8 bytes. */
status = (*info->read_memory_func) (pc, buf, buflength, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
return -1;
}
/* We have all 64 bits in the buffer now. We have to figure out
what combination of instruction sizes are present. The two
high order bits will indicate whether or not we have a 16 bit
core insn or not. If not, then we have to look at the 7,8th
bytes to tell whether we have 64 bit copro insn or a 32 bit
core insn with a 32 bit copro insn. Endianness will make a
difference here. */
/* Put the big endian representation of the bytes to be examined
in the temporary buffers for examination. */
/* indicator16[0] = buf[0]; */
if (info->endian == BFD_ENDIAN_BIG)
{
indicator16[0] = buf[0];
indicator64[0] = buf[0];
indicator64[1] = buf[1];
indicator64[2] = buf[2];
indicator64[3] = buf[3];
}
else
{
indicator16[0] = buf[1];
indicator64[0] = buf[1];
indicator64[1] = buf[0];
indicator64[2] = buf[3];
indicator64[3] = buf[2];
}
/* If the two high order bits are 00, 01 or 10, we have a 16 bit
core insn and a 48 bit copro insn. */
if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
{
if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
&& ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
{
/* We have a 64 bit copro insn. */
corebuflength = 0;
/* All 8 bytes are one copro insn. */
cop1buflength = 8;
}
else
{
/* We have a 32 bit core insn and a 32 bit copro insn. */
corebuflength = 4;
cop1buflength = 4;
}
}
else
{
/* We have a 16 bit core insn and a 48 bit copro insn. */
corebuflength = 2;
cop1buflength = 6;
}
/* Now we have the distrubution set. Print them out. */
status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
cop1buflength, cop2buflength);
return status;
}
static int
mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
int status;
/* Extract and adapt to configuration number, if available. */
if (info->section && info->section->owner)
{
bfd *abfd = info->section->owner;
mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
/* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
}
/* Picking the right ISA bitmask for the current context is tricky. */
if (info->section)
{
if (info->section->flags & SEC_MEP_VLIW)
{
/* Are we in 32 or 64 bit vliw mode? */
if (MEP_VLIW64)
status = mep_examine_vliw64_insns (cd, pc, info);
else
status = mep_examine_vliw32_insns (cd, pc, info);
/* Both the above branches set their own isa bitmasks. */
}
else
{
cd->isas = & MEP_CORE_ISA;
status = default_print_insn (cd, pc, info);
}
}
else /* sid or gdb */
{
status = default_print_insn (cd, pc, info);
}
return status;
}
/* -- opc.c */
#include "elf/mep.h"
/* A mask for all ISAs executed by the core. */
CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0};
void
init_mep_all_core_isas_mask (void)
{
if (mep_all_core_isas_mask.length != 0)
return;
cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX);
cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP);
/* begin-all-core-isas */
cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1);
cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE2);
/* end-all-core-isas */
}
CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0};
void
init_mep_all_cop_isas_mask (void)
{
if (mep_all_cop_isas_mask.length != 0)
return;
cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX);
/* begin-all-cop-isas */
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_16);
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_32);
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_48);
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_64);
/* end-all-cop-isas */
}
int
mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask)
{
CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
return cgen_bitset_intersect_p (& insn_isas, isa_mask);
}
#define OPTION_MASK \
( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \
| (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \
| (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \
| (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \
| (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \
| (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \
| (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \
| (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \
| (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \
| (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \
| (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \
| (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \
| (1 << CGEN_INSN_OPTIONAL_CP_INSN) \
| (1 << CGEN_INSN_OPTIONAL_CP64_INSN) )
mep_config_map_struct mep_config_map[] =
{
/* config-map-start */
/* Default entry: mep core only, all options enabled. */
{ "", 0, EF_MEP_CPU_C2, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
{ "simple", CONFIG_SIMPLE, EF_MEP_CPU_C2, 1, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
0 },
{ "fmax", CONFIG_FMAX, EF_MEP_CPU_C2, 1, 0, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x2" }, { 1, "\x1e" }, { 1, "\xa0" },
0
| (1 << CGEN_INSN_OPTIONAL_CP_INSN)
| (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
| (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
| (1 << CGEN_INSN_OPTIONAL_BIT_INSN)
| (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)
| (1 << CGEN_INSN_OPTIONAL_ABS_INSN)
| (1 << CGEN_INSN_OPTIONAL_AVE_INSN)
| (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)
| (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)
| (1 << CGEN_INSN_OPTIONAL_SAT_INSN) },
/* config-map-end */
{ 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 }
};
int mep_config_index = 0;
static int
check_configured_mach (int machs)
{
/* All base insns are supported. */
int mach = 1 << MACH_BASE;
switch (MEP_CPU)
{
case EF_MEP_CPU_C2:
case EF_MEP_CPU_C3:
mach |= (1 << MACH_MEP);
break;
case EF_MEP_CPU_H1:
mach |= (1 << MACH_H1);
break;
default:
break;
}
return machs & mach;
}
int
mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG);
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
int ok1;
int ok2;
int ok3;
/* If the insn has an option bit set that we don't want,
reject it. */
if (CGEN_INSN_ATTRS (insn)->bool & OPTION_MASK & ~MEP_OMASK)
return 0;
/* If attributes are absent, assume no restriction. */
if (machs == 0)
machs = ~0;
ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas));
/* If the insn is config-specific, make sure it matches. */
ok2 = (iconfig == 0 || iconfig == MEP_CONFIG);
/* Make sure the insn is supported by the configured mach */
ok3 = check_configured_mach (machs);
return (ok1 && ok2 && ok3);
}