Re: delayed branches and zero overhead loops

[Joern Rennecke <joernr at arc dot com>]

On Tue, Feb 13, 2007 at 01:51:19PM -0500, Frank Ch. Eigler wrote:
> Hi -
> 
> > The ARCompact architecture has delay slots and zero overhead loops.
> > I see that there is already a cgen simulator with delay slots, for
> > the iq2000.  I've looked at its mloop.in xextract-pbb case [...]
> 
> For what it's worth, my recollection about how the PBB stuff works is
> so hazy that I won't be able to give quick good advice.  Have you
> considered using a plain non-pbb kernel, where you can hand-code these
> subtleties in plain C/C++ code?

Yes, I have.  In fact I though for a while that pbb was plain impossible,
because I had a part of the instruction length calculation in the
semantics, but that left me uncomfortable because it seemed like I was
only going to write a proof that you can make a slow simulator swith cgen.

The problem is that long immediates are available to a lot of different
instruction formats by using an encoding that looks like 'core register 62'.
Most of the instructions have two fields that can specify that.
Trying to express this with separate formats is not feasible, a this would
only quadruple the number of insn definition (double the number of formats
but awkward decoding), but also cause trouble making the decoder generator
comprehend where the boundaries between the different formats are.

So I originally had the immediate fecth and pc increment in a piece of
semantics.
Now I've figured out I can go pbb by doing the pc increment based on
instruction attributes in the pbb acse of mloop*.in.