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mep: Add C5 support
- From: DJ Delorie <dj at redhat dot com>
- To: cgen at sourceware dot org
- Date: Tue, 7 Apr 2009 22:39:55 -0400
- Subject: mep: Add C5 support
This patch adds support for the MeP C5 core. This adds a few new
opcodes, as well as extending (in a backward compatible way) some
existing opcodes. Ok?
* cpu/mep-c5.cpu: New.
* cpu/mep-core.cpu: Add C5 support.
* cpu/mep.opc: Likewise.
Index: cpu/mep-c5.cpu
===================================================================
RCS file: cpu/mep-c5.cpu
diff -N cpu/mep-c5.cpu
--- cpu/mep-c5.cpu 1 Jan 1970 00:00:00 -0000
+++ cpu/mep-c5.cpu 8 Apr 2009 02:31:00 -0000
@@ -0,0 +1,263 @@
+; Insns introduced for the MeP-c5 core
+;
+
+(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4)
+(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4)
+(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4)
+(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4)
+(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
+(dnf f-12s20 "extended field" (all-mep-core-isas) 20 12)
+
+(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
+(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20)
+
+(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
+ "stcb $rn,($rma)"
+ (+ MAJ_7 rn rma (f-sub4 12))
+ (c-call VOID "do_stcb" rn (and rma #xffff))
+ ((mep (unit u-use-gpr (in usereg rn))
+ (unit u-use-gpr (in usereg rma))
+ (unit u-exec)
+ (unit u-stcb))))
+
+(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
+ "ldcb $rn,($rma)"
+ (+ MAJ_7 rn rma (f-sub4 13))
+ (set rn (c-call SI "do_ldcb" (and rma #xffff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-ldcb)
+ (unit u-exec)
+ (unit u-ldcb-gpr (out loadreg rn)))))
+
+(dnci pref "cache prefetch" ((MACH c5) VOLATILE)
+ "pref $cimm4,($rma)"
+ (+ MAJ_7 cimm4 rma (f-sub4 5))
+ (sequence ()
+ (c-call VOID "check_option_dcache" pc)
+ (c-call VOID "do_cache_prefetch" cimm4 rma pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
+ "pref $cimm4,$sdisp16($rma)"
+ (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)
+ (sequence ()
+ (c-call VOID "check_option_dcache" pc)
+ (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "casb3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
+ (sequence ()
+ (c-call VOID "do_casb3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "cash3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))
+ (sequence ()
+ (c-call VOID "do_cash3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+ "casw3 $rl5,$rn,($rm)"
+ (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))
+ (sequence ()
+ (c-call VOID "do_casw3" (index-of rl5) rn rm pc)
+ (set rl5 rl5)
+ )
+ ((mep (unit u-use-gpr (in usereg rl5))
+ (unit u-load-gpr (out loadreg rl5))
+ (unit u-exec))))
+
+
+
+(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "sbcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+ (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lbcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lbucp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+
+(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "shcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+ (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lhcp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+ "lhucp $crn,$cdisp12($rma)"
+ (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+
+(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+ "lbucpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (add rma cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+ "lhucpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (add rma (ext SI cdisp10a2))))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))
+ "lbucpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (mod0 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))
+ "lhucpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod0 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))
+ "lbucpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem QI rma)))
+ (set rma (mod1 cdisp10)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN)
+ "lhucpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)
+ (sequence ()
+ (c-call "check_option_cp" pc)
+ (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+ (set rma (mod1 cdisp10a2)))
+ ((mep (unit u-use-gpr (in usereg rma))
+ (unit u-exec))))
+
+(dnci uci "uci" ((MACH c5) VOLATILE)
+ "uci $rn,$rm,$uimm16"
+ (+ MAJ_15 rn rm (f-sub4 2) simm16)
+ (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8)
+(dnf f-c5-rm "register m" (all-mep-isas) 8 4)
+(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f)
+
+(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+ (f-c5-rm f-c5-16u16)
+ (sequence () ; insert
+ (set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16))
+ (set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
+ )
+ (sequence () ; extract
+ (set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
+ (sll (ifield f-c5-rm) 16)))
+ )
+ )
+(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)
+
+(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+ (f-c5-rnm f-c5-16u16)
+ (sequence () ; insert
+ (set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16))
+ (set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
+ )
+ (sequence () ; extract
+ (set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
+ (sll (ifield f-c5-rnm) 16)))
+ )
+ )
+(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)
+
+(dnci dsp "dsp" ((MACH c5) VOLATILE)
+ "dsp $rn,$rm,$uimm16"
+ (+ MAJ_15 rn rm (f-sub4 0) uimm16)
+ (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))
+ ((mep (unit u-use-gpr (in usereg rm))
+ (unit u-use-gpr (in usereg rn))
+ (unit u-exec))))
+
+(dncmi dsp0 "dsp0" ((MACH c5) NO-DIS VOLATILE)
+ "dsp0 $c5rnmuimm24"
+ (emit dsp
+ (rn (sll c5rnmuimm24 20))
+ (rm (and (sll c5rnmuimm24 16) #xf))
+ (uimm16 (and c5rnmuimm24 #xffff)))
+ )
+
+(dncmi dsp1 "dsp1" ((MACH c5) NO-DIS VOLATILE)
+ "dsp1 $rn,$c5rmuimm20"
+ (emit dsp
+ rn
+ (rm (sll c5rnmuimm24 16))
+ (uimm16 (and c5rnmuimm24 #xffff)))
+ )
Index: cpu/mep-core.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/mep-core.cpu,v
retrieving revision 1.3
diff -p -U3 -r1.3 cpu/mep-core.cpu
--- cpu/mep-core.cpu 3 Feb 2009 21:30:16 -0000 1.3
+++ cpu/mep-core.cpu 8 Apr 2009 02:31:01 -0000
@@ -17,7 +17,7 @@
(name mep)
(comment "Toshiba MeP Media Engine")
(insn-lsb0? #f) ;; work around cgen limitation
- (machs mep h1)
+ (machs mep h1 c5)
isa-enum
)
@@ -67,10 +67,17 @@
isa-enum
)
+(define-mach
+ (name c5)
+ (comment "C5 media engine")
+ (cpu mepf)
+ isa-enum
+)
+
(define-model
(name mep)
(comment "MeP media engine processor")
- (mach mep) ; mach gets changed by MeP-Integrator
+ (mach c5) ; mach gets changed by MeP-Integrator
(unit u-exec "execution unit" ()
1 1 ; issue done
@@ -281,6 +288,8 @@
(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3)
(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4)
(dnf f-ext "extended field" (all-mep-core-isas) 16 8)
+(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4)
+(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2)
(dnf f-crn "copro register n" (all-mep-core-isas) 4 4)
(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
@@ -436,16 +445,21 @@
; These are all for the coprocessor opcodes
-(df f-8s24 "copro b-offset (8 bits)" (all-mep-core-isas) 24 8 INT #f #f)
-(df f-8s24a2 "copro h-offset (8 bits)" (all-mep-core-isas) 24 7 INT
- ((value pc) (sra SI value 1))
- ((value pc) (sll SI value 1)))
-(df f-8s24a4 "copro w-offset (8 bits)" (all-mep-core-isas) 24 6 INT
- ((value pc) (sra SI value 2))
- ((value pc) (sll SI value 2)))
-(df f-8s24a8 "copro m-offset (8 bits)" (all-mep-core-isas) 24 5 INT
- ((value pc) (sra SI value 3))
- ((value pc) (sll SI value 3)))
+; The field is like IJKiiiiiii where I and J are toggled if K is set,
+; for compatibility with older cores.
+(define-pmacro (compute-cdisp10 val)
+ (cond SI
+ ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200)
+ (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400))
+ (else
+ (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)))
+ )
+ )
+
+(df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 UINT
+ ((value pc) (compute-cdisp10 value))
+ ((value pc) (compute-cdisp10 value))
+ )
; Non-contiguous fields.
@@ -667,10 +681,11 @@
(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn)
(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24)
-(dnop cdisp8 "copro addend (8 bits)" (all-mep-core-isas) h-sint f-8s24)
-(dpop cdisp8a2 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 2)) h-sint f-8s24a2 "mep_align")
-(dpop cdisp8a4 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 4)) h-sint f-8s24a4 "mep_align")
-(dpop cdisp8a8 "copro addend (8 bits)" (all-mep-core-isas (ALIGN 8)) h-sint f-8s24a8 "mep_align")
+
+(dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
+(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10")
; Special operand representing the various ways that the literal zero can be
; specified.
@@ -955,6 +970,36 @@
+; pmacros needed for coprocessor modulo addressing.
+
+; Taken from supplement ``The operation of the modulo addressing'' in
+; Toshiba documentation rev 2.2, p. 34.
+
+(define-pmacro (compute-mask0)
+ (sequence SI ((SI temp))
+ (set temp (or mb0 me0))
+ (srl (const SI -1) (c-call SI "do_ldz" temp))))
+
+(define-pmacro (mod0 immed)
+ (sequence SI ((SI modulo-mask))
+ (set modulo-mask (compute-mask0))
+ (if SI (eq (and rma modulo-mask) me0)
+ (or (and rma (inv modulo-mask)) mb0)
+ (add rma (ext SI immed)))))
+
+(define-pmacro (compute-mask1)
+ (sequence SI ((SI temp))
+ (set temp (or mb1 me1))
+ (srl (const SI -1) (c-call SI "do_ldz" temp))))
+
+(define-pmacro (mod1 immed)
+ (sequence SI ((SI modulo-mask))
+ (set modulo-mask (compute-mask1))
+ (if SI (eq (and rma modulo-mask) me1)
+ (or (and rma (inv modulo-mask)) mb1)
+ (add rma (ext SI immed)))))
+
+
; Instructions.
; A pmacro for use in semantic bodies of unimplemented insns.
@@ -962,6 +1007,7 @@
; Core specific instructions
; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
+(include "mep-c5.cpu") ; -- exposed by MeP-Integrator
; Load/store instructions.
@@ -2482,290 +2528,261 @@
(unit u-exec))))
(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
- "sbcpa $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext 0) cdisp8)
+ "sbcpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
- (set rma (add rma (ext SI cdisp8))))
+ (set rma (add rma (ext SI cdisp10))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
- "lbcpa $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x40) cdisp8)
+ "lbcpa $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
- (set rma (add rma (ext SI cdisp8))))
+ (set rma (add rma (ext SI cdisp10))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
- "shcpa $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x10) cdisp8a2 (f-31 0))
+ "shcpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
- (set rma (add rma (ext SI cdisp8a2))))
+ (set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
- "lhcpa $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x50) cdisp8a2 (f-31 0))
+ "lhcpa $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
- (set rma (add rma (ext SI cdisp8a2))))
+ (set rma (add rma (ext SI cdisp10a2))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
- "swcpa $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x20) cdisp8a4 (f-30 0) (f-31 0))
+ "swcpa $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
- (set rma (add rma (ext SI cdisp8a4))))
+ (set rma (add rma (ext SI cdisp10a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
- "lwcpa $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x60) cdisp8a4 (f-30 0) (f-31 0))
+ "lwcpa $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
- (set rma (add rma (ext SI cdisp8a4))))
+ (set rma (add rma (ext SI cdisp10a4))))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
- "smcpa $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x30) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "smcpa $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
- (c-call "do_smcpa" (index-of rma) cdisp8a8 crn64 pc)
+ (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc)
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
- "lmcpa $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x70) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "lmcpa $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
- (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp8a8 pc))
+ (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc))
(set rma rma)) ; reference as output for intrinsic generation
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
-; pmacros needed for coprocessor modulo addressing.
-
-; Taken from supplement ``The operation of the modulo addressing'' in
-; Toshiba documentation rev 2.2, p. 34.
-
-(define-pmacro (compute-mask0)
- (sequence SI ((SI temp))
- (set temp (or mb0 me0))
- (srl (const SI -1) (c-call SI "do_ldz" temp))))
-
-(define-pmacro (mod0 immed)
- (sequence SI ((SI modulo-mask))
- (set modulo-mask (compute-mask0))
- (if SI (eq (and rma modulo-mask) me0)
- (or (and rma (inv modulo-mask)) mb0)
- (add rma (ext SI immed)))))
-
-(define-pmacro (compute-mask1)
- (sequence SI ((SI temp))
- (set temp (or mb1 me1))
- (srl (const SI -1) (c-call SI "do_ldz" temp))))
-
-(define-pmacro (mod1 immed)
- (sequence SI ((SI modulo-mask))
- (set modulo-mask (compute-mask1))
- (if SI (eq (and rma modulo-mask) me1)
- (or (and rma (inv modulo-mask)) mb1)
- (add rma (ext SI immed)))))
-
(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
- "sbcpm0 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x08) cdisp8)
+ "sbcpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
- (set rma (mod0 cdisp8)))
+ (set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
- "lbcpm0 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x48) cdisp8)
+ "lbcpm0 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
- (set rma (mod0 cdisp8)))
+ (set rma (mod0 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
- "shcpm0 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x18) cdisp8a2 (f-31 0))
+ "shcpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
- (set rma (mod0 cdisp8a2)))
+ (set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
- "lhcpm0 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x58) cdisp8a2 (f-31 0))
+ "lhcpm0 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
- (set rma (mod0 cdisp8a2)))
+ (set rma (mod0 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
- "swcpm0 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x28) cdisp8a4 (f-30 0) (f-31 0))
+ "swcpm0 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
- (set rma (mod0 cdisp8a4)))
+ (set rma (mod0 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
- "lwcpm0 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x68) cdisp8a4 (f-30 0) (f-31 0))
+ "lwcpm0 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (mem SI (and rma (inv SI 3))))
- (set rma (mod0 cdisp8a4)))
+ (set rma (mod0 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "smcpm0 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x38) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "smcpm0 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call VOID "check_write_to_text" rma)
(c-call "do_smcp" rma crn64 pc)
- (set rma (mod0 cdisp8a8)))
+ (set rma (mod0 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "lmcpm0 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x78) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "lmcpm0 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
- (set rma (mod0 cdisp8a8)))
+ (set rma (mod0 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
- "sbcpm1 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x0c) cdisp8)
+ "sbcpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" rma)
(set (mem QI rma) (and crn #xff))
- (set rma (mod1 cdisp8)))
+ (set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
- "lbcpm1 $crn,($rma+),$cdisp8"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x4c) cdisp8)
+ "lbcpm1 $crn,($rma+),$cdisp10"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem QI rma)))
- (set rma (mod1 cdisp8)))
+ (set rma (mod1 cdisp10)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
- "shcpm1 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x1c) cdisp8a2 (f-31 0))
+ "shcpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 1)))
(set (mem HI (and rma (inv SI 1))) (and crn #xffff))
- (set rma (mod1 cdisp8a2)))
+ (set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
- "lhcpm1 $crn,($rma+),$cdisp8a2"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x5c) cdisp8a2 (f-31 0))
+ "lhcpm1 $crn,($rma+),$cdisp10a2"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem HI (and rma (inv SI 1)))))
- (set rma (mod1 cdisp8a2)))
+ (set rma (mod1 cdisp10a2)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
- "swcpm1 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x2c) cdisp8a4 (f-30 0) (f-31 0))
+ "swcpm1 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(c-call VOID "check_write_to_text" (and rma (inv SI 3)))
(set (mem SI (and rma (inv SI 3))) crn)
- (set rma (mod1 cdisp8a4)))
+ (set rma (mod1 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
- "lwcpm1 $crn,($rma+),$cdisp8a4"
- (+ MAJ_15 crn rma (f-sub4 5) (f-ext #x6c) cdisp8a4 (f-30 0) (f-31 0))
+ "lwcpm1 $crn,($rma+),$cdisp10a4"
+ (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4)
(sequence ()
(c-call "check_option_cp" pc)
(set crn (ext SI (mem SI (and rma (inv SI 3)))))
- (set rma (mod1 cdisp8a4)))
+ (set rma (mod1 cdisp10a4)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "smcpm1 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x3c) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "smcpm1 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(c-call "do_smcp" rma crn64 pc)
(c-call VOID "check_write_to_text" rma)
- (set rma (mod1 cdisp8a8)))
+ (set rma (mod1 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
- "lmcpm1 $crn64,($rma+),$cdisp8a8"
- (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext #x7c) cdisp8a8 (f-29 0) (f-30 0) (f-31 0))
+ "lmcpm1 $crn64,($rma+),$cdisp10a8"
+ (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8)
(sequence ()
(c-call "check_option_cp" pc)
(c-call "check_option_cp64" pc)
(set crn64 (c-call DI "do_lmcp" rma pc))
- (set rma (mod1 cdisp8a8)))
+ (set rma (mod1 cdisp10a8)))
((mep (unit u-use-gpr (in usereg rma))
(unit u-exec))))
@@ -2911,14 +2928,10 @@
(dnri 21 MAJ_7 15)
(dnri 22 MAJ_12 7)
(dnri 23 MAJ_14 13)
-(dnri 24 MAJ_15 3)
-(dnri 25 MAJ_15 6)
+;(dnri 24 MAJ_15 3)
(dnri 26 MAJ_15 8)
-; begin non-mep-h1 reserved insns
-(dnri 16 MAJ_7 5)
-(dnri 18 MAJ_7 12)
-(dnri 19 MAJ_7 13)
-; end non-mep-h1 reserved insns
+; begin core-specific reserved insns
+; end core-specific reserved insns
; Macro instructions.
Index: cpu/mep.opc
===================================================================
RCS file: /cvs/src/src/cgen/cpu/mep.opc,v
retrieving revision 1.2
diff -p -U3 -r1.2 cpu/mep.opc
--- cpu/mep.opc 3 Feb 2009 21:30:16 -0000 1.2
+++ cpu/mep.opc 8 Apr 2009 02:31:01 -0000
@@ -74,6 +74,8 @@ extern int mep_cgen_insn_supported (CGEN
/* -- asm.c */
+#include "elf/mep.h"
+
#define CGEN_VALIDATE_INSN_SUPPORTED
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
@@ -149,9 +151,6 @@ parse_mep_align (CGEN_CPU_DESC cd, const
case MEP_OPERAND_PCREL12A2:
case MEP_OPERAND_PCREL17A2:
case MEP_OPERAND_PCREL24A2:
- case MEP_OPERAND_CDISP8A2:
- case MEP_OPERAND_CDISP8A4:
- case MEP_OPERAND_CDISP8A8:
err = cgen_parse_signed_integer (cd, strp, type, field);
break;
case MEP_OPERAND_PCABS24A2:
@@ -178,16 +177,13 @@ parse_mep_align (CGEN_CPU_DESC cd, const
case MEP_OPERAND_PCREL24A2:
case MEP_OPERAND_PCABS24A2:
case MEP_OPERAND_UDISP7A2:
- case MEP_OPERAND_CDISP8A2:
lsbs = *field & 1;
break;
case MEP_OPERAND_UDISP7A4:
case MEP_OPERAND_UIMM7A4:
case MEP_OPERAND_ADDR24A4:
- case MEP_OPERAND_CDISP8A4:
lsbs = *field & 3;
break;
- case MEP_OPERAND_CDISP8A8:
lsbs = *field & 7;
break;
default:
@@ -464,6 +460,66 @@ parse_unsigned7 (CGEN_CPU_DESC cd, const
return parse_mep_alignu (cd, strp, opindex, valuep);
}
+static ATTRIBUTE_UNUSED const char *
+parse_cdisp10 (CGEN_CPU_DESC cd,
+ const char **strp,
+ int opindex,
+ long *valuep)
+{
+ const char *errmsg = 0;
+ signed long value;
+ long have_zero = 0;
+ int wide = 0;
+ int alignment;
+
+ switch (opindex)
+ {
+ case MEP_OPERAND_CDISP10A4:
+ alignment = 2;
+ break;
+ case MEP_OPERAND_CDISP10A2:
+ alignment = 1;
+ break;
+ case MEP_OPERAND_CDISP10:
+ default:
+ alignment = 0;
+ break;
+ }
+
+ if (MEP_CPU == EF_MEP_CPU_C5)
+ wide = 1;
+
+ if (strncmp (*strp, "0x0", 3) == 0
+ || (**strp == '0' && *(*strp + 1) != 'x'))
+ have_zero = 1;
+
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+ if (errmsg)
+ return errmsg;
+
+ if (wide)
+ {
+ if (value < -512 || value > 511)
+ return _("Immediate is out of range -512 to 511");
+ }
+ else
+ {
+ if (value < -128 || value > 127)
+ return _("Immediate is out of range -128 to 127");
+ }
+
+ if (value & ((1<<alignment)-1))
+ return _("Value is not aligned enough");
+
+ /* If this field may require a relocation then use larger dsp16. */
+ if (! have_zero && value == 0)
+ return (wide ? _("Immediate is out of range -512 to 511")
+ : _("Immediate is out of range -128 to 127"));
+
+ *valuep = value;
+ return 0;
+}
+
/* BEGIN LIGHTWEIGHT MACRO PROCESSOR. */
#define MAXARGS 9
@@ -1181,8 +1237,8 @@ mep_config_map_struct mep_config_map[] =
{
/* config-map-start */
/* Default entry: mep core only, all options enabled. */
- { "", 0, EF_MEP_CPU_C4, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
- { "default", CONFIG_DEFAULT, EF_MEP_CPU_C4, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
+ { "", 0, EF_MEP_CPU_C5, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
+ { "default", CONFIG_DEFAULT, EF_MEP_CPU_C5, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
0
| (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
| (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
@@ -1213,6 +1269,10 @@ check_configured_mach (int machs)
case EF_MEP_CPU_H1:
mach |= (1 << MACH_H1);
break;
+ case EF_MEP_CPU_C5:
+ mach |= (1 << MACH_MEP);
+ mach |= (1 << MACH_C5);
+ break;
default:
break;
}