problem with 64-bit arch

[Jean-Marc Saffroy <jean-marc dot saffroy at joguin dot com>]

Hi,

I am trying to use CGEN for an experimental 64-bit architecture (ie. 
word-bitsize is 64), and in my case the generated arch-ibld.c file is 
incorrect.

I defined the following insn field:

(df f-disp24     "disp24"              (PCREL-ADDR) 8 24 INT
    ((value pc) (sra WI (sub WI value pc) (const 2)))
    ((value pc) (add WI (sll WI value (const 2)) pc))
)

(define-operand
  (name disp24)
  (comment "24 bit signed displacement")
  (type h-iaddr)
  (mode WI)
  (index f-disp24)
)

And arch-ibld.c contains the following code (in <arch>_cgen_insert_operand):

  switch (opindex)
    {
    case <ARCH>_OPERAND_DISP24 :
      {
        long value = fields->f_disp24;
        value = (() (((value) - (pc))) >> (2));
        errmsg = insert_normal (cd, value,
0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32,
total_length, buffer);
      }
      break;

Note the missing type in the cast before assigning to value. Also using 
a long type for value will cause problems when running on a 32-bit host, 
since it operates on 64-bit values.

I had a quick look at the other two archs that use word-bitsize 64, ie. 
sparc64 and ia64, and it seems they use multi-ifields for this kind of 
PC-relative field, which may be an artificial way of avoiding the problem.

Is there an obvious fix to this problem?

Cheers,
JM