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Delay slots in GNU sim
- From: Julius Baxter <juliusbaxter at gmail dot com>
- To: cgen at sourceware dot org
- Date: Sun, 15 Jan 2012 14:24:25 +1100
- Subject: Delay slots in GNU sim
Hi,
I've been working on the OpenRISC CGEN description and have got the
assembler working and am now looking at getting a GNU sim port running
too.
I can see a lot of functionality working OK so far (I've based my
simulator port on the lm32 and m32r ports, which are both CGEN-based
implementations of the simulator) but one thing which is not working
are delay slots. They never appear to b executed when a branch is
going to be taken.
I'm yet to delve into the workings if the simulator to figure out why
it's not executing the delay slots, but I just wanted to ask if this
is a known issue with the particular configuration I'm using. The sim
port has "#define WITH_SCACHE_PBB 1", in the tconfig.in file and the
Makefile calls the mloop.c generation script with:
...
$(SHELL) $(srccom)/genmloop.sh \
-mono -fast -pbb -full-switch -switch sem-switch.c \
-cpu or1k32bef -infile $(srcdir)/mloop.in
...
My understanding is that this will generate a main loop for a "fast"
model with pseudo-basic-block processing. This is an "upgrade" over
the default "simple" model without pbb.
I'm wondering if delay slots not working are a known issue when
compiling a fast model with pbb support?
As far as I can tell, my semantic description is correct. For example,
the jump instruction is:
(dni l-j "jump (pc-relative iaddr)"
; This function may not be in delay slot
(NOT-IN-DELAY-SLOT)
"l.j ${disp-26}"
(+ OPC_J disp-26)
; We execute the delay slot before doin' the real branch
(delay 1 (set pc disp-26))
()
)
Other semantic descriptions of delay slot execution appear to be along
the same lines, but I can't see any CGEN-based sim ports which have
instructions with delay slots, so, as I said, I'm wondering if this is
even supported at all.
Thanks for any help,
Julius