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[PATCH] Addons for OpenRISC support
- From: Christian Svensson <blue at cmd dot nu>
- To: cgen at sourceware dot org
- Date: Wed, 23 Apr 2014 22:24:00 +0000
- Subject: [PATCH] Addons for OpenRISC support
- Authentication-results: sourceware.org; auth=none
Hi,
We (OpenRISC) have recently begun upstreaming a lot of code. One of the first
things is our binutils port which depends on these CGEN modifications.
This patch has been living in the OpenRISC CGEN repository since 2012.
I would be delighted if it could be merged.
I'm submitting this patch but the author is Peter Gavin, one of the co-authors
of the binutils port.
2014-04-23 Peter Gavin <pgavin@gmail.com>
* sim-arch.scm: define WI, UWI, AI, & IAI using mode:c-type
* add mul-o1flag (1's complement unsigned multiply overflow flag)
and mul-o2flag (2's complement signed multiply overflow flag)
* rtl-c.scm:
(rem) add rem (reminder) function (needed for OR1K lf.rem.[sd])
(mul-o1flag) new define-fn
(mul-o2flag) ditto
* rtx-funcs.scm:
(rem) add rem (reminder) function (needed for OR1K lf.rem.[sd])
(mul-o1flag) new drn
(mul-o2flag) ditto
--- cgen.orig/rtl-c.scm 2010-08-30 16:51:27.000000000 +0000
+++ cgen/rtl-c.scm 2014-01-11 11:53:15.565783879 +0000
@@ -1746,6 +1746,14 @@
(define-fn mul (*estate* options mode s1 s2)
(s-binop *estate* "MUL" "*" mode s1 s2)
)
+; 1's complement overflow
+(define-fn mul-o1flag (*estate* options mode s1 s2)
+ (s-binop *estate* "MUL1OF" #f mode s1 s2)
+)
+; 2's complement overflow
+(define-fn mul-o2flag (*estate* options mode s1 s2)
+ (s-binop *estate* "MUL2OF" #f mode s1 s2)
+)
(define-fn div (*estate* options mode s1 s2)
(s-binop *estate* "DIV" "/" mode s1 s2)
)
@@ -1758,6 +1766,9 @@
(define-fn umod (*estate* options mode s1 s2)
(s-binop *estate* "UMOD" "%" mode s1 s2)
)
+(define-fn rem (*estate* options mode s1 s2)
+ (s-binop *estate* "REM" #f mode s1 s2)
+)
(define-fn sqrt (*estate* options mode s1)
(s-unop *estate* "SQRT" #f mode s1)
--- cgen.orig/rtx-funcs.scm 2010-01-25 03:50:43.000000000 +0000
+++ cgen/rtx-funcs.scm 2014-01-11 11:53:15.565783879 +0000
@@ -755,6 +755,20 @@
BINARY
#f
)
+; 1's complement overflow
+(drn (mul-o1flag &options &mode s1 s2)
+ BI
+ (OPTIONS ANYINTMODE RTX RTX) (NA NA MATCHEXPR MATCH2)
+ BINARY
+ #f
+)
+; 2's complement overflow
+(drn (mul-o2flag &options &mode s1 s2)
+ BI
+ (OPTIONS ANYINTMODE RTX RTX) (NA NA MATCHEXPR MATCH2)
+ BINARY
+ #f
+)
; ??? In non-sim case, ensure s1,s2 is in right C type for right result.
; ??? Need two variants, one that avoids implementation defined situations
; [both host and target], and one that specifies implementation defined
@@ -783,6 +797,12 @@
BINARY
#f
)
+(drn (rem &options &mode s1 s2)
+ #f
+ (OPTIONS ANYFLOATMODE RTX RTX) (NA NA MATCHEXPR MATCH2)
+ BINARY
+ #f
+)
; wip: mixed mode mul/div
--- cgen.orig/sim-arch.scm 2009-11-23 00:59:57.000000000 +0000
+++ cgen/sim-arch.scm 2014-01-11 11:53:15.565783879 +0000
@@ -100,10 +100,10 @@
"\n"
"#define TARGET_BIG_ENDIAN 1\n\n" ; FIXME
;(gen-mem-macros)
- ;"/* FIXME: split into 32/64 parts */\n"
- ;"#define WI SI\n"
- ;"#define UWI USI\n"
- ;"#define AI USI\n\n"
+ "#define WI " (mode:c-type WI) "\n"
+ "#define UWI " (mode:c-type UWI) "\n"
+ "#define AI " (mode:c-type AI) "\n" "\n"
+ "#define IAI " (mode:c-type IAI) "\n" "\n"
/gen-cpuall-defines
/gen-support-decls
/gen-arch-model-decls