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So when will the FSF start addressing the development of hardware? There is already a Verilog simulation system available under GPL or some other free software arrangement. What is needed is a systhesizer, which is the tool that converts the HDL to a netlist of low level gates, somewhat like the code generation phase of a software compiler, and a floorplanning tool, which essentially does the job of a linking loader for hardware. Most work on the GNU project is done by volunteers. Circuit design is a rather specialized application, so we won't be spending funds on it; we have to wait for volunteers to do it.