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On Tue, Dec 05, 2000 at 03:52:33PM +0100, Julien Ducourthial wrote: > The exact behaviour seems to depend on the PPC model. I worked on a driver for AMD > ethernet chip, for an in-house OS. There was no eieio in the code, but the registers > were mapped with guarded and cache-inhibited mmu attributes. It ran flawlessly on a > 603e board. But when we received newer boards with 604e cpu, the driver wasn't > anymore working. Ah - IIRC, the MPC860 has a 603 or 603e core (I don't have access to the manuals until I am back in office next week), so we should be safe *for now*. > first write its adress then read the data. Without eieio in between, the read is made > ahead of the write (at least on the 604e) and ... you do not really get the data > expected. Yup - there's enough other scenarios where re-ordered accesses can cause problems even when all registers are directly memory-mapped, and on the MPC860, you also have to take care of the buffer descriptors which may be in main memory for some peripherals. cu Michael ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sourceware.cygnus.com
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