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Hi All I am hoping someone can help. I am looking for startup / exception handler code for a TX19L for handling the NMI. According to the information I have, the R4000 (and the TX19L) share the reset vector for the hardware reset, soft reset and nmi events, and the handler code is required to differentiate between S/W and H/W resets using the SR bit of the status register, and the NMI and Soft reset are differentiated using "system level identification", which I assume can be implemented using a variable in NVRAM. The CRT0 code that I have examined (from newlib, and a couple of commercial compilers) makes no checking of the SR bit, and just proceeds as if the event is a H/W reset. Has anybody written an exception handler for this to both differentiate between RESET/Soft RESET and NMI events ? Have I missed something (I am fairly new to MIPS development). Regards Robert Ward -- -------------------------------------------------------------------------- VaST Systems Technology Tel: +61 2 9460 4945 349 Pacific Highway, Suite 204, Fax: +61 2 9460 4954 North Sydney NSW 2060 Email: r.ward@vastsytems.com Australia Web: http://www.vastsystems.com -------------------------------------------------------------------------- ------ Want more information? See the CrossGCC FAQ, http://www.objsw.com/CrossGCC/ Want to unsubscribe? Send a note to crossgcc-unsubscribe@sources.redhat.com
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