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Hi, Here is a seperated patch for gcc 4.6.0 + binutils 2.21.1 for SPARC-LEON. -- Greetings Konrad
>From 9f1a836df137053c696ea80403189d71deef72fa Mon Sep 17 00:00:00 2001
From: Konrad Eisele <konrad@gaisler.com>
Date: Mon, 5 Dec 2011 09:45:56 +0100
Subject: [PATCH 1/1] patches: Add SPARC LEON gcc 4.6.0 patch, add binutils 2.21.1a patch
gcc: Adds support for vendor [hf|sf]leon[v8], readds the -mv8 switch.
binutils: Adds -Aleon support, enables "casa" and smac/umac insns for LEON.
Signed-off-by: Konrad Eisele <konrad@gaisler.com>
---
patches/binutils/2.21.1a/400-sparc-leon.patch | 107 +++++++
patches/gcc/4.6.0/200-sparc-leon.patch | 423 +++++++++++++++++++++++++
2 files changed, 530 insertions(+), 0 deletions(-)
create mode 100644 patches/binutils/2.21.1a/400-sparc-leon.patch
create mode 100644 patches/gcc/4.6.0/200-sparc-leon.patch
diff --git a/patches/binutils/2.21.1a/400-sparc-leon.patch b/patches/binutils/2.21.1a/400-sparc-leon.patch
new file mode 100644
index 0000000..c08d0ad
--- /dev/null
+++ b/patches/binutils/2.21.1a/400-sparc-leon.patch
@@ -0,0 +1,107 @@
+diff -Naur binutils-2.21.1.ori/gas/config/tc-sparc.c binutils-2.21.1/gas/config/tc-sparc.c
+--- binutils-2.21.1.ori/gas/config/tc-sparc.c 2011-11-10 11:55:35.000000000 +0100
++++ binutils-2.21.1/gas/config/tc-sparc.c 2011-11-10 12:00:24.000000000 +0100
+@@ -212,7 +212,7 @@
+ for this use. That table is for opcodes only. This table is for opcodes
+ and file formats. */
+
+-enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
++enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
+ v8plusa, v9, v9a, v9b, v9_64};
+
+ static struct sparc_arch {
+@@ -228,6 +228,7 @@
+ { "v6", "v6", v6, 0, 1 },
+ { "v7", "v7", v7, 0, 1 },
+ { "v8", "v8", v8, 32, 1 },
++ { "leon", "leon", leon, 32, 1 },
+ { "sparclet", "sparclet", sparclet, 32, 1 },
+ { "sparclite", "sparclite", sparclite, 32, 1 },
+ { "sparc86x", "sparclite", sparc86x, 32, 1 },
+diff -Naur binutils-2.21.1.ori/gas/configure.tgt binutils-2.21.1/gas/configure.tgt
+--- binutils-2.21.1.ori/gas/configure.tgt 2011-11-10 11:55:34.000000000 +0100
++++ binutils-2.21.1/gas/configure.tgt 2011-11-10 12:01:43.000000000 +0100
+@@ -80,6 +80,11 @@
+ sparclet*) cpu_type=sparc arch=sparclet ;;
+ sparclite*) cpu_type=sparc arch=sparclite ;;
+ sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
++ sparc*)
++ case ${vendor} in
++ *leon*) cpu_type=sparc arch=leon ;;
++ *) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
++ esac ;;
+ strongarm*be) cpu_type=arm endian=big ;;
+ strongarm*b) cpu_type=arm endian=big ;;
+ strongarm*) cpu_type=arm endian=little ;;
+diff -Naur binutils-2.21.1.ori/include/opcode/sparc.h binutils-2.21.1/include/opcode/sparc.h
+--- binutils-2.21.1.ori/include/opcode/sparc.h 2011-11-10 11:55:35.000000000 +0100
++++ binutils-2.21.1/include/opcode/sparc.h 2011-11-10 11:56:05.000000000 +0100
+@@ -42,6 +42,7 @@
+ SPARC_OPCODE_ARCH_V6 = 0,
+ SPARC_OPCODE_ARCH_V7,
+ SPARC_OPCODE_ARCH_V8,
++ SPARC_OPCODE_ARCH_LEON,
+ SPARC_OPCODE_ARCH_SPARCLET,
+ SPARC_OPCODE_ARCH_SPARCLITE,
+ /* V9 variants must appear last. */
+diff -Naur binutils-2.21.1.ori/opcodes/sparc-opc.c binutils-2.21.1/opcodes/sparc-opc.c
+--- binutils-2.21.1.ori/opcodes/sparc-opc.c 2011-11-10 11:55:36.000000000 +0100
++++ binutils-2.21.1/opcodes/sparc-opc.c 2011-11-10 11:56:05.000000000 +0100
+@@ -33,6 +33,7 @@
+ #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
+ #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
+ #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
++#define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
+ #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
+ #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
+ #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
+@@ -56,6 +57,7 @@
+ recognizes all v8 insns. */
+ #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
+ | MASK_V9 | MASK_V9A | MASK_V9B)
++#define leon (MASK_LEON)
+ #define sparclet (MASK_SPARCLET)
+ #define sparclite (MASK_SPARCLITE)
+ #define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
+@@ -76,6 +78,7 @@
+ { "v6", MASK_V6 },
+ { "v7", MASK_V6 | MASK_V7 },
+ { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
++ { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON },
+ { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
+ { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
+ /* ??? Don't some v8 priviledged insns conflict with v9? */
+@@ -1640,9 +1643,8 @@
+ { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
+
+ /* sparclet specific insns */
+-
+-COMMUTEOP ("umac", 0x3e, sparclet),
+-COMMUTEOP ("smac", 0x3f, sparclet),
++COMMUTEOP ("umac", 0x3e, sparclet|MASK_LEON),
++COMMUTEOP ("smac", 0x3f, sparclet|MASK_LEON),
+ COMMUTEOP ("umacd", 0x2e, sparclet),
+ COMMUTEOP ("smacd", 0x2f, sparclet),
+ COMMUTEOP ("umuld", 0x09, sparclet),
+@@ -1693,8 +1695,8 @@
+ #undef SLCBCC2
+ #undef SLCBCC
+
+-{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
+-{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
++{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9|MASK_LEON },
++{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9|MASK_LEON },
+ { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
+ { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
+
+@@ -1704,8 +1706,8 @@
+ { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
+ { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
+ { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
+-{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
+-{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
++{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9|MASK_LEON }, /* casa [rs1]ASI_P,rs2,rd */
++{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9|MASK_LEON }, /* casa [rs1]ASI_P_L,rs2,rd */
+ { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
+ { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
+
diff --git a/patches/gcc/4.6.0/200-sparc-leon.patch b/patches/gcc/4.6.0/200-sparc-leon.patch
new file mode 100644
index 0000000..1d97105
--- /dev/null
+++ b/patches/gcc/4.6.0/200-sparc-leon.patch
@@ -0,0 +1,423 @@
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 39d9a19..6808f12 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -2524,12 +2524,13 @@ sh-wrs-vxworks)
+ ;;
+ sparc-*-elf*)
+ tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h sparc/sysv4.h sparc/sp-elf.h"
+- case ${target} in
++ leonver=`echo ${target} | sed -e "s/sparc-//" | sed -e 's/-.*$//' | sed -e 's/leon[3-9]/leon3/' `
++ case ${target} in
+ *-leon-*)
+- tmake_file="sparc/t-leon"
++ tmake_file="sparc/t-${leonver}"
+ ;;
+- *-leon[3-9]*)
+- tmake_file="sparc/t-leon3"
++ *-leon[3-9]*|*-sfleon*|*-hfleon*)
++ tmake_file="sparc/t-${leonver}"
+ ;;
+ *)
+ tmake_file="sparc/t-elf"
+@@ -2546,12 +2547,13 @@ sparc-*-rtems*)
+ sparc-*-linux*)
+ tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h"
+ extra_options="${extra_options} sparc/long-double-switch.opt"
++ leonver=`echo ${target} | sed -e "s/sparc-//" | sed -e 's/-.*$//' | sed -e 's/leon[3-9]/leon3/' `
+ case ${target} in
+ *-leon-*)
+- tmake_file="${tmake_file} sparc/t-leon"
++ tmake_file="${tmake_file} sparc/t-${leonver}"
+ ;;
+- *-leon[3-9]*)
+- tmake_file="${tmake_file} sparc/t-leon3"
++ *-leon[3-9]*|*-sfleon*|*-hfleon*)
++ tmake_file="${tmake_file} sparc/t-${leonver}"
+ ;;
+ *)
+ tmake_file="${tmake_file} sparc/t-linux"
+@@ -3043,8 +3045,13 @@ if test x$with_cpu = x ; then
+ mips*-*-vxworks)
+ with_arch=mips2
+ ;;
+- sparc-leon*-*)
+- with_cpu=v8;
++ sparc-sfleon*-*|sparc-hfleon*-*)
++ leonver=`echo ${target} | sed -e "s/sparc-//" | sed -e 's/-.*$//' | sed -e 's/leon[3-9]/leon/' `
++ with_cpu="${leonver}";
++ ;;
++ sparc-*leon*-*)
++ leonver=`echo ${target} | sed -e "s/sparc-//" | sed -e 's/-.*$//' | sed -e 's/leon[3-9]/leon/' `
++ with_cpu="${leonver}";
+ ;;
+ sparc*-*-*)
+ with_cpu="`echo ${target} | sed 's/-.*$//'`"
+@@ -3567,7 +3574,7 @@ case "${target}" in
+ case ${val} in
+ "" | sparc | sparcv9 | sparc64 \
+ | v7 | cypress \
+- | v8 | supersparc | hypersparc | leon \
++ | v8 | supersparc | hypersparc | *leon* \
+ | sparclite | f930 | f934 | sparclite86x \
+ | sparclet | tsc701 \
+ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2)
+@@ -3713,9 +3720,10 @@ case ${target} in
+ cxx_target_objs="${cxx_target_objs} sh-c.o"
+ ;;
+
+- sparc-leon*-*)
++ sparc-*leon*-*)
++ leonver=`echo ${target} | sed -e "s/sparc-//" | sed -e 's/-.*$//' | sed -e 's/leon[3-9]/leon/' `
+ if test x$with_tune = x ; then
+- with_tune=leon;
++ with_tune="${leonver}";
+ fi
+
+ # The SPARC port checks this value at compile-time.
+diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
+index 1c2ba93..5aadff6 100644
+--- a/gcc/config/sparc/sparc.c
++++ b/gcc/config/sparc/sparc.c
+@@ -497,7 +497,9 @@ enum processor_type sparc_cpu;
+
+ /* Whether an FPU option was specified. */
+ static bool fpu_option_set = false;
+-
++/* Weather -mv8 was specified. */
++static bool mv8_option_set = false;
++
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+ static const struct default_options sparc_option_optimization_table[] =
+ {
+@@ -690,6 +692,10 @@ sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+ fpu_option_set = true;
+ break;
+
++ case OPT_mv8:
++ mv8_option_set = true;
++ break;
++
+ case OPT_mcpu_:
+ sparc_select[1].string = arg;
+ break;
+@@ -739,6 +745,10 @@ sparc_option_override (void)
+ { TARGET_CPU_ultrasparc3, "ultrasparc3" },
+ { TARGET_CPU_niagara, "niagara" },
+ { TARGET_CPU_niagara2, "niagara2" },
++ { TARGET_CPU_sparchfleon, "hfleon" },
++ { TARGET_CPU_sparchfleonv8, "hfleonv8" },
++ { TARGET_CPU_sparcsfleon, "sfleon" },
++ { TARGET_CPU_sparcsfleonv8, "sfleonv8" },
+ { 0, 0 }
+ };
+ const struct cpu_default *def;
+@@ -756,8 +766,12 @@ sparc_option_override (void)
+ { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
+ { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
+ /* LEON */
+- { "leon", PROCESSOR_LEON, MASK_ISA, MASK_V8|MASK_FPU },
++ { "leon", PROCESSOR_LEON, MASK_ISA, MASK_FPU },
+ { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
++ { "hfleon", PROCESSOR_LEON, MASK_ISA, MASK_FPU },
++ { "hfleonv8", PROCESSOR_LEON, MASK_ISA & ~(MASK_V8), MASK_V8|MASK_FPU },
++ { "sfleon", PROCESSOR_LEON, MASK_ISA | MASK_FPU, 0 },
++ { "sfleonv8", PROCESSOR_LEON, (MASK_ISA | MASK_FPU) & ~(MASK_V8), MASK_V8 },
+ /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
+ { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
+ /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
+@@ -865,7 +879,9 @@ sparc_option_override (void)
+ the processor default. */
+ if (fpu_option_set)
+ target_flags = (target_flags & ~MASK_FPU) | fpu;
+-
++ if (mv8_option_set)
++ target_flags |= MASK_V8;
++
+ /* Don't allow -mvis if FPU is disabled. */
+ if (! TARGET_FPU)
+ target_flags &= ~MASK_VIS;
+diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
+index 297844f..5e28646 100644
+--- a/gcc/config/sparc/sparc.h
++++ b/gcc/config/sparc/sparc.h
+@@ -247,6 +247,10 @@ extern enum cmodel sparc_cmodel;
+ #define TARGET_CPU_ultrasparc3 10
+ #define TARGET_CPU_niagara 11
+ #define TARGET_CPU_niagara2 12
++#define TARGET_CPU_sparchfleon 13
++#define TARGET_CPU_sparchfleonv8 14
++#define TARGET_CPU_sparcsfleon 15
++#define TARGET_CPU_sparcsfleonv8 16
+
+ #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
+@@ -319,10 +323,31 @@ extern enum cmodel sparc_cmodel;
+ #endif
+
+ #if TARGET_CPU_DEFAULT == TARGET_CPU_leon
+-#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
+-#define ASM_CPU32_DEFAULT_SPEC ""
++#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ "
++#define ASM_CPU32_DEFAULT_SPEC "-Aleon"
++#endif
++
++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleon
++#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ "
++#define ASM_CPU32_DEFAULT_SPEC "-Aleon"
++#endif
++
++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleon
++#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D_SOFT_FLOAT"
++#define ASM_CPU32_DEFAULT_SPEC "-Aleon"
+ #endif
+
++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleonv8
++#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__ "
++#define ASM_CPU32_DEFAULT_SPEC "-Aleon"
++#endif
++
++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleonv8
++#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__ -D_SOFT_FLOAT"
++#define ASM_CPU32_DEFAULT_SPEC "-Aleon"
++#endif
++
++
+ #endif
+
+ #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
+@@ -368,12 +393,16 @@ extern enum cmodel sparc_cmodel;
+ %{mcpu=v8:-D__sparc_v8__} \
+ %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
+ %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
+-%{mcpu=leon:-D__leon__ -D__sparc_v8__} \
++%{mcpu=leon:-D__leon__ } \
+ %{mcpu=v9:-D__sparc_v9__} \
+ %{mcpu=ultrasparc:-D__sparc_v9__} \
+ %{mcpu=ultrasparc3:-D__sparc_v9__} \
+ %{mcpu=niagara:-D__sparc_v9__} \
+ %{mcpu=niagara2:-D__sparc_v9__} \
++%{mcpu=hfleon:-D__leon__} \
++%{mcpu=hfleonv8:-D__leon__ -D__sparc_v8__} \
++%{mcpu=sfleon:-D__leon__ -D_SOFT_FLOAT} \
++%{mcpu=sfleonv8:-D__leon__ -D_SOFT_FLOAT -D__sparc_v8__} \
+ %{!mcpu*:%(cpp_cpu_default)} \
+ "
+ #define CPP_ARCH32_SPEC ""
+@@ -409,6 +438,11 @@ extern enum cmodel sparc_cmodel;
+ %{mcpu=sparclite86x:-Asparclite} \
+ %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
+ %{mv8plus:-Av8plus} \
++%{mcpu=leon:-Aleon} \
++%{mcpu=hfleon:-Aleon} \
++%{mcpu=hfleonv8:-Aleon} \
++%{mcpu=sfleon:-Aleon} \
++%{mcpu=sfleonv8:-Aleon} \
+ %{mcpu=v9:-Av9} \
+ %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
+ %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
+diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
+index a97cad1..68afe28 100644
+--- a/gcc/config/sparc/sparc.opt
++++ b/gcc/config/sparc/sparc.opt
+@@ -115,8 +115,9 @@ Mask(SPARCLITE)
+ Mask(SPARCLET)
+ ;; Generate code for SPARClet
+
+-Mask(V8)
+-;; Generate code for SPARC-V8
++mv8
++Target Report Mask(V8)
++Generate code for SPARC-V8, use hardware smul/sdiv
+
+ Mask(V9)
+ ;; Generate code for SPARC-V9
+diff --git a/gcc/config/sparc/t-hfleon b/gcc/config/sparc/t-hfleon
+new file mode 100644
+index 0000000..192a502
+--- /dev/null
++++ b/gcc/config/sparc/t-hfleon
+@@ -0,0 +1,37 @@
++# Copyright (C) 2010 Free Software Foundation, Inc.
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3, or (at your option)
++# any later version.
++#
++# GCC is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3. If not see
++# <http://www.gnu.org/licenses/>.
++
++# We want fine grained libraries, so use the new code to build the
++# floating point emulation libraries.
++FPBIT = fp-bit.c
++DPBIT = dp-bit.c
++
++dp-bit.c: $(srcdir)/config/fp-bit.c
++ cat $(srcdir)/config/fp-bit.c > dp-bit.c
++
++fp-bit.c: $(srcdir)/config/fp-bit.c
++ echo '#define FLOAT' > fp-bit.c
++ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
++
++# Multilibs for LEON3
++#MULTILIB_OPTIONS = msoft-float
++#MULTILIB_DIRNAMES = soft
++#MULTILIB_MATCHES = msoft-float=mno-fpu
++
++LIBGCC = stmp-multilib
++INSTALL_LIBGCC = install-multilib
+diff --git a/gcc/config/sparc/t-hfleonv8 b/gcc/config/sparc/t-hfleonv8
+new file mode 100644
+index 0000000..192a502
+--- /dev/null
++++ b/gcc/config/sparc/t-hfleonv8
+@@ -0,0 +1,37 @@
++# Copyright (C) 2010 Free Software Foundation, Inc.
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3, or (at your option)
++# any later version.
++#
++# GCC is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3. If not see
++# <http://www.gnu.org/licenses/>.
++
++# We want fine grained libraries, so use the new code to build the
++# floating point emulation libraries.
++FPBIT = fp-bit.c
++DPBIT = dp-bit.c
++
++dp-bit.c: $(srcdir)/config/fp-bit.c
++ cat $(srcdir)/config/fp-bit.c > dp-bit.c
++
++fp-bit.c: $(srcdir)/config/fp-bit.c
++ echo '#define FLOAT' > fp-bit.c
++ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
++
++# Multilibs for LEON3
++#MULTILIB_OPTIONS = msoft-float
++#MULTILIB_DIRNAMES = soft
++#MULTILIB_MATCHES = msoft-float=mno-fpu
++
++LIBGCC = stmp-multilib
++INSTALL_LIBGCC = install-multilib
+diff --git a/gcc/config/sparc/t-leon3 b/gcc/config/sparc/t-leon3
+index ce57d16..2bb1621 100644
+--- a/gcc/config/sparc/t-leon3
++++ b/gcc/config/sparc/t-leon3
+@@ -29,9 +29,9 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
+ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+ # Multilibs for LEON3
+-MULTILIB_OPTIONS = msoft-float
+-MULTILIB_DIRNAMES = soft
+-MULTILIB_MATCHES = msoft-float=mno-fpu
++MULTILIB_OPTIONS = msoft-float mv8
++MULTILIB_DIRNAMES = soft v8
++MULTILIB_MATCHES = msoft-float=mno-fpu mv8=mcpu?v8
+
+ LIBGCC = stmp-multilib
+ INSTALL_LIBGCC = install-multilib
+diff --git a/gcc/config/sparc/t-sfleon b/gcc/config/sparc/t-sfleon
+new file mode 100644
+index 0000000..192a502
+--- /dev/null
++++ b/gcc/config/sparc/t-sfleon
+@@ -0,0 +1,37 @@
++# Copyright (C) 2010 Free Software Foundation, Inc.
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3, or (at your option)
++# any later version.
++#
++# GCC is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3. If not see
++# <http://www.gnu.org/licenses/>.
++
++# We want fine grained libraries, so use the new code to build the
++# floating point emulation libraries.
++FPBIT = fp-bit.c
++DPBIT = dp-bit.c
++
++dp-bit.c: $(srcdir)/config/fp-bit.c
++ cat $(srcdir)/config/fp-bit.c > dp-bit.c
++
++fp-bit.c: $(srcdir)/config/fp-bit.c
++ echo '#define FLOAT' > fp-bit.c
++ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
++
++# Multilibs for LEON3
++#MULTILIB_OPTIONS = msoft-float
++#MULTILIB_DIRNAMES = soft
++#MULTILIB_MATCHES = msoft-float=mno-fpu
++
++LIBGCC = stmp-multilib
++INSTALL_LIBGCC = install-multilib
+diff --git a/gcc/config/sparc/t-sfleonv8 b/gcc/config/sparc/t-sfleonv8
+new file mode 100644
+index 0000000..192a502
+--- /dev/null
++++ b/gcc/config/sparc/t-sfleonv8
+@@ -0,0 +1,37 @@
++# Copyright (C) 2010 Free Software Foundation, Inc.
++#
++# This file is part of GCC.
++#
++# GCC is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3, or (at your option)
++# any later version.
++#
++# GCC is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with GCC; see the file COPYING3. If not see
++# <http://www.gnu.org/licenses/>.
++
++# We want fine grained libraries, so use the new code to build the
++# floating point emulation libraries.
++FPBIT = fp-bit.c
++DPBIT = dp-bit.c
++
++dp-bit.c: $(srcdir)/config/fp-bit.c
++ cat $(srcdir)/config/fp-bit.c > dp-bit.c
++
++fp-bit.c: $(srcdir)/config/fp-bit.c
++ echo '#define FLOAT' > fp-bit.c
++ cat $(srcdir)/config/fp-bit.c >> fp-bit.c
++
++# Multilibs for LEON3
++#MULTILIB_OPTIONS = msoft-float
++#MULTILIB_DIRNAMES = soft
++#MULTILIB_MATCHES = msoft-float=mno-fpu
++
++LIBGCC = stmp-multilib
++INSTALL_LIBGCC = install-multilib
--
1.6.4.1
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