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Re: [PATCH] Cygwin: fegetenv() in winsup/cygwin/fenv.cc should not disable exceptions!
On 2018-08-03 12:39, Corinna Vinschen wrote:
On Aug 3 11:27, Houder wrote:
On 2018-08-03 09:36, Corinna Vinschen wrote:
[snip]
> In terms of x86_64, do we have to change the fenv stuff completely
> to use only SSE opcodes? Does that make sense at all?
Ho! I have to disappoint you here! I am not an expert at all.
Thanks all the same for your detailed description. A quick search in
glibc shows that x86_64 FP exceptions in fact work somewhat different
in
that it additionally reads and writes from the SSE control register,
e.g. sysdeps/x86_64/fpu/fesetenv.c:
__asm__ ("fnstenv %0\n"
"stmxcsr %1" : "=m" (*&temp), "=m" (*&temp.__mxcsr));
[...]
__asm__ ("fldenv %0\n"
"ldmxcsr %1" : : "m" (temp), "m" (temp.__mxcsr));
? ... uhm, this also happens in Korn's implementation (Cygwin). Only
Dave Korn verifies if SSE is present (does the machine have SSE?).
Both implementations both manage SSE and x87 FPU simultaneously.
For instance fetestexcept(), i.e. show me the status flags, return
status flag in SSE | status flag in x87 FPU
(bit-wise "OR" of both "status registers")
Both Korn and Jaeger try to hide that there are in fact two devices
that do "floating-point".
Can gcc generate code for both devices at the same time? Possibly!
Did it in case of my _tiny_ STC? ("double d = 1.0; long l = d + 0.4")
No (as far as I tell).
On Linux and Cygwin 64-bits, the SSE was used. On WoW the x87 FPU was
used.
As far as I tell, it is neither the machine nor "fenv" that devices
to switch from x87 FPU to SSE ...
Why gcc prefers x87 FPU in case of WoW, I cannot tell (Yes, I a bit
outspoken here; though that is my hypothesis).
Regards,
Henri
If you're still interested in this stuff, feel free to create more
patches :)
Thanks,
Corinna