Scheduler problem with MPC855T port

[khoffmann at mmm dot com]

Hello everybody,

I've got a problem with my attempts to port eCos to our MPC855T board:

I started with the FADS template (which I now know, was not the best idea) 
and got so far that I can access my RAM, my FLASH, the UARTs and the FEC 
(at least I can see the DHCP requests on the net).

When I compile the 'twothreads' example, I can find a bunch of threads in 
the internal threadlist, obviously everything fine, some 'SLEEPING', some 
'RUNNING'.

But after each thread has  run once, the processor is only looping  throug 
the main_idle_thread() and it's doing nothing else. The trace issues the 
following a short time before the endless 'loop' (where the 'loop' is 
probably triggered by an external interrupt).

TRACE: <2>[447]void Cyg_Mutex::unlock() return void
TRACE: <2>[709]void Cyg_Alarm::initialize() enter
TRACE: <2>[277]void Cyg_Counter::add_alarm() enter
TRACE: <2>[277]void Cyg_Counter::add_alarm() RETURNING UNSET!
TRACE: <2>[709]void Cyg_Alarm::initialize() RETURNING UNSET!
TRACE: <2>[351]static void Cyg_Thread::sleep() enter
TRACE: <2>[271]void Cyg_Scheduler_Implementation::rem_thread() enter
TRACE: <2>[271]void Cyg_Scheduler_Implementation::rem_thread() 
thread=0045de10
TRACE: <2>[325]void Cyg_Scheduler_Implementation::rem_thread() return void
TRACE: <2>[372]static void Cyg_Thread::sleep() return void
TRACE: <2>[741]void Cyg_ThreadQueue_Implementation::enqueue() enter
TRACE: <2>[741]void Cyg_ThreadQueue_Implementation::enqueue() 
thread=0045de10
TRACE: <2>[818]void Cyg_ThreadQueue_Implementation::enqueue() return void
TRACE: <2>[119]Cyg_Thread* Cyg_Scheduler_Implementation::schedule() enter
TRACE: <2>[192]Cyg_Thread* Cyg_Scheduler_Implementation::schedule() 
returning thread 00419070
TRACE: <2>[87]static void Cyg_HardwareThread::thread_entry() enter
TRACE: <1>[1239]void idle_thread_main() enter
TBSCR 0001, vec 15: sivec 3c000000, simask 10010000, sipend 40020000
TBSCR 0001, vec 15: sivec 3c000000, simask 10010000, sipend 40020000
TBSCR 0001, vec 15: sivec 3c000000, simask 10010000, sipend 40000000
TBSCR 0001, vec 15: sivec 3c000000, simask 10010000, sipend 40020000
TBSCR 0001, vec 15: sivec 3c000000, simask 10010000, sipend 40000000
... ad infinitum ...

I probably missed something, but what?

Any help is appreciated!

With kind regards,

Karsten Hoffmann

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