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RE: GDB stubs / MIPS ISA I


> Jurica> breakpoint. So, it seems that debugged program is always on
> Jurica> the first breakpoint and it is not possible to step through
> Jurica> the rest of the code.
>
> Could be that caches are not handled properly, so when the stub tries
> to single step it hits the existing breakpoint.
>

In fact, this is true. I looked at cache invalidation code for about hundred
times, but didn't see anything suspicious...
It was a stupid bug. Now it seems that GDB stubs works fine. Thanks a lot.


> Jurica> P.S.  If you are interested in compatibility problems I found
> Jurica> in '/mips/arch/...'  I can say that they are related to not
> Jurica> respecting the MIPS ISA I load delay slot.
> [snip]
> Jurica> What is the best way to avoid this kind of incompatibilities?
>
> Something for Nick to reply to - but I suspect it's due to all the
> existing MIPS variants introduce delays in hardware if the register
> content is not ready when attempted used.

[Excerpt taken from IDT MIPS Microprocessor Family Software Reference
Manual, Page 152]

+ Load delay:
The MIPS-I ISA requires a load delay slot to be explicitly attended to by
the software. Later ISAs automatically interlock. In any case, compiler
software and programmers both attempt to fill the delay slot with
non-dependent instructions.

[End of excerpt]


> If you send a patch with MIPS I compatibility fixes, I'm sure they
> would be accepted almost immediately.

No problem. This should be easy, since load delay slot is the only issue to
be solved. However, I would like to test thoroughly 'full' eCos (not only
the stubs) on my MIPS board. Thereupon, I could send a patch.

Regards,
Jura.



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