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MIPS R3000 patch for MIPS arch
- To: ecos-discuss at sourceware dot cygnus dot com
- Subject: [ECOS] MIPS R3000 patch for MIPS arch
- From: sun409 at pchome dot com dot tw
- Date: 1 Jun 2000 13:21:29 -0000
The attach is the patch file for MIPS architecture to
make the source codes in hal/mips/arch/ directory comply
with MIPS I ISA.
There are mainly two kinds of modification:
1. Add a delay slot after lw insn.
2. Change non-MIPS I insn. to equiv. MIPS I insn.
I hope you in Cygnus could accept this patch.
And, any further modification to the hal/mips/arch/
will not use instructions other than MIPS I.
Regards,
Tim Ouyang
_________________________________________________________
pchome 免費電子信箱,申請請至: http://www.pchome.com.tw
diff -Naur eCos-orig/packages/hal/mips/arch/current/include/arch.inc eCos/packages/hal/mips/arch/current/include/arch.inc
--- eCos-orig/packages/hal/mips/arch/current/include/arch.inc Mon May 29 01:32:19 2000
+++ eCos/packages/hal/mips/arch/current/include/arch.inc Mon May 29 17:27:55 2000
@@ -249,6 +249,13 @@
jr \pc # jump back to interrupted code
rfe # restore state (delay slot)
.endm
+#elif defined(CYG_HAL_MIPS_R3000A)
+ .macro hal_cpu_eret pc,sr
+ mtc0 \sr,status # Load status register
+ nop
+ jr \pc # jump back to interrupted code
+ rfe # restore state (delay slot)
+ .endm
#else
.macro hal_cpu_eret pc,sr
.set mips3
@@ -300,6 +307,7 @@
la v1,hal_intc_translation_table
add v0,v0,v1 # index into table
lb \vnum,0(v0) # pick up vector number
+ nop # sun409@pchome.com.tw added
.endm
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
diff -Naur eCos-orig/packages/hal/mips/arch/current/include/hal_intr.h eCos/packages/hal/mips/arch/current/include/hal_intr.h
--- eCos-orig/packages/hal/mips/arch/current/include/hal_intr.h Fri May 19 20:47:54 2000
+++ eCos/packages/hal/mips/arch/current/include/hal_intr.h Mon May 29 17:27:55 2000
@@ -227,6 +227,7 @@
asm volatile ( \
"mfc0 $8,$12; nop;" \
"and %0,%0,0x1;" \
+ "and $8,$8,0XFFFFFFFE;" \
"or $8,$8,%0;" \
"mtc0 $8,$12;" \
"nop; nop; nop;" \
diff -Naur eCos-orig/packages/hal/mips/arch/current/src/context.S eCos/packages/hal/mips/arch/current/src/context.S
--- eCos-orig/packages/hal/mips/arch/current/src/context.S Tue Mar 28 22:11:26 2000
+++ eCos/packages/hal/mips/arch/current/src/context.S Mon May 29 17:27:55 2000
@@ -117,6 +117,7 @@
ssp t0,sp
mfc0 t1,status # Save status register
+ nop # sun409@pchome.com.tw added
sw t1,mipsreg_sr(sp)
sw sp,0(a1) # save sp in save loc
@@ -135,7 +136,8 @@
hal_thread_load_context:
lw sp,0(a0) # load new SP directly
-
+ nop # sun409@pchome.com.tw added
+
#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
hal_fpu_load_caller sp
diff -Naur eCos-orig/packages/hal/mips/arch/current/src/vectors.S eCos/packages/hal/mips/arch/current/src/vectors.S
--- eCos-orig/packages/hal/mips/arch/current/src/vectors.S Mon May 29 01:32:25 2000
+++ eCos/packages/hal/mips/arch/current/src/vectors.S Wed May 31 14:20:51 2000
@@ -105,6 +105,7 @@
la k0,32
la k1,hal_vsr_table # Get VSR table
lw k1,32*4(k1) # load debug vector
+ nop # sun409@pchome.com.tw added
jr k1 # go there
nop # (delay slot)
FUNC_END(debug_vector)
@@ -120,6 +121,7 @@
la k1,hal_vsr_table # address of VSR table
add k1,k1,k0 # offset of VSR entry
lw k1,0(k1) # k1 = pointer to VSR
+ nop # sun409@pchome.com.tw added
jr k1 # go there
nop # (delay slot)
@@ -131,6 +133,7 @@
la k0,33
la k1,hal_vsr_table # Get VSR table
lw k1,33*4(k1) # load utlb vector
+ nop # sun409@pchome.com.tw added
jr k1 # go there
nop # (delay slot)
FUNC_END(utlb_vector)
@@ -281,6 +284,7 @@
la k0,34*4
la k1,hal_vsr_table # Get VSR table
lw k1,34*4(k1) # load NMI vector
+ nop # sun409@pchome.com.tw added
jr k1 # go there
nop # (delay slot)
@@ -482,6 +486,7 @@
.extern cyg_scheduler_sched_lock
la v0,cyg_scheduler_sched_lock
lw a0,0(v0)
+ nop # sun409@pchome.com.tw added
addi a0,a0,1
sw a0,0(v0)
#endif
@@ -575,6 +580,7 @@
lw sp,mips_stack_frame_size(sp) # sp = *sp
+ nop # sun409@pchome.com.tw added
subu sp,sp,mips_stack_frame_size # make a null frame
#endif
@@ -733,6 +739,7 @@
nop
lw a0,24(sp) # get status reg
+ nop # sun409@pchome.com.tw added
hal_cpu_int_merge a0 # merge with current SR
@@ -763,8 +770,9 @@
FUNC_START(__break_vsr_springboard)
mfc0 k0,epc
mfc0 k1,cause
- bltzl k1,1f
- addi k0,k0,4 # delay slot (only executed if BD set)
+ bgez k1,1f # sun409@pchome.com.tw modified
+ nop
+ addi k0,k0,4 # only executed if BD set
1: lw k1,0(k0) # get break instruction
la k0,0x0007000d # break 0x7 used by GCC for d-b-z
bne k0,k1,2f
@@ -773,6 +781,7 @@
la k1,hal_vsr_table # address of VSR table
add k1,k1,k0 # offset of VSR entry
lw k1,0(k1) # k1 = pointer to VSR
+ nop # sun409@pchome.com.tw added
jr k1 # go there
nop # (delay slot)
2: ori k0,$0,9*4 # CYGNUM_HAL_VECTOR_BREAKPOINT