Re: [ECOS] How to access PCI memory(HELP)....

["Ling Su" <lingsu at palmmicro dot com>]

Nick wrote,
>
> PCI_IOSPACE_BASE only maps PCI device IO registers, not memory
> mappings. I don't believe we actually use any of these mappings, which
> appear at 0x0C000000/0xAC000000 physical/logical addresses.
>
> We also use the master address windows. Window one is set up to map
> the 4372 control registers at 0x1C000000 in PCI space to
> 0x1C000000/0xBC000000 in the CPU. Window 2 maps 0x80000000 in PCI
> space to 0x80000000 physical which the MMU remaps to 0xC0000000
> logical. However, the 4372 also occupies the first 256Mb of this.
>
[Ling]
You mean the south bridge chip also occupies 256MB space? Where I can find
this information? I didn't quite understand the MMU inialization part now, I
have to read the vr4300 manual to catch it. I agree that the part on PCI
address windows, you mean the first register is for mapping 4372 registers,
so the second register windows set for memory space on PCI bus, right?

> So, if my reading of the code and documentation is correct, then
> HAL_PCI_PHYSICAL_MEMORY_BASE should be 0xD0000000, to skip the first
> 256Mb, and HAL_PCI_ALLOC_BASE_MEMORY should be 0x90000000. You should
> then be able to access PCI device memory from 0xD0000000.
>

Why need I set HAL_PCI_ALLOC_BASE_MEMORY to 0x90000000, originally it is
0x0, which means mapp the memory from the beginning, what is the rational to
add a 0x9000_0000 offset?

> Of course currently the MMU only maps the first 256Mb of PCI space at
> 0xC0000000, so the MMU mapping needs to be extended. The simplest way
> to do this is to increase NUMB_PG in platform.S from 8 to 16. The
> current code appears to only use 16 of the 32 TLB entries, so using
> all 32 will give 512Mb of mapped PCI memory.
>
>
> Ling Su, please give this a try and if it works we can put these
> values into the standard sources.
>

Nick, I follow your suggestion, basically I changed three things,
(1). HAL_PCI_PHYSICAL_MEMORY_BASE set to 0xD0000000
(2). HAL_PCI_ALLOC_BASE_MEMORY set to 0x90000000
(3). increase NUMB_PG to 16

Unfortunately it doesn't work, I append the the log in the end of this
message, what causes a SIGSEGV signal ususally?

Any other suggestions? Thanks a lot!

Regards,
-Ling

============================================
(gdb) set remotebaud 38400
(gdb) target remote /dev/ttyS0
Remote debugging using /dev/ttyS0
0x80003a50 in ?? ()
(gdb) load
Loading section .rom_vectors, size 0xb4 lma 0x80100000
Loading section .text, size 0xd9b0 lma 0x801000b4
Loading section .ctors, size 0x28 lma 0x8010da64
Loading section .dtors, size 0x14 lma 0x8010da8c
Loading section .rodata, size 0x9cc lma 0x8010daa0
Loading section .data, size 0x473c lma 0x8010e470
Start address 0x801000a4 , load size 76712
Transfer rate: 27895 bits/sec, 501 bytes/write.
(gdb) cont
Continuing.
Found device on bus 0, devfn 0x10:
 Device configuration succeeded
 **** Device IO and MEM access enabled
 Vendor    0x1688
 Device    0x8888
 Command   0x0000, Status 0x0280
 Class/Rev 0x07800001
 Header 0x11FF0F
 SubVendor 0x1111, Sub ID 0xFF1A
 BAR[0]    0x09000000 / probed size 0xFFF00000 / CPU addr 0xD9000000
 BAR[1]    0x00000000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF
 BAR[2]    0x00000000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF
 BAR[3]    0x00000000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF
 BAR[4]    0x00000000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF
 BAR[5]    0x00000000 / probed size 0x00000000 / CPU addr 0xFFFFFFFF
 Wired to HAL vector 13
Current pci base is D9000000
[New thread 3]

Program received signal SIGSEGV, Segmentation fault.
[Switching to thread 3]
0x80100bb8 in pci_test () at pcitest.c:293
293     (*(pci_base + 0x004)) = 0x0000;
Current language:  auto; currently c
(gdb)