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Re: context switching in ecos


>>>>> "Suet" == Suet Fei Li <suetfei@bwrc.eecs.berkeley.edu> writes:
Suet> It seems to me that the current status of the CPU has to be
Suet> saved twice (once right after the interrupt, the second time
Suet> during HAL_THREAD_SWITCH_CONTEXT ). If this is indeed true,
Suet> isn't it rather inefficient? Why did not it just:

Suet> interrupt -> save everything on the current thread -> scheduler
Suet> -> load the context from next thread.

What should happen is that in the VSR all registers that are marked
volatile on calls should be saved. The context switch function should
only save non-volatile registers.

On some architectures, however, there's no (or little) distinction
between the two sets. x86 is probably the worst architecture in this
regard, while most RISC architectures will have two destinct sets.

Jesper

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