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Re: setting up RAM on AEB
- To: ecos <ecos-discuss at sourceware dot cygnus dot com>, ecos <ecos-discuss at sourceware dot cygnus dot com>
- Subject: Re: [ECOS] setting up RAM on AEB
- From: Ormund Williams <ormundw at brainlink dot com>
- Date: Wed, 01 Nov 2000 00:48:17 -0500
- Organization: Ormlab
- References: <2253171AF143D21185A60000F8FA748B0229AA6C@pluto.combitech.se>
Andreas.Karlsson@combitechsystems.com wrote:
>
> Hi,
>
> I have extended my AEB board to use more memory. It took I while to figure
> out that whatever I set the values to in hal_platform_setup.h they will do
> nothing, even if I comment the lines away nothing will happen.
>
> I'm changing in the sources and doing make clean, compiling and then linking
> with the new install-files.
>
> To avoid collision with the AEB_BAD region I have to override its values in
> BANK3 and define my new memory in this BANK to be able to test the memory.
>
> My question is where, in which file, does eCos specify the size and location
> of SRAM?
>
> When expanding the memory I have to set which 'chip enable' pins the new
> memory bank should use, I just can't find out where eCos specify this for
> memory-BANK2 which is used by eCos, I have seen in memory that eCos sets
> this to 0x900C, but where?
>
> Thanks
>
> Andreas
Hi Andreas
I have just finished building a board I designed that uses the LH77790
and porting eCos, it works so don't be discouraged.
I started with the AEB port, first modifying it to run stand-alone (Do
you have an EPROM programmer so that you can erase the Flash chip and
burn your own gdb-stub?) the following are the steps I took:
1. Added new ARM package and target to
.../ecos/ecos-1.3.1/packages/ecos.db
2. Copy AEB directory tree and change all occurrences of aeb to new
target name. (in my case awt60)
3. Edit
.../ecos/ecos-1.3.1/packages/hal/arm/awt60/v1_3_1/cdl/hal_arm_awt60.cdl
- mostly removing "rev B/C" stuff and changing cdl_option
CYGBLD_BUILD_GDB_STUBS.
4. Mostly name changes to the files in
.../ecos/ecos-1.3.1/packages/hal/arm/awt60/v1_3_1/src
5. Here is how I rewrote hal_platform_setup.h:
---------start------------
#if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
// Override default to a more sensible value
#undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
#endif
// AWT60 has 2MB DRAM, 2/4MB of Flash ROM, 8KB battery backed SRAM+Clock
// and 4KB on-chip SRAM. The cache is broken(LH77790A).
// Move Flash-1 to 0x04000000 segment-1, CE0
// Move Flash-2 to 0x04020000 segment-2, CE1
// Move BBRAM+C to 0x05000000 segment-3, CE4
// On-chip SRAM at 0x60000000 default segment, Cache in SRAM mode at
0x60000800
// Place DRAM at 0x00000000 segment-6, CE2-3
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
#define
PLATFORM_SETUP1 \
ldr
r1,bcr1 ;\
ldr
r2,bcr1+4 ;\
str
r2,[r1] ;\
ldr
r1,sdr1 ;\
ldr
r2,sdr1+4 ;\
str
r2,[r1] ;\
ldr
r1,stop1 ;\
ldr
r2,stop1+4 ;\
str
r2,[r1] ;\
ldr
r1,start1 ;\
ldr
r2,start1+4 ;\
str
r2,[r1] ;\
ldr pc,=NewROM /* Set the Program Counter to New
address */ ;\
mov r0,r1 /* Nop
*/ ;\
mov r0,r1 /* Nop
*/ ;\
;\
NewROM: ldr
r0,=SRStart ;\
SRLoop: ldr
r1,[r0],#4 ;\
ldr
r2,[r0],#4 ;\
str r2,[r1] ;\
cmp r1,#0
;\
bne SRLoop ;\
b
SetupEnd ;\
;\
bcr1: .long 0xFFFFA104,0x00001003 /* Flash1,8bit,2wait-state,CE0
*/ ;\
sdr1: .long 0xFFFFA044,0x00007802 /* S-r/w U-r/w Noncacheable
*/ ;\
start1: .long
0xFFFFA004,0x04000000 ;\
stop1: .long
0xFFFFA024,0x04200000 ;\
SRStart:
;\
bcr2: .long 0xFFFFA108,0x0000100C /* Flash2,8bit,3wait-state,CE1
*/ ;\
sdr2: .long 0xFFFFA048,0x00007804 /* S-r/w U-r/w Noncacheable
*/ ;\
start2: .long
0xFFFFA008,0x04200000 ;\
stop2: .long
0xFFFFA028,0x04400000 ;\
bcr3: .long 0xFFFFA10C,0x00001300 /* BBRAM+Ck,8bit,1 wait-state,CE4
*/ ;\
sdr3: .long 0xFFFFA04C,0x00007808 /* S-r/w U-r/w Noncacheable
*/ ;\
start3: .long
0xFFFFA00C,0x03000000 ;\
stop3: .long
0xFFFFA02C,0x03002000 ;\
bcr4: .long 0xFFFFA110,0x00000000 /* Bad address
*/ ;\
sdr4: .long 0xFFFFA050,0x00007808 /* No access
*/ ;\
start4: .long
0xFFFFA010,0x00200000 ;\
stop4: .long
0xFFFFA030,0x03000000 ;\
bcr6a: .long 0xFFFFA118,0x00009090 /* DRAM 16bit FCAS 1.5 CE2-3
*/ ;\
bcr6b: .long 0xFFFFA120,0x00000033 /* BCAS 1.5,Refresh,1K page,Page
mode */ ;\
sdr6: .long 0xFFFFA058,0x00007840 /* S-r/w U-r/w Noncacheable
*/ ;\
start6: .long
0xFFFFA018,0x00000000 ;\
stop6: .long
0xFFFFA038,0x00200000 ;\
drr: .long 0xFFFFA128,0x00000730 /* DRAM Refresh 1840
*/ ;\
sdr8: .long 0xFFFFA060,0x00007801 /* On-Chip:RAM,Config Reg,I/O
*/ ;\
ccr: .long 0xFFFFA400,0x00000002 /* Cache in SRAM mode
*/ ;\
lscr: .long 0xFFFFA404,0x00000003 /* On-Chip SRAM at 0x60000000
*/ ;\
ppctlr: .long 0xFFFF1C0C,0x00000082 /* Port A and C output, B input
*/ ;\
SREnd: .long
0x00000000 ;\
;\
.balign
4 ;\
SetupEnd:
;
#else
#define PLATFORM_SETUP1
#endif
---------stop----------
6. This is the contents of mlt_arm_awt60_rom.h:
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
#define CYGMEM_REGION_ram (0x00000000)
#define CYGMEM_REGION_ram_SIZE (0x00200000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R |
CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0x04000000)
#define CYGMEM_REGION_rom_SIZE (0x00200000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
extern char CYG_LABEL_NAME (_reserved_vectors) [];
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME
(_reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x1000)
extern char CYG_LABEL_NAME (_reserved_not_mapped) [];
#define CYGMEM_SECTION_reserved_not_mapped (CYG_LABEL_NAME
(_reserved_not_mapped))
#define CYGMEM_SECTION_reserved_not_mapped_SIZE (0x7000)
If you want to build a stand-alone gdb-stub for your modified AEB I can
send you the other files I have.
One other thing, a warning; the AEB has a poor reset circuit and even if
the processor seems to be executing properly, some of the on board
peripherals; DRAM controller, UARTs; will not function correctly. This
wasted a lot of my time, looking for nonexistent errors in my setup
code. A work-around for that, when ever you reset or power up the AEB,
connect with gdb send a "kill" signal and then reconnect then you can
"load" and debug your code.
--
Ormund