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Re: Bug in PPC 405 target.



On 04-May-2001 Sergio Nunes wrote:
> 
> 
> 
> No I wasn't aware there was a ppc40x port in place. I downloaded the eCos v1_3_
> 1 which doesn't have a ppc40x port. Is the ppc40x on the ftp site?
> 

Yes, via anon CVS.

1.3.1 is terribly old - more than a year.  Only the CVS is [currently] up to date.

> Sergio
> 
> 
> 
> 
> 
> Gary Thomas <gthomas@cambridge.redhat.com>@sources.redhat.com on 05/04/2001
> 11:44:10 AM
> 
> Sent by:  ecos-discuss-owner@sources.redhat.com
> 
> 
> To:   Sergio Nunes <snunes@Celestica.com>
> cc:   ecos-discuss@sources.redhat.com
> 
> Subject:  Re: [ECOS] Bug in PPC 405 target.
> 
> 
> 
> On 04-May-2001 Sergio Nunes wrote:
>>
>>
>>
>> Dennis,
>>
>> I'm tinkering with a port of eCos to PPC405CR. Currently, I've managed to
>> workaround this problem by using RiscWatch to preset my registers (including
>> EVPR) to the correct values and run my compiled code from RAM. The proper
>> location for this type of initialization is either in hal_cpu_init (in
>> variant.inc) or hal_hardware_int (at platform level). Both of these
>> functions/macros are called from vectors.s
>>
>> Another change that is needed to port existing PPC HALs to PPC405 family is
> the
>> code support for the (Programmable Interrupt Timer - PIT), since the 405
> family
>> does not provide the decrementer functionality.  You'll need to change this if
>> you hope to do any task switching. I have this working with some success,
>> although it's not fully debugged.
>>
>> There is some variant specific code currently at the archecetiture level of
> the
>> PowerPC HAL. Not sure you can completely avoid changing archictecture files,
>> since 405 family does vary somewhat from base PowerPC arctecture. However you
>> should be able to keep changes to a minimal.
>>
>> Sergio
> 
> Are you using the ppc40x variant code?   The PIT stuff should be handled
> properly already.  Also the setup for the EVPR is in there.
> 
>>
>>
>>
>>
>>
>>
>> "Dennis Ehlin (ECS)" <Dennis.Ehlin@ecs.ericsson.se>@sources.redhat.com on
>> 05/04/2001 11:06:17 AM
>>
>> Sent by:  ecos-discuss-owner@sources.redhat.com
>>
>>
>> To:   ecos-discuss@sources.redhat.com
>> cc:
>>
>> Subject:  [ECOS] Bug in PPC 405 target.
>>
>>
>> Hi,
>>
>> The option "CYGHWR_HAL_POWERPC_VECTOR_BASE  (0xfff00000 or 0x00000000)"
>> doesn't work as intended on the PPC405GP and (i think also the PPC403).
>>
>> Because the MSR_IP bit is not valid for changing the exception vector offset
>> (The IP_BIT is actually marked as reserved in the MSR register).
>> Instead the EVPR register should be used.
>>
>> It would be great if I could fix this, but I'm not sure how to tackle the
>> problem, because if I change something in the
>> "powerpc/arch/current/src/vectors.S" file the changes will affect all PPC
>> targets, and that is not what I want, and
>> also the cdl file for the PPC arch needs to be changed to allow setting of
> other
>> exception vector offsets than 0x00000000 and 0xfff00000 for the PPC40x
> targets.
>>
>> "User's Manual page 95"
>>
>> 23:25 Reserved
>>
>> "User's Manual page 884"
>> EVPR
>>
>> Exception Vector Prefix Register
>>
>> SPR 0x3D6
>>
>> See "Exception Vector Prefix Register (EVPR)" on page 10-30.
>>
>> Figure 25-13. Exception Vector Prefix Register (EVPR)
>>
>> 0:15 EVP Exception Vector Prefix 16:31 Reserved
>>
>> //Dennis
>>
>>
> 


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