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RE: cyg_drv_interrupt_create ()



> > interrupt table. The ARM processor only has one IRQ and one
> > FIQ pin and on most boards these lines are connected to an
> > interrupt controller (this may be part of a chip with an
>
>I'm counting three interrupt lines, and an FIQ line myself.  Does this
>most likely mean that I will have to add the handling for the interrupt
>that I'm using?

The CL-EP7312 has (at a quick count) 22 interrupt sources; five are routed 
to FIQ (EXTFIQ pin, battery low, watchdog, media change [pin], and DAI) and 
the remainder are routed to IRQ (CODEC, the three EINT pins, TC1 underflow, 
TC2 underflow, real-time alarm, 64Hz tick, UART1 Tx FIFO empty, UART1 Rx 
FIFO full, UART1 status change, SSI1 end of transfer, key press (PORTA 
activity), SSI 16-byte Rx, SSI 16-byte Tx, UART2 Tx FIFO empty, UART2 Rx 
FIFO full).

Refer to pp.22-23 of the EP7312 User's Manual (DS608UM1) and vectors.s, 
which [must] be reading the INTSR1/INTSR2/INTSR3 registers and routing 
incoming IRQs and FIQs appropriately.

>What's a hardware debugger?  Doesn't sound like I want to get into using
>a hardware debugger.

In the context of the 7312, a JTAG debugger.


-- Lewin A.R.W. Edwards
Embedded Engineer, Digi-Frame Inc.
Work: http://www.digi-frame.com/
Tel (914) 937-4090 9am-6:30pm M-F ET
Personal: http://www.larwe.com/ http://www.zws.com/

"Far better it is to dare mighty things, to win glorious triumphs, even 
though checkered by failure, than to rank with those poor spirits who 
neither enjoy much nor suffer much, because they live in the gray twilight 
that knows not victory nor defeat."
(Theodore Roosevelt)


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