[ECOS] EP7211 bug? (slightly off topic but relevant)

["Trenton D. Adams" <tadams at extremeeng dot com>]

I think there's a bug in the Cirrus logic EP7211 CPU.
Board EDB7111-2 RevB.

Has anyone seen this occur before?

SSI1 does not work correctly.
First of all, the ADCCKNSEN bit in SYSCON3 says that data is transmitted
on rising edge if the bit is set, and falling edge if it's cleared.
>From what our logic analyzer says it's rising edge when it's cleared,
and falling edge when it's set.

Second, sometimes the lower 3 bits sent out on SSI1 don't even last for
half a clock.  If the interface is set to rising edge (ADCCKNSEN not
set), lower bits sometimes don't quite reach the rising edge of the
clock in which case the other end may not receive those bits properly
depending on what type of data latching they are using.  This phenomenon
is not random or irregular.  It completely depends on how bits are set
above each of the lower 3 bits.  In some cases, the lower 3 bits aren't
even shown at all on the logic analyzer.  There seems to never be more
than one bit that is screwed up.  Some examples are below.

Values of 0x0-0x5, 0000b-0101b don't even show up on the logic analyzer
at all.
0x6, 0110b shows up as 01*0 with bit * representing a bit that shows as
less than half a clock.


Some more binary values are below.  Again, * represents bits that are
less than 1/2 a clock.

000001*0
0000011*
0010011*
0100011*
1000011*
10010111
1010011*
10110111
1100011*
11010111
1110011*
11110111

Another interesting thing you might notice is that when bit 4 is set,
none of the lower 3 bits are 1/2 clocks.  It seems like a bug to me.  If
there was a setting to allow this to happen, that would seem extremely
weird to me.

Any other reports of this?

Some sample code to try it for your self is attached.  JP13 and JP10
have required header hookups for the logic analyzer for SSI1.

We disconnected DIN, DOUT, and SCLK on the Maxim ADC on the board to see
how that would affect it.  It didn't change a thing.


Trenton D. Adams
Extreme Engineering
#17, 6025 - 12 St. SE
Calgary, Alberta, Canada
T2H 2K1

Phone: 403 640 9494 ext-208
Fax: 403 640 9599

http://www.extremeeng.com

Makefile

eeprom.h

eeprom.c