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mistake in Altera Excalibur Port?
- From: "Qiang Huang" <jameshq at liverpool dot ac dot uk>
- To: "Ecos-Discuss" <ecos-discuss at sources dot redhat dot com>
- Date: Thu, 23 Jan 2003 15:54:37 -0000
- Subject: [ECOS] mistake in Altera Excalibur Port?
Hi:
In the code hal_platform_setup.h where setting the PLL clocks as:
// PLL Registers Addresses
2: .long EXCALIBUR_CLK_BASE+_CLK_PLL1_KCNT
.long EXCALIBUR_CLK_BASE+_CLK_PLL1_MCNT
.long EXCALIBUR_CLK_BASE+_CLK_PLL1_NCNT
.long EXCALIBUR_CLK_BASE+_CLK_PLL2_KCNT
.long EXCALIBUR_CLK_BASE+_CLK_PLL2_MCNT
.long EXCALIBUR_CLK_BASE+_CLK_PLL2_NCNT
// PLL Registers Values ensure this follows on from the
// addresses the code depends on it
.long 0x40000 // CLK_PLL1_KCNT_VAL = 1
.long 0x20101 // CLK_PLL1_MCNT_VAL = 2
.long 0x40000 // CLK_PLL1_NCNT_VAL = 1
.long 0x40000 // CLK_PLL2_KCNT_VAL = 1
.long 0x20303 // CLK_PLL2_MCNT_VAL = 6
.long 0x40000 // CLK_PLL2_NCNT_VAL = 1
actually the AHB1 is operating at 150MHz(derived from PLL1 after divided by
2) , but according the value specified above for PLL1
Ref. 50MHz --> F(AHB1) = ( 50*M / (N*K) ) / 2 = ( 50*2 / (1*1) ) / 2 = 50MHz
(CPU) , F(AHB2) = ( 50*M / (N*K) ) / 2 = ( 50*6/1*1)/2 = 150MHz for SDRAM.
so why the AHB1(CPU) is 50MHz, AHB2(SDRAM) is 150MHz here why not the value
150MHz and 75MHz spcified in the *.cdl file , am I wrong here? thanks
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