This is the mail archive of the
ecos-discuss@sources.redhat.com
mailing list for the eCos project.
hal/powerpc/arch/current/src/vectors.S
- From: Bob Koninckx <bob dot koninckx at mech dot kuleuven dot ac dot be>
- To: ecos-discuss at sources dot redhat dot com
- Date: Mon, 27 Oct 2003 23:25:43 +0100
- Subject: [ECOS] hal/powerpc/arch/current/src/vectors.S
- Organization: KULeuven
- Reply-to: bob dot koninckx at mech dot kuleuven dot ac dot be
Hi,
Apparently, the following few lines in default interrupt and exception
vsr of the powerpc architecture have been made conditional. That is,
lines 474 and following
# Enable MMU.
lwi r3,CYG_MSR
sync
mtmsr r3
sync
have been changed to
#ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
# Enable MMU.
lwi r3,CYG_MSR
sync
mtmsr r3
sync
#endif
I think this is not correct, since the CYG_MSR macro holds more
information than just enabling / disabling of the MMU. On the mpc555, it
is also used to enable / disable the floating point unit. This
particular processor does not have an MMU. As a consequence, the now
made conditional code is no longer included in the build. The first
interrupt therefore causes a floating point unavail exception as soon as
the floating point registers are stached away.
Bob
--
----------------------------------------------------------------------
ir. Bob Koninckx
Katholieke Universiteit Leuven
Division Production Engineering, tel. +32 16 322535
Machine Design and Automation fax. +32 16 322987
Celestijnenlaan 300B bob.koninckx@mech.kuleuven.ac.be
B-3001 Leuven Belgium http://www.mech.kuleuven.ac.be/pma
----------------------------------------------------------------------
--
Before posting, please read the FAQ: http://sources.redhat.com/fom/ecos
and search the list archive: http://sources.redhat.com/ml/ecos-discuss