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Serial Driver Performance Tuning


Hi,

I am writing a serial driver which support block transfer for ARM.  The baud rate can be 57600 when I layout whole system in SRAM on demo board.  But the destination board is only have 8K or 32K SRAM ( and 2M DRAM).  I must layout most of system on DRAM.  The baud rate only can be 19200 in this case.  I try to layout the serial DSR and ISR in the size limited SRAM, but the serial DSR performance only increase about 10%.  I also try to layout some parts of kernel in SRAM.  But the address of SRAM and DRAM is 0x00000000 and 0xd0000000.  This cause the "b" instrument can not be used on ARM when code in SRAM call function in DRAM, and vice versa.  But kernel is C++ program.  gcc always generate "b" instrument for global object constructor no matter if long call compiler option is used.  My questions are:

1.  Is there other way to increase the performance to support baud rate 57600 ?
3.  What codes are layout in SRAM can increase performance of overall serial DSR dramatically.
2.  Is there any clean way to layout kernel in SRAM.

Thanks for your attention.
Haibo Tang

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