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HAL_INTERRUPT_ACKNOWLEDGE on mips
- From: "Andy Dyer" <adyer at righthandtech dot com>
- To: <ecos-discuss at ecos dot sourceware dot org>
- Date: Tue, 24 Feb 2004 14:38:12 -0600
- Subject: [ECOS] HAL_INTERRUPT_ACKNOWLEDGE on mips
looking in hal/mips/arch/current/include/hal_intr.h
I see the generic implementation of HAL_INTERRUPT_ACKNOWLEDGE
for mips tries to write back into the Cause register
(CP0 register $13), presumably to clear the IP[7:2]
bits.
All of the books I have handy say that the only fields
in that register that are writable are IP[1:0]
(sometimes used to allow s/w to generate interrupts)
and those aren't touched by this code.
Is there some variant where this isn't true or can this
code be removed?
--
Andrew Dyer | adyer@righthandtech.com
Sr. Engineer | (630) 238-0789
RightHand Technologies | (630) 238-0469 (fax)
735 N. Edgewood Ave. |
Suite D |
Wood Dale, IL 60191-1261 |
USA |
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