Re: [ECOS] HAL_INTERRUPT_ACKNOWLEDGE on mips

[Nick Garnett <nickg at ecoscentric dot com>]

"Andy Dyer" <adyer@righthandtech.com> writes:

> looking in hal/mips/arch/current/include/hal_intr.h
> I see the generic implementation of HAL_INTERRUPT_ACKNOWLEDGE
> for mips tries to write back into the Cause register
> (CP0 register $13), presumably to clear the IP[7:2]
> bits.
> 
> All of the books I have handy say that the only fields
> in that register that are writable are IP[1:0]
> (sometimes used to allow s/w to generate interrupts)
> and those aren't touched by this code.
> 
> Is there some variant where this isn't true or can this
> code be removed?

I suspect that this was the case in the TX39, the very first MIPS
target we supported. It has some non-standard features, including the
way it uses the IP bits in the status and cause registers.

In reality, not many targets actually use this set of macros since
they usually have a separate interrupt controller and redefine them.

Maybe it should be tidied up, the TX39 is obsolete and we no longer
have any way of running executables. However, its doing no real harm,
and just in case it is actually used by some other platform, it is
probably best left alone for now.

-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com      The eCos and RedBoot experts


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