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A&M Rattler board question


Has anyone had sucess defining a new memory region using an A&M Rattler board? I have used the AdderII boards prior to receiving a Rattler, and have not had a problem.

My technique for creating a new memory region was to change adder.S and hal_aux.c as follows:
(adder.S)
/* NVRAM */
lwi r3,0xfc000401 # 8-bit, GPCM
lwi r5,0xffff8f30
stw r3,BR5(r4)
stw r5,OR5(r4)
(hal_aux.c)
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
// Mapping for the Adder 85x development boards
CYGARC_MEMDESC_CACHE( 0xfe000000, 0x00800000 ), // ROM region
CYGARC_MEMDESC_NOCACHE( 0xff000000, 0x00100000 ), // MCP registers
CYGARC_MEMDESC_NOCACHE( 0xfd000000, 0x00008000 ), // Quad UART
CYGARC_MEMDESC_NOCACHE( 0xfc000000, 0x00008000 ), // NVRAM on exp board
CYGARC_MEMDESC_NOCACHE( 0xfa000000, 0x00400000 ), // Control/Status+LEDs
CYGARC_MEMDESC_CACHE( CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory


CYGARC_MEMDESC_TABLE_END


When I make similar changes in rattler.S and hal_aux.c, I end up segfaulting in hal_variant_
IRQ_init.


(rattler.S)
      // CS5 - NVRAM on exp board
       lwi     r3,0xFFFF9030
       stw     r3,CYGARC_REG_IMM_OR5(r30)
       lwi     r3,0xFC000801
       stw     r3,CYGARC_REG_IMM_BR5(r30)
(hal_aux.c)
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
   // Mapping for the Rattler board
   CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x SDRAM
   CYGARC_MEMDESC_CACHE( 0xFE000000, 0x00800000 ), // ROM region
   CYGARC_MEMDESC_NOCACHE( 0x80000000, 0x00100000 ), // Extended I/O
   CYGARC_MEMDESC_NOCACHE( 0xfc000000, 0x00008000 ), // NVRAM on exp board
   CYGARC_MEMDESC_NOCACHE( 0xFF000000, 0x00100000 ), // IMMR registers

CYGARC_MEMDESC_TABLE_END


Taking the changes out of hal_aux.c and rattler.S allows my test applications to run (as long as they don't access the memory region in question). Any ideas or suggestions are welcome.


Regards,
Rich

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