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Re: A&M Rattler board question


Richard.von.Lehe@gd-ais.com said:
> I need to read the 8250 documentation again.  At the moment I am
> confused as to why there would be a dozen base/option registers for
> various memory banks.
>
> Do I need to disable the MMU to take advantage of the 12 supported banks?
>

That would not be wise, as you would also lose caches!

Try re-arranging your segments to fit within the BAT capabilities.

>
> Gary Thomas wrote:
>
>>Todd Smith said:
>>
>>
>>>I had a similar issue on a custom MPC8250 board. If I remember
>>>correctly, the number of memory region entries is limited (only 4
>>>allowed?) with the MMU on that processor.
>>>
>>>
>>
>>Correct - the 8250 only supports 4 BAT registers.
>>
>>
>>
>>>--Todd
>>>
>>>Richard.von.Lehe@gd-ais.com wrote:
>>>
>>>
>>>
>>>>Has anyone had sucess defining a new memory region using an A&M
>>>>Rattler board?  I have used the AdderII boards prior to receiving a
>>>>Rattler, and have not had a problem.
>>>>
>>>>My technique for creating a new memory region was to change adder.S
>>>>and hal_aux.c as follows:
>>>>(adder.S)
>>>>       /* NVRAM */
>>>>       lwi     r3,0xfc000401   # 8-bit, GPCM
>>>>       lwi     r5,0xffff8f30
>>>>       stw     r3,BR5(r4)
>>>>       stw     r5,OR5(r4)
>>>>(hal_aux.c)
>>>>CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
>>>>   // Mapping for the Adder 85x development boards
>>>>   CYGARC_MEMDESC_CACHE(   0xfe000000, 0x00800000 ), // ROM region
>>>>   CYGARC_MEMDESC_NOCACHE( 0xff000000, 0x00100000 ), // MCP registers
>>>>   CYGARC_MEMDESC_NOCACHE( 0xfd000000, 0x00008000 ), // Quad UART
>>>>   CYGARC_MEMDESC_NOCACHE( 0xfc000000, 0x00008000 ), // NVRAM on exp
>>>>board
>>>>   CYGARC_MEMDESC_NOCACHE( 0xfa000000, 0x00400000 ), //
>>>>Control/Status+LEDs
>>>>   CYGARC_MEMDESC_CACHE(   CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE
>>>>), // Main memory
>>>>
>>>>   CYGARC_MEMDESC_TABLE_END
>>>>
>>>>
>>>>When I make similar changes in rattler.S and hal_aux.c, I end up
>>>>segfaulting in hal_variant_
>>>>IRQ_init.
>>>>(rattler.S)
>>>>      // CS5 - NVRAM on exp board
>>>>       lwi     r3,0xFFFF9030
>>>>       stw     r3,CYGARC_REG_IMM_OR5(r30)
>>>>       lwi     r3,0xFC000801
>>>>       stw     r3,CYGARC_REG_IMM_BR5(r30)
>>>>(hal_aux.c)
>>>>CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
>>>>   // Mapping for the Rattler board
>>>>   CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x
>>>>SDRAM
>>>>   CYGARC_MEMDESC_CACHE( 0xFE000000, 0x00800000 ), // ROM region
>>>>   CYGARC_MEMDESC_NOCACHE( 0x80000000, 0x00100000 ), // Extended I/O
>>>>   CYGARC_MEMDESC_NOCACHE( 0xfc000000, 0x00008000 ), // NVRAM on exp
>>>>board
>>>>   CYGARC_MEMDESC_NOCACHE( 0xFF000000, 0x00100000 ), // IMMR registers
>>>>
>>>>   CYGARC_MEMDESC_TABLE_END
>>>>
>>>>
>>>>Taking the changes out of hal_aux.c and rattler.S allows my test
>>>>applications to run (as long as they don't access the memory region in
>>>>question).  Any ideas or suggestions are welcome.
>>>>Regards,
>>>>Rich
>>>>
>>>>
>>>>
>>>--
>>>Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
>>>and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
>>>
>>>
>>>
>>>
>>
>>
>>
>>
>
>
> --
> Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
> and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss
>
>


------------------------------------------------------------
Gary Thomas                 |
MLB Associates              |  Consulting for the
+1 (970) 229-1963           |    Embedded world
http://www.mlbassoc.com/    |
email: <gary@mlbassoc.com>  |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------

-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss


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