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ARM HAL issues.
- From: osv <osv at javad dot com>
- To: ecos-discuss at ecos dot sourceware dot org
- Date: Thu, 17 Nov 2005 20:12:31 +0300
- Subject: [ECOS] ARM HAL issues.
Hello,
Recently I worked with the eCos ARM HAL got from the public CVS
repository and found some pieces of code that look strange/buggy for me:
1. Entry to hal_thread_switch_context looks buggy.
FUNC_START_ARM(hal_thread_switch_context, r2)
sub ip,sp,#20 // skip svc_sp, svc_lr, vector, cpsr, and pc
stmfd ip!,{sp,lr}
mov sp,ip
...
Please notice that sp and lr are saved on the current stack outside the
current stack boundaries and only in the next instruction the stack
pointer is advanced to include the saved values. Should an interrupt
occur between stmfd and mov instructions, the saved sp and lr could
well be clobbered. Here is a suggested fix (that besides avoids using of
the magic number):
FUNC_START_ARM(hal_thread_switch_context, r2)
mov ip,sp
sub sp,sp,#(ARMREG_SIZE - armreg_lr - 4)
stmfd sp!,{ip,lr}
...
2. IRQ disable in hal_thread_load_context.
FUNC_START_ARM(hal_thread_load_context, r2)
ldr fp,[r0] // get context to restore
mrs r0,cpsr // disable IRQ's
orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
msr cpsr,r0
...
I failed to find disabling of IRQs in the context switch/load routines
in any other eCos HAL. Is it indeed necessary to disable IRQs here?
3. Vague comment in vectors.S.
What I mean is the following:
IRQ:
// Note: I use this exception stack while saving the context because
// the current SP does not seem to be always valid in this CPU mode.
ldr sp,.__exception_stack // get good stack
stmfd sp!,{r0-r5} // save some supervisor regs
What could be the cause of IRQ mode SP being invalid? Is it deficiency
of some ARM chip implementation, hiding HAL bug, or what?
--
Sergei.
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