RE: [ECOS] Thumb support for arm9 variants?

["Lars Povlsen" <lpovlsen at vitesse dot com>]

Andrew,

The offending instructions are indeed inline assembly - its both the
cache manip and reset:

void
cyg_hal_arm9_soft_reset(CYG_ADDRESS entry)
{

    /* It would probably make more sense to have the
       clear/drain/invalidate after disabling the cache and MMU, but
       then we'd have to know the (unmapped) address of this code. */
    asm volatile ("mrs r1,cpsr;"
                  "bic r1,r1,#0x1F;"  /* Put processor in SVC mode */
                  "orr r1,r1,#0x13;"
                  "msr cpsr,r1;"

                  "mov r1, #0;"
                  "mcr p15,0,r1,c7,c7,0;"  /* clear I+DCache */
                  "mcr p15,0,r1,c7,c10,4;" /* Drain Write Buffer */
                  "mcr p15,0,r1,c8,c7,0;"  /* Invalidate TLBs */
                  "mrc p15,0,r1,c1,c0,0;"
                  "bic r1,r1,#0x1000;"     /* disable ICache */
                  "bic r1,r1,#0x0007;"     /* disable DCache, MMU and
alignment faults */
                  "mcr p15,0,r1,c1,c0,0;"
                  "nop;"                   /* delay 1 */
                  "mov pc, %0;"            /* delay 2  - next
instruction should be fetched flat */
                  : : "r" (entry) : "r1");
    for(;;);
}

As this is none of my code (!) - my question is more along the lines as
why the hal/arm/arm9/* variants does not support thumb - when the arm/*
variants do? I was under the impression that the former was the most
recent?

---Lars

-----Original Message-----
From: Andrew Lunn [mailto:andrew@lunn.ch] 
Sent: 12. juni 2006 22:56
To: Lars Povlsen
Cc: eCos Disuss
Subject: Re: [ECOS] Thumb support for arm9 variants?

On Mon, Jun 12, 2006 at 10:02:57PM +0200, Lars Povlsen wrote:
> 
> Hello All!
> 
> I have been tinkering with a couple of ARM9/ARM926 platforms for which

> I have built an eCos HAL modeled after the ARM9 variants in 
> packages/hal/arm/arm9/*. Everything (mostly) is looking great, but 
> wanting to test the thumb-mode of my chips turned out to be less than 
> straight-forward...
> 
> I deduced that I was unable to just "enable" in configtool due to 
> missing "implements CYGINT_HAL_ARM_THUMB_ARCH". But with that added 
> (and the -mthumb compile options that goes along), it seems that not 
> all code in hal/arm/arm9 is "thumb"-compatible:
> 
> arm-elf-gcc -c
> -I/proj/sw/usr/lpovlsen/ecos/build_luton28_ram/install/include
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/
> sr
> c
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/
> te
> sts -I.
> -I/users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/
> sr c/ -finline-limit=7000 -mthumb -mthumb-interwork -mcpu=arm9 -Wall 
> -Wpointer-arith -Wstrict-prototypes -Winline -Wundef  -g -O2 
> -ffunction-sections -fdata-sections  -fno-exceptions 
> -Wp,-MD,src/arm9_misc.tmp -o src/hal_arm_arm9_var_arm9_misc.o 
> /users/lpovlsen/project/ecos/base/packages/hal/arm/arm9/var/current/sr
> c/
> arm9_misc.c
> /tmp/ccmyIUwO.s: Assembler messages:
> /tmp/ccmyIUwO.s:24: Error: bad instruction `mrc p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:24: Error: register expected, not '#0x000F' -- `orr 
> r1,r1,#0x000F'
> /tmp/ccmyIUwO.s:24: Error: bad instruction `mcr p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:26: Error: bad instruction `mrc p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:26: Error: register expected, not '#0x1000' -- `orr 
> r1,r1,#0x1000'
> /tmp/ccmyIUwO.s:26: Error: register expected, not '#0x0002' -- `orr 
> r1,r1,#0x0002'
> /tmp/ccmyIUwO.s:26: Error: bad instruction `mcr p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mrs r1,cpsr'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x1F' -- `bic 
> r1,r1,#0x1F'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x13' -- `orr 
> r1,r1,#0x13'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `msr cpsr,r1'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c7,c7,0'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c7,c10,4'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c8,c7,0'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mrc p15,0,r1,c1,c0,0'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x1000' -- `bic 
> r1,r1,#0x1000'
> /tmp/ccmyIUwO.s:45: Error: register expected, not '#0x0007' -- `bic 
> r1,r1,#0x0007'
> /tmp/ccmyIUwO.s:45: Error: bad instruction `mcr p15,0,r1,c1,c0,0'
> make[1]: *** [src/arm9_misc.o.d] Error 1

Where did these fragments of assembly code come from?  I would not
expect the compiler to generate ARM code when it is supposed to be
generating thumb code. So is this some inline assembly? eg is this cache
manipulation? You might need to write thumb equivelents.

      Andrew


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