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Re: Possible fix for interrupt latency problems on Arm
- From: Jürgen Lambrecht <J dot Lambrecht at televic dot com>
- To: eCos Discussion <ecos-discuss at ecos dot sourceware dot org>
- Date: Mon, 31 Jul 2006 10:30:57 +0200
- Subject: Re: [ECOS] Possible fix for interrupt latency problems on Arm
- References: <44B7850A.4050508@ovus.co.uk>
Hello Mike,
I'm just back from holidays - you didn't receive any reply on your mail?
I also use an ARM (ARM7TDMI, eb55 board based), so I'm interested in the
problem. I don't have interrupt latency problems (yet), but I will ask my
colleague.
This is list is normally a good place to start committing modifications..
For the patch, you must send a diff (you can find examples in the mailing
list), and :
"Next time, please send to ecos-patches@ecos.sourceware.org. Also
include a ChangeLog entry so we don't have to fabricate one."
Kind regards,
Juergen
---
Jürgen Lambrecht
Development Engineer
Televic Transport Systems
http://www.televic.com
Televic NV / SA (main office)
Leo Bekaertlaan 1
B-8870 Izegem
Tel: +32 (0)51 303045
Fax: +32 (0)51 310670
Mike wrote:
I have been looking at why my Arm LPC2220 board occasionally gets
terrible interrupt latencies. This happens particularly when the
interrupt I'm interested in occurs whilst ecos is doing processing after
a TIMER0 (ecos RTC) interrupt.
It seems that interrupt_end() is called from
hal/arm/arch/current/src/vectors.s with interrupts disabled, whereas it
looks to me like interrupt_end() has been designed to run with
interrupts enabled in order for DSRs to be interruptible.
I have modified my own vectors.s by inserting the following immediately
before the call to interrupt_end():
// Enable interrupts
mrs r4,cpsr
bic r4,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
msr cpsr,r4
This seems to work for me, but I would appreciate feedback if this is a
sane and wise thing to do.
As a newbie, how do I submit such modifications for inclusion in the
repository?
Thanks,
Mike
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