RE: [ECOS] gdb , warm reset and debugging

["Sinan KAYA" <sinan dot kaya at siemens dot com>]

Yeah,
That's also what i thought about. I have changed my platform_setup to
disable interrupts both from cpu and icu part. Nevertheless, software
does not stop at my entry point reset_vector. Therefore, it does not
disable them. 

Here is my platform_setup:

        .macro  _platform_setup2
    
        ldr     r1,=ERTEC200_INT_MASK_ALL
        ldr     r2,=1
        str     r2,[r1]

        // initialize CPSR (machine state register)
        mov
r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0
    
        mov r1, #0
        mcr p15,0,r1,c7,c7,0   /* clear I+DCache */
        mcr p15,0,r1,c7,c10,4  /* Drain Write Buffer */
        mcr p15,0,r1,c8,c7,0   /* Invalidate TLBs */
        mrc p15,0,r1,c1,c0,0
        bic r1,r1,#0x1000      /* disable ICache */
        bic r1,r1,#0x0007     /* disable DCache, MMU and alignment
faults */
        mcr p15,0,r1,c1,c0,0
        nop                  



        ldr     r1,=ERTEC200_TIMER0_CTRL_STAT
        ldr     r2,=0
        str     r2,[r1]
        ldr     r1,=ERTEC200_TIMER1_CTRL_STAT
        ldr     r2,=0
        str     r2,[r1]
        ldr     r1,=ERTEC200_INT_MASK_CLEAR
        ldr     r2,=0
        str     r2,[r1]
        ldr     r1,=ERTEC200_INT_MASK_CLEAR
        ldr     r2,=1
        str     r2,[r1]

    
    
        .endm




-----Original Message-----
From: ecos-discuss-owner@ecos.sourceware.org
[mailto:ecos-discuss-owner@ecos.sourceware.org] On Behalf Of Paul D.
DeRocco
Sent: Tuesday, December 05, 2006 10:27 AM
To: ecos-discuss@ecos.sourceware.org
Subject: RE: [ECOS] gdb , warm reset and debugging

> From: Sinan KAYA
>
> I wonder how other people have been performing their debugging
process.
>
> With my current set up here:
> 1. arm946es
> 2. jtag
> 3. insight debugger
> 4. little endian
>
> i receive spurious interrupts when i stop a running a program
> load the software again and run again. However, it does not
> happen again if i do a reload again.
>
> So i receive one spurious interrupt problem per reloading of
> software. Once failed, i do a reload again and it works.
>
> Here is the message:
> ASSERT FAIL: <FFFF>hal_misc.c[213]hal_arch_default_isr() Spurious
> Interrupt!!!
> ASSERT FAIL: <FFFF>hal_misc.c          [ 213] hal_arch_default_isr()
>                              Spurious Interrupt!!!
> ,
> I debugged the code and have seen that the source of spurious
> interrupt is the clock.
>
> To further trace the problem, i put a breakpoint to reset_vector
> function but it does not stop at this place when spurious
> interrupt happens.
>
> Is this a bug of insight or am i missing something ?

It sounds like interrupts are enabled when you restart, which they
shouldn't
be. The spurious interrupt masks further interrupts, so when you restart
a
second time, it works okay.

--

Ciao,               Paul D. DeRocco
Paul                mailto:pderocco@ix.netcom.com


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