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SPI and 9 bit transfers (on AT91)
- From: Peter Niebert <peter at niebert dot com>
- To: ecos-discuss <ecos-discuss at ecos dot sourceware dot org>
- Date: Fri, 22 May 2009 11:55:14 +0200
- Subject: [ECOS] SPI and 9 bit transfers (on AT91)
SPI transfers can vary depending on the protocol between 8 and 16
bits. The generic SPI API suggests transfers in multiples of 8bits
though. How should this be interpreted in cases of protocols with 9 or
more bits?
I suppose that there is no other way than splitting such transfers to
two bytes. It could be acceptable to have this transparent in the
generic SPI API, but the byte order has to be clarified somewhere.
Now I look at the SPI driver for AT91, which currently implements 8bit
transfers only. The configuration record could be extended by an
additional field (bits, by default 8). Then the transfer functions
(polled and dma) have to be adapted. I have no idea how the dma
controller interpretes the transfers for the case of 9bit or higher,
but in principle it should interprete these transfers as half words.
It is of course possible to start with an implementation of polled mode.
Any suggestions?
Thanks!
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