/*============================================================================== System : INTRA S/W Copyright 2008.. ================================================================ BRUSAG, Sensorik & messtechn. ph: +41 44 926 74 74 Entwicklungen, fx: +41 44 926 73 34 Chapfwiesenstr. 14 em: rbrusa@brusag.ch CH-8712 Staefa (Switzerland) http://www.brusag.ch ================================================================================ SWSystem: eCOS and toolchain arm-elf-gcc (GCC) 3.2.1 (eCosCentric) Target: INTRA Controller with AT91SAM7X-256 Abstract: Definitions for the INTRA-target und initialization routine for the ports and peripherals as used by the INTRA-target. See also /from_eva/PIOs_1.ods for more details. -------------------------------------------------------------------------------- Edit history: 23-Sep-08 RWB: Creation - based on Olis input 13-Mar-09 RWB: switch for prototype moved from rtc.c to this file. */ #ifndef BASE_H_ #define BASE_H_ #include #include #define PROTOB 0 // set nonzero if running on a protoboard were SPI-in/out are tied tog // ***************************************************************************** // BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 & AT91SAM7X // rwb 080912 present status: // some of this is used for INTRA, but the list is not // checked and many definitions are probably even invalid // for our maschine. See also for more such definitions. // ***************************************************************************** #define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address #define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address #define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address #define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address #define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address #define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address //#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address #define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address #define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address #define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address #define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address #define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address #define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address #define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address #define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address #define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address #define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address #define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address #define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address #define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address #define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address #define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address #define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address #define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address #define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address #define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address #define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address #define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address #define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address #define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address #define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address #define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address #define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address #define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address #define AT91_PWMC_CMR ( 0) // Channel Mode Register #define AT91_PWMC_CDTYR ( 4) // Channel Duty Cycle Register #define AT91_PWMC_CPRDR ( 8) // Channel Period Register #define AT91_PWMC_CCNTR (12) // Channel Counter Register #define AT91_PWMC_CUPDR (16) // Channel Update Register #define AT91_PWMC_Reserved (20) // Reserved // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- #define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx #define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) #define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) #define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) #define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment #define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity #define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- #define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- #define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- #define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- #define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update // ***************************************************************************** // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface // ***************************************************************************** // *** Register offset in AT91S_PWMC structure *** #define AT91_PWMC_MR ( 0) // PWMC Mode Register #define AT91_PWMC_ENA ( 4) // PWMC Enable Register #define AT91_PWMC_DIS ( 8) // PWMC Disable Register #define AT91_PWMC_SR (12) // PWMC Status Register #define AT91_PWMC_IER (16) // PWMC Interrupt Enable Register #define AT91_PWMC_IDR (20) // PWMC Interrupt Disable Register #define AT91_PWMC_IMR (24) // PWMC Interrupt Mask Register #define AT91_PWMC_ISR (28) // PWMC Interrupt Status Register #define AT91_PWMC_VR (252) // PWMC Version Register #define AT91_PWMC_CH (512) // PWMC Channel 0 // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- #define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. #define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A #define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) #define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. #define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B #define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- #define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 #define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 #define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 #define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 #define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 #define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 #define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 #define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 #define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address #define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address #define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address #define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address #define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address // external routines / prototypes ============================================== extern void Iniihw( void ); // initialization routine -flag-protected, may be // called more than once. #endif /*BASE_H_*/