Re: [ECOS] Change exceptions and interrupts Base for MIPS32

[Nick Garnett <nickg at ecoscentric dot com>]

Elad Yosef <elad.yosef@gmail.com> writes:

> Hi,
> My target is MIPS32 4KEc (not the 4Kc)
> In this CPU, I can configure the base address for exceptions/interrupts.
> 
> The fetch/reset address is always 0xBFC0:0000 and resides inside a ROM
> The ROM is very small. The ROM code only enables the flash device and
> jumps to the RedBoot code in the flash (reset_vector code)
> 
> The Flash device is not mapped to  0xBFC0:0000, according to my platform.
> 
> My issue here is:
> Where is the best location to update the base address?
> 
> variant_init? platfrom_init ? or even in earlier stage inside _start ?

The location of the vectors is controlled by the BEV bit in the status
register. If you take a look at the arch.inc header you will see that
the initial value of this register is defined by INITIAL_SR. If your
platform HAL defines this in its platform.inc then it will override
the default and allow you to clear the BEV bit. There is no need for
extra code.


-- 
Nick Garnett                                       eCos Kernel Architect
eCosCentric Limited    http://www.eCosCentric.com       The eCos experts
Barnwell House, Barnwell Drive, Cambridge, UK.      Tel: +44 1223 245571
Registered in England and Wales:                         Reg No: 4422071
Besuchen Sie uns vom 1-3 MÃrz auf der Embedded World 2011,  Stand 11-414
Visit us at Embedded World 2011, NÃrnberg-Germany, 1-3 Mar, Stand 11-414


--
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss