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IOP310 related cleanups
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Wed, 13 Nov 2002 10:46:22 -0500 (EST)
- Subject: IOP310 related cleanups
I missed the fact earlier, but the recent IOP310 related reorg dropped
an IQ80310 patch I had made last month. This puts that patch back in.
In addition are a few cleanups in the iop310-based hal_platform_setups
to use generic xscale code/macros. And finally, a fix for IOP310 PCI
handling of primary side bridges when acting as PCI host.
--Mark
Index: hal/arm/xscale/cores/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/cores/current/ChangeLog,v
retrieving revision 1.2
diff -u -p -5 -r1.2 ChangeLog
--- hal/arm/xscale/cores/current/ChangeLog 1 Oct 2002 02:18:05 -0000 1.2
+++ hal/arm/xscale/cores/current/ChangeLog 13 Nov 2002 15:41:00 -0000
@@ -1,5 +1,9 @@
+2002-11-13 Mark Salter <msalter@redhat.com>
+
+ * src/xscale_stub.c (find_watch_address): Squelch compiler warning.
+
2002-10-01 Jonathan Larmour <jifl@eCosCentric.com>
* include/hal_cache.h: SA11X0 -> XScale
2002-09-23 Mark Salter <msalter@redhat.com>
Index: hal/arm/xscale/cores/current/src/xscale_stub.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/cores/current/src/xscale_stub.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 xscale_stub.c
--- hal/arm/xscale/cores/current/src/xscale_stub.c 23 Sep 2002 15:57:54 -0000 1.1
+++ hal/arm/xscale/cores/current/src/xscale_stub.c 13 Nov 2002 15:41:00 -0000
@@ -496,11 +496,11 @@ find_thumb_watch_address(unsigned wa0, i
static unsigned
find_watch_address(unsigned wa0, int mode0, unsigned wa1, int mode1)
{
unsigned pc = get_register(PC) - 4;
unsigned cpsr = get_register(PS);
- unsigned opcode, Rn, Rd, Rm, base, addr, val, wd0, wd1;
+ unsigned opcode, Rn, Rd, Rm, base, addr, val = 0, wd0, wd1;
int is_store, use_val, i, offset, shift, size;
if (cpsr & CPSR_THUMB_ENABLE)
is_store = is_thumb_store_insn(pc);
else
Index: hal/arm/xscale/iop310/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/ChangeLog,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ChangeLog
--- hal/arm/xscale/iop310/current/ChangeLog 12 Nov 2002 17:38:49 -0000 1.1
+++ hal/arm/xscale/iop310/current/ChangeLog 13 Nov 2002 15:41:00 -0000
@@ -1,5 +1,14 @@
+2002-11-13 Mark Salter <msalter@redhat.com>
+
+ * src/iop310_pci.c (cyg_hal_plf_pci_init): Reorganize to deal with
+ early PCI setup. Also fix support for primary side bridges when
+ acting as PCI host.
+
+ * include/hal_iop310.h (IOP310_EARLY_PCI_SETUP): Define asm macro to
+ be used by platform setup code to do early (pre-ECC scrub) PCI setup.
+
2002-11-12 Gary Thomas <gary@mlbassoc.com>
* src/iop310_pci.c:
* src/iop310_misc.c:
* src/hal_diag.c:
Index: hal/arm/xscale/iop310/current/include/hal_iop310.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/include/hal_iop310.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 hal_iop310.h
--- hal/arm/xscale/iop310/current/include/hal_iop310.h 12 Nov 2002 17:38:50 -0000 1.1
+++ hal/arm/xscale/iop310/current/include/hal_iop310.h 13 Nov 2002 15:41:01 -0000
@@ -593,10 +593,52 @@ extern void hal_plf_hardware_init(void);
#ifndef __ASSEMBLER__
extern unsigned int _80312_EMISR; // Only valid for PEC ISR
#endif
// ------------------------------------------------------------------------
+#ifdef __ASSEMBLER__
+// Macro to perform early setup (in hal_platform_setup.h) of some PCI
+// registers. This should be used prior to the ECC scrup loop to prevent
+// timeouts with some Plug 'n Play PC BIOSes. Before the 'retry' bit is
+// cleared, this macro must setup the vendor/device ID and the primary
+// inbound window BAR to allow primary side access to SDRAM.
+//
+// Input: reg, reg1 -- scratch registers
+// reg_dram_size -- register holding size of SDRAM
+// vendor_id -- PCI vendor ID
+// device_id -- PCI device ID
+
+.macro IOP310_EARLY_PCI_SETUP reg0, reg1, reg_dram_size, vendor_id, device_id
+ // Setup vendor/device ID for 80312
+ ldr \reg0, =ASVIR_ADDR
+ ldr \reg1, =\vendor_id
+ strh \reg1, [\reg0]
+ ldr \reg0, =ASIR_ADDR
+ ldr \reg1, =\device_id
+ strh \reg1, [\reg0]
+ // Make all secondary bus devices private
+ ldr \reg0, =SISR_ADDR
+ ldr \reg1, =0x03FF
+ strh \reg1, [\reg0]
+ // Setup primary inbound window into SDRAM
+ ldr \reg0, =PIATVR_ADDR
+ mov \reg1, #0xa0000000
+ str \reg1, [\reg0]
+ ldr \reg0, =PIALR_ADDR
+ sub \reg1, \reg_dram_size, #1 // dram_size - 1
+ mvn \reg1, \reg1 // 1s complement
+ str \reg1, [\reg0]
+#ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY
+ ldr \reg0, =EBCR_ADDR
+ mov \reg1, #0x0008
+ strh \reg1, [\reg0]
+#endif
+.endm
+
+#endif // __ASSEMBLER__
+
+// ------------------------------------------------------------------------
// Override the default MMU off code. This is intended
// to be included in an inline asm statement.
#define CYGARC_HAL_MMU_OFF(__paddr__) \
" mrc p15,0,r0,c1,c0,0\n" \
Index: hal/arm/xscale/iop310/current/src/iop310_pci.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/src/iop310_pci.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 iop310_pci.c
--- hal/arm/xscale/iop310/current/src/iop310_pci.c 12 Nov 2002 17:38:50 -0000 1.1
+++ hal/arm/xscale/iop310/current/src/iop310_pci.c 13 Nov 2002 15:41:02 -0000
@@ -69,39 +69,18 @@
#include <cyg/io/pci_hw.h>
#include <cyg/io/pci.h>
static cyg_uint8 pbus_nr;
static cyg_uint8 sbus_nr;
+static cyg_uint8 subbus_nr;
void cyg_hal_plf_pci_init(void)
{
- cyg_uint32 limit_reg, adj_dram_size;
+ cyg_uint32 limit_reg;
cyg_uint8 next_bus;
- // Initialize Secondary PCI bus (bus 1)
- *(volatile cyg_uint16 *)BCR_ADDR |= 0x40; // reset secondary bus
- hal_delay_us(10 * 1000); // 10ms enough??
- *(volatile cyg_uint16 *)BCR_ADDR &= ~0x40; // release reset
-
- // ********* vendor / device id **********
- *(cyg_uint16 *)ASVIR_ADDR = 0x113C;
- *(cyg_uint16 *)ASIR_ADDR = 0x0700;
-
- // suppress secondary bus idsels to provide private secondary devices
- *(cyg_uint16 *)SISR_ADDR = 0x03FF;
-
- // ******* Primary Inbound ATU *********
-
- // set primary inbound ATU translate value register to point to
- // base of local DRAM
- *(cyg_uint32 *)PIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC;
- // set primary inbound ATU limit register to include all of installed DRAM.
- // This value used as a mask.
- adj_dram_size = hal_dram_size;
- limit_reg = (0xFFFFFFFF-(adj_dram_size-1)) & 0xFFFFFFF0;
- *(cyg_uint32 *)PIALR_ADDR = limit_reg;
-
+ // ************ bridge registers *******************
if (iop310_is_host()) {
// set the primary inbound ATU base address to the start of DRAM
*(cyg_uint32 *)PIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000;
@@ -118,34 +97,83 @@ void cyg_hal_plf_pci_init(void)
// outbound DAC Window
*(cyg_uint32 *)PODWVR_ADDR = PRIMARY_DAC_BASE;
// outbound I/O window
*(cyg_uint32 *)POIOWVR_ADDR = PRIMARY_IO_BASE;
- }
+ // set the bridge command register
+ *(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
+
+ // set the subordinate bus number to 0xFF
+ *(cyg_uint8 *)SUBBNR_ADDR = 0xFF;
+ // set the secondary bus number to 1
+ *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
+ *(cyg_uint16 *)BCR_ADDR = 0x0823;
+ // set the primary bus number to 0
+ *(cyg_uint8 *)PBNR_ADDR = PRIMARY_BUS_NUM;
+
+ // allow primary ATU to act as a bus master, respond to PCI
+ // memory accesses, assert P_SERR#, and enable parity checking
+ *(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
+ } else {
#ifdef CYGSEM_HAL_ARM_IOP310_CLEAR_PCI_RETRY
- // clear RETRY
- *(cyg_uint16 *)EBCR_ADDR = 0x0008;
+ // Wait for PC BIOS to initialize bus number
+ int i;
+
+ for (i = 0; i < 15000; i++) {
+ if (*((volatile cyg_uint16 *)PCR_ADDR) & CYG_PCI_CFG_COMMAND_MEMORY)
+ break;
+ hal_delay_us(1000); // 1msec
+ }
+ for (i = 0; i < 15000; i++) {
+ if (*((volatile cyg_uint8 *)SBNR_ADDR) != 0)
+ break;
+ hal_delay_us(1000); // 1msec
+ }
#endif
+ if (*((volatile cyg_uint8 *)SBNR_ADDR) == 0)
+ *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
+ if (*((volatile cyg_uint8 *)SUBBNR_ADDR) == 0)
+ *(cyg_uint8 *)SUBBNR_ADDR = 0xFF;
+ if (*((volatile cyg_uint16 *)BCR_ADDR) == 0)
+ *(cyg_uint16 *)BCR_ADDR = 0x0823;
+ if (*((volatile cyg_uint16 *)PCR_ADDR) == 0)
+ *(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
+ if (*((volatile cyg_uint16 *)PATUCMD_ADDR) == 0)
+ *(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
+ }
+
+ // Initialize Secondary PCI bus (bus 1)
+ *(volatile cyg_uint16 *)BCR_ADDR |= 0x40; // reset secondary bus
+ hal_delay_us(10 * 1000); // 10ms enough??
+ *(volatile cyg_uint16 *)BCR_ADDR &= ~0x40; // release reset
// ******** Secondary Inbound ATU ***********
// set secondary inbound ATU translate value register to point to base
// of local DRAM
*(cyg_uint32 *)SIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC;
// set secondary inbound ATU base address to start of DRAM
*(cyg_uint32 *)SIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000;
- // set secondary inbound ATU limit register to include all of
- // installed DRAM. This value used as a mask.
-
// always allow secondary pci access to all memory (even with A0 step)
- limit_reg = (0xFFFFFFFF - (adj_dram_size - 1)) & 0xFFFFFFF0;
+ limit_reg = (0xFFFFFFFF - (hal_dram_size - 1)) & 0xFFFFFFF0;
*(cyg_uint32 *)SIALR_ADDR = limit_reg;
-
// ********** Set Secondary Outbound Windows ***********
// Note: The secondary outbound ATU memory window value register
// and i/o window value registers are defaulted to 0
@@ -157,21 +185,10 @@ void cyg_hal_plf_pci_init(void)
*(cyg_uint32 *)SODWVR_ADDR = SECONDARY_DAC_BASE;
// outbound I/O window
*(cyg_uint32 *)SOIOWVR_ADDR = SECONDARY_IO_BASE;
- // *********** command / config / latency registers ************
-
- if (iop310_is_host()) {
- // allow primary ATU to act as a bus master, respond to PCI
- // memory accesses, assert P_SERR#, and enable parity checking
- *(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
- }
-
// allow secondary ATU to act as a bus master, respond to PCI memory
// accesses, and assert S_SERR#
*(cyg_uint16 *)SATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
CYG_PCI_CFG_COMMAND_PARITY | \
CYG_PCI_CFG_COMMAND_MASTER | \
@@ -179,39 +196,10 @@ void cyg_hal_plf_pci_init(void)
// enable primary and secondary outbound ATUs, BIST, and primary bus
// direct addressing
*(cyg_uint32 *)ATUCR_ADDR = 0x00000006;
- // ************ bridge registers *******************
- if (iop310_is_host()) {
-
- // set the bridge command register
- *(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
-
- // set the secondary bus number to 1
- *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
- *(cyg_uint16 *)BCR_ADDR = 0x0823;
- // set the primary bus number to 0
- *(cyg_uint8 *)PBNR_ADDR = PRIMARY_BUS_NUM;
- } else {
-#ifdef CYGSEM_HAL_ARM_IOP310_CLEAR_PCI_RETRY
- // Wait for PC BIOS to initialize bus number
- int i;
-
- for (i = 0; i < 15000; i++) {
- if (*((volatile cyg_uint8 *)SBNR_ADDR) != 0)
- break;
- hal_delay_us(1000); // 1msec
- }
-#endif
- if (*((volatile cyg_uint8 *)SBNR_ADDR) == 0)
- *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
- }
-
pbus_nr = *(cyg_uint8 *)PBNR_ADDR;
sbus_nr = *(cyg_uint8 *)SBNR_ADDR;
// Now initialize the PCI busses.
@@ -220,26 +208,36 @@ void cyg_hal_plf_pci_init(void)
next_bus = sbus_nr + 1;
// If we are the host on the Primary bus, then configure it.
if (iop310_is_host()) {
+ // Initialize these so all config cycles first go out over
+ // the Primary side
+ pbus_nr = 0;
+ sbus_nr = 0xff;
+
+ // set the primary bus number to 0
+ *(cyg_uint8 *)PBNR_ADDR = 0;
+ next_bus = 1;
+
// Initialize Primary PCI bus (bus 0)
cyg_pci_set_memory_base(PRIMARY_MEM_BASE);
cyg_pci_set_io_base(PRIMARY_IO_BASE);
cyg_pci_configure_bus(0, &next_bus);
+
+ // set the secondary bus number to next available number
+ *(cyg_uint8 *)SBNR_ADDR = sbus_nr = next_bus;
+
+ pbus_nr = *(cyg_uint8 *)PBNR_ADDR;
+ next_bus = sbus_nr + 1;
}
// Initialize Secondary PCI bus (bus 1)
cyg_pci_set_memory_base(SECONDARY_MEM_BASE);
cyg_pci_set_io_base(SECONDARY_IO_BASE);
cyg_pci_configure_bus(sbus_nr, &next_bus);
-}
-
-void cyg_hal_plf_pci_config_setup( cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset)
-{
+ *(cyg_uint8 *)SUBBNR_ADDR = subbus_nr = next_bus - 1;
}
// Use "naked" attribute to suppress C prologue/epilogue
static void __attribute__ ((naked)) __pci_abort_handler(void)
{
@@ -254,11 +252,11 @@ static inline cyg_uint32 *pci_config_set
{
cyg_uint32 *pdata, *paddr;
cyg_uint32 dev = CYG_PCI_DEV_GET_DEV(devfn);
cyg_uint32 fn = CYG_PCI_DEV_GET_FN(devfn);
- if (bus == 0) {
+ if (bus < sbus_nr || bus > subbus_nr) {
paddr = (cyg_uint32 *)POCCAR_ADDR;
pdata = (cyg_uint32 *)POCCDR_ADDR;
} else {
paddr = (cyg_uint32 *)SOCCAR_ADDR;
pdata = (cyg_uint32 *)SOCCDR_ADDR;
@@ -283,11 +281,11 @@ static inline cyg_uint32 *pci_config_set
static inline int pci_config_cleanup(cyg_uint32 bus)
{
cyg_uint32 status = 0, err = 0;
- if (bus == pbus_nr) {
+ if (bus < sbus_nr || bus > subbus_nr) {
status = *(cyg_uint16 *) PATUSR_ADDR;
if ((status & 0xF900) != 0) {
err = 1;
*(cyg_uint16 *)PATUSR_ADDR = status & 0xF980;
}
Index: hal/arm/xscale/iq80310/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/ChangeLog,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ChangeLog
--- hal/arm/xscale/iq80310/current/ChangeLog 12 Nov 2002 17:38:51 -0000 1.1
+++ hal/arm/xscale/iq80310/current/ChangeLog 13 Nov 2002 15:41:02 -0000
@@ -1,5 +1,19 @@
+2002-11-13 Mark Salter <msalter@redhat.com>
+
+ * misc/redboot_RAM.ecm: Remove CYGPKG_IO_SERIAL_ARM_XSCALE_IQ80310.
+ * misc/redboot_RAMA.ecm: Ditto.
+ * misc/redboot_ROM.ecm: Ditto
+ * misc/redboot_ROMA.ecm: Ditto
+
+ * cdl/hal_arm_xscale_iq80310.cdl (CYGBLD_INTEL_DIAGNOSTICS): Change
+ default to 1.
+ * include/hal_platform_setup.h: Use IOP310_EARLY_PCI_SETUP to make
+ some BIOSes happy. BTB_INIT macro provided elsewhere.
+ * src/diag/*: General cleanup to get rid of warnings and to eliminate
+ functionality provided by the HAL.
+
2002-11-12 Gary Thomas <gary@mlbassoc.com>
* src/diag/xscale_test.c:
* src/diag/test_menu.h:
* src/diag/test_menu.c:
Index: hal/arm/xscale/iq80310/current/cdl/hal_arm_xscale_iq80310.cdl
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/cdl/hal_arm_xscale_iq80310.cdl,v
retrieving revision 1.1
diff -u -p -5 -r1.1 hal_arm_xscale_iq80310.cdl
--- hal/arm/xscale/iq80310/current/cdl/hal_arm_xscale_iq80310.cdl 12 Nov 2002 17:38:51 -0000 1.1
+++ hal/arm/xscale/iq80310/current/cdl/hal_arm_xscale_iq80310.cdl 13 Nov 2002 15:41:02 -0000
@@ -102,11 +102,11 @@ cdl_package CYGPKG_HAL_ARM_XSCALE_IQ8031
}
}
cdl_option CYGBLD_INTEL_DIAGNOSTICS {
display "Build Intel Xscale diagnostics"
- default_value 0
+ default_value 1
parent CYGPKG_REDBOOT_HAL_OPTIONS
active_if CYGBLD_BUILD_REDBOOT_BIN
no_define
description "Enabling this option will include diagnostics
from Intel in the RedBoot image."
Index: hal/arm/xscale/iq80310/current/include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/include/hal_platform_setup.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 hal_platform_setup.h
--- hal/arm/xscale/iq80310/current/include/hal_platform_setup.h 12 Nov 2002 17:38:51 -0000 1.1
+++ hal/arm/xscale/iq80310/current/include/hal_platform_setup.h 13 Nov 2002 15:41:03 -0000
@@ -44,22 +44,24 @@
//#####DESCRIPTIONBEGIN####
//
// Author(s): msalter
// Contributors:
// Date: 2000-10-10
-// Purpose: Intel IOP310 platform specific support routines
+// Purpose: Intel IQ80310 platform specific support routines
// Description:
// Usage: #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
#include <pkgconf/system.h> // System-wide configuration info
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/hal_mm.h> // More MMU definitions
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
#include <cyg/hal/hal_iop310.h> // Platform specific hardware definitions
-#include <cyg/hal/hal_mmu.h> // MMU definitions
// Define macro used to diddle the LEDs during early initialization.
// Can use r0+r1. Argument in \x.
#define CYGHWR_LED_MACRO \
b 667f ;\
@@ -90,12 +92,10 @@
#define RAM_BASE 0xa0000000
#define DRAM_SIZE (512*1024*1024) // max size of available SDRAM
#define DCACHE_SIZE (32*1024) // size of the Dcache
-#define MMU_Control_BTB 0x800
-
// Reserved area for battery backup SDRAM memory test
// This area is not zeroed out by initialization code
#define SDRAM_BATTERY_TEST_BASE 0xA1FFFFF0 // base address of last 16 memory locations in a 32MB SDRAM
@@ -133,46 +133,10 @@
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
- // Enable the BTB
- .macro BTB_INIT reg
-#ifdef CYGSEM_HAL_ARM_IOP310_BTB
- mrc p15, 0, \reg, c1, c0, 0
- orr \reg, \reg, #MMU_Control_BTB
- mcr p15, 0, \reg, c1, c0, 0
- CPWAIT \reg
-#endif
- .endm
-
- // form a first-level section entry
- .macro FL_SECTION_ENTRY base,x,ap,p,d,c,b
- .word (\base << 20) | (\x << 12) | (\ap << 10) | (\p << 9) |\
- (\d << 5) | (\c << 3) | (\b << 2) | 2
- .endm
-
- // form a first-level page table entry
- .macro FL_PT_ENTRY base,p,d
- // I wanted to use logical operations here, but since I am using symbols later
- // to fill in the parameters, I had to use addition to force the assembler to
- // do it right
- .word \base + (\p << 9) + (\d << 5) + 1
- .endm
-
- // form a second level small page entry
- .macro SL_SMPAGE_ENTRY base,ap3,ap2,ap1,ap0,c,b
- .word (\base << 12) | (\ap3 << 10) | (\ap2 << 8) | (\ap1 << 6) |\
- (\ap0 << 4) | (\c << 3) | (\b << 2) | 2
- .endm
-
- // form a second level extended small page entry
- .macro SL_XSMPAGE_ENTRY base,x,ap,c,b
- .word (\base << 12) | (\x << 6) | (\ap << 4) | (\c << 3) | (\b << 2) | 3
- .endm
-
-
// start of platform setup
.macro _platform_setup1
// This is where we wind up immediately after reset. On the IOP310, we have
// to jump around a hole in flash which runs from 0x00001000 - 0x0001fff.
@@ -722,10 +686,12 @@ SDRAM_DRIVE_2_BANK_X8:
// Move 4 byte Test Pattern into register prior to zeroing out
// contents of SDRAM locations
ldr r9, =SDRAM_BATTERY_TEST_BASE
ldr r10, [r9]
+ IOP310_EARLY_PCI_SETUP r0, r1, r4, 0x113C, 0x0700
+
// scrub/init SDRAM if enabled/present
ldr r11, =RAM_BASE // base address of SDRAM
mov r12, r4 // size of memory to scrub
mov r8,r4 // save DRAM size
mov r0, #0 // scrub with 0x0000:0000
Index: hal/arm/xscale/iq80310/current/misc/redboot_RAM.ecm
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/misc/redboot_RAM.ecm,v
retrieving revision 1.1
diff -u -p -5 -r1.1 redboot_RAM.ecm
--- hal/arm/xscale/iq80310/current/misc/redboot_RAM.ecm 12 Nov 2002 17:38:52 -0000 1.1
+++ hal/arm/xscale/iq80310/current/misc/redboot_RAM.ecm 13 Nov 2002 15:41:03 -0000
@@ -15,12 +15,10 @@ cdl_configuration eCos {
package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ;
package -hardware CYGPKG_HAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_IO_PCI current ;
package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
package -hardware CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310 current ;
- package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ;
- package -hardware CYGPKG_IO_SERIAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310 current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_ISOINFRA current ;
Index: hal/arm/xscale/iq80310/current/misc/redboot_RAMA.ecm
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/misc/redboot_RAMA.ecm,v
retrieving revision 1.1
diff -u -p -5 -r1.1 redboot_RAMA.ecm
--- hal/arm/xscale/iq80310/current/misc/redboot_RAMA.ecm 12 Nov 2002 17:38:52 -0000 1.1
+++ hal/arm/xscale/iq80310/current/misc/redboot_RAMA.ecm 13 Nov 2002 15:41:03 -0000
@@ -15,11 +15,10 @@ cdl_configuration eCos {
package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ;
package -hardware CYGPKG_HAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_IO_PCI current ;
package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
package -hardware CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310 current ;
- package -hardware CYGPKG_IO_SERIAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310 current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package CYGPKG_IO_FLASH current ;
Index: hal/arm/xscale/iq80310/current/misc/redboot_ROM.ecm
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/misc/redboot_ROM.ecm,v
retrieving revision 1.1
diff -u -p -5 -r1.1 redboot_ROM.ecm
--- hal/arm/xscale/iq80310/current/misc/redboot_ROM.ecm 12 Nov 2002 17:38:52 -0000 1.1
+++ hal/arm/xscale/iq80310/current/misc/redboot_ROM.ecm 13 Nov 2002 15:41:03 -0000
@@ -15,12 +15,10 @@ cdl_configuration eCos {
package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ;
package -hardware CYGPKG_HAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_IO_PCI current ;
package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
package -hardware CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310 current ;
- package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X current ;
- package -hardware CYGPKG_IO_SERIAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310 current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package -template CYGPKG_ISOINFRA current ;
Index: hal/arm/xscale/iq80310/current/misc/redboot_ROMA.ecm
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/misc/redboot_ROMA.ecm,v
retrieving revision 1.1
diff -u -p -5 -r1.1 redboot_ROMA.ecm
--- hal/arm/xscale/iq80310/current/misc/redboot_ROMA.ecm 12 Nov 2002 17:38:52 -0000 1.1
+++ hal/arm/xscale/iq80310/current/misc/redboot_ROMA.ecm 13 Nov 2002 15:41:03 -0000
@@ -15,11 +15,10 @@ cdl_configuration eCos {
package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ;
package -hardware CYGPKG_HAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_IO_PCI current ;
package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 current ;
package -hardware CYGPKG_DEVS_ETH_ARM_XSCALE_IQ80310 current ;
- package -hardware CYGPKG_IO_SERIAL_ARM_XSCALE_IQ80310 current ;
package -hardware CYGPKG_DEVS_FLASH_ARM_XSCALE_IQ80310 current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
package CYGPKG_IO_FLASH current ;
Index: hal/arm/xscale/iq80310/current/src/diag/7_segment_displays.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/7_segment_displays.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 7_segment_displays.h
--- hal/arm/xscale/iq80310/current/src/diag/7_segment_displays.h 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/7_segment_displays.h 13 Nov 2002 15:41:03 -0000
@@ -52,51 +52,44 @@
/* Addresses of the 7-segment displays registers */
/* 08/25/00 jwf */
-/* iq80303 address decode */
-/*
-#define MSB_DISPLAY_REG (volatile unsigned char *)0xe0040000
-#define LSB_DISPLAY_REG (volatile unsigned char *)0xe0050000
-*/
-
-/* 08/25/00 jwf */
/* iq80310 address decode */
#define MSB_DISPLAY_REG (volatile unsigned char *)0xfe840000 /* 7 segment 0 */
#define LSB_DISPLAY_REG (volatile unsigned char *)0xfe850000 /* 7 segment 1 */
-
/* Values for the 7-segment displays */
-#define DISPLAY_OFF 0xFF
-#define ZERO 0xC0
-#define ONE 0xF9
-#define TWO 0xA4
-#define THREE 0xB0
-#define FOUR 0x99
-#define FIVE 0x92
-#define SIX 0x82
-#define SEVEN 0xF8
-#define EIGHT 0x80
-#define NINE 0x90
-#define LETTER_A 0x88
-#define LETTER_B 0x83
-#define LETTER_C 0xC6
-#define LETTER_D 0xA1
-#define LETTER_E 0x86
-#define LETTER_F 0x8E
-#define LETTER_I 0xCF
-#define LETTER_L 0xC7
-#define LETTER_P 0x8C
-#define LETTER_S 0x92
-#define DECIMAL_POINT 0x7F
-#define DISPLAY_ERROR 0x06 /* Displays "E." */
-
+#define DISPLAY_OFF 0xFF
+#define ZERO 0xC0
+#define ONE 0xF9
+#define TWO 0xA4
+#define THREE 0xB0
+#define FOUR 0x99
+#define FIVE 0x92
+#define SIX 0x82
+#define SEVEN 0xF8
+#define EIGHT 0x80
+#define NINE 0x90
+#define LETTER_A 0x88
+#define LETTER_B 0x83
+#define LETTER_C 0xC6
+#define LETTER_D 0xA1
+#define LETTER_E 0x86
+#define LETTER_F 0x8E
+#define LETTER_I 0xCF
+#define LETTER_L 0xC7
+#define LETTER_P 0x8C
+#define LETTER_S 0x92
+#define DECIMAL_POINT 0x7F
+#define DISPLAY_ERROR 0x06 /* Displays "E." */
/* Parameters for functions */
-#define MSB 0
-#define LSB 1
-#define BOTH 2
+#define MSB 0
+#define LSB 1
+#define BOTH 2
+
+extern const unsigned char SevSegDecode[];
Index: hal/arm/xscale/iq80310/current/src/diag/cycduart.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/cycduart.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 cycduart.c
--- hal/arm/xscale/iq80310/current/src/diag/cycduart.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/cycduart.c 13 Nov 2002 15:41:04 -0000
@@ -45,18 +45,20 @@
// Description:
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
-
+#include <redboot.h>
+#include <cyg/hal/hal_iop310.h> // Hardware definitions
#include "cycduart.h"
#include "iq80310.h"
+#include "test_menu.h"
#define DFLTLOOPERMS 500
//extern int printf(char*,...);
-extern long hexIn();
+extern long hexIn(void);
int break_flag = 0;
unsigned long baud_rate = 0;
static int duart_already_init = FALSE;
@@ -67,11 +69,11 @@ static int calc_looperms(void);
void serial_init(void);
int inreg(int);
void outreg(int, unsigned char);
void serial_set(unsigned long);
void serial_loopback(int);
-int serial_getc();
+int serial_getc(void);
void serial_putc(int);
int serial_write(int, const unsigned char *, int);
int serial_read(int, unsigned char *, int, int);
extern int enable_external_interrupt (int int_id);
@@ -79,31 +81,27 @@ extern int disable_external_interrupt (i
extern int isr_connect(int int_num, void (*handler)(int), int arg);
extern int isr_disconnect(int int_num);
-void duart_initialize()
+void duart_initialize(void)
{
+ if (duart_already_init == FALSE) {
+ /* Calculate the time constant for timeouts on serial_read. */
+ if ((looperms = calc_looperms()) <= 0)
+ looperms = DFLTLOOPERMS;
+ }
- if (duart_already_init == FALSE)
- {
- /* Calculate the time constant for timeouts on serial_read. */
- if ((looperms = calc_looperms()) <= 0)
- looperms = DFLTLOOPERMS;
-
- }
-
- /* Initialize the serial port and set the baud rate.
- * The baud rate is set here for sanity only; the autobaud
- * mechanism will change it as required when the host connects.
- */
-
- serial_init();
- serial_set(baud_rate?baud_rate:9600L);
+ /* Initialize the serial port and set the baud rate.
+ * The baud rate is set here for sanity only; the autobaud
+ * mechanism will change it as required when the host connects.
+ */
- duart_already_init = TRUE;
+ serial_init();
+ serial_set(baud_rate?baud_rate:9600L);
+ duart_already_init = TRUE;
}
/* Establish the loop/time constant to be used in the timing loop in
* serial_read. This is done by putting the UART into loopback mode.
@@ -121,84 +119,80 @@ void duart_initialize()
#define TOTAL_MS (NBYTES*BITS_PER_BYTE*1000/TESTBAUD)
static int
calc_looperms(void)
{
- int i, count, c;
- int totalloops = 0;
+ int i, count, c;
+ int totalloops = 0;
- serial_init();
- serial_set(TESTBAUD); /* set 300 baud */
- serial_loopback(1); /* enable loop back mode */
+ serial_init();
+ serial_set(TESTBAUD); /* set 300 baud */
+ serial_loopback(1); /* enable loop back mode */
+
+ for (i=0; i < NBYTES; i++) {
+ count = 1;
+ serial_putc(0xaa); /* xmit character */
- for (i=0; i < NBYTES; i++)
- {
- count = 1;
- serial_putc(0xaa); /* xmit character */
-
- /*
- * The timing loop is the same as the loops in serial_read.
- * Any changes to the loops in serial_read should be reflected
- * here.
- */
- do
- {
- c = serial_getc();
- } while (c < 0 && count++ > 0);
+ /*
+ * The timing loop is the same as the loops in serial_read.
+ * Any changes to the loops in serial_read should be reflected
+ * here.
+ */
+ do {
+ c = serial_getc();
+ } while (c < 0 && count++ > 0);
- totalloops += count;
- }
+ totalloops += count;
+ }
- serial_loopback(0);
+ serial_loopback(0);
- return(totalloops/TOTAL_MS);
+ return(totalloops/TOTAL_MS);
}
/*
* Initialize the device driver.
*/
void serial_init(void)
{
- /* If the serial port has been init'd before, there may be data in it */
- /* Wait for the transmit FIFO to empty out before resetting anything */
- if (duart_already_init == TRUE)
- {
- while (!(inreg(LSR) & LSR_TSRE));
- }
+ /* If the serial port has been init'd before, there may be data in it */
+ /* Wait for the transmit FIFO to empty out before resetting anything */
+ if (duart_already_init == TRUE) {
+ while (!(inreg(LSR) & LSR_TSRE));
+ }
- /*
- * Configure active port, (uart_unit already set.)
- *
- * Set 8 bits, 1 stop bit, no parity.
- *
- * LCR<7> 0 divisor latch access bit
- * LCR<6> 0 break control (1=send break)
- * LCR<5> 0 stick parity (0=space, 1=mark)
- * LCR<4> 0 parity even (0=odd, 1=even)
- * LCR<3> 0 parity enable (1=enabled)
- * LCR<2> 0 # stop bits (0=1, 1=1.5)
- * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
- */
+ /*
+ * Configure active port, (uart_unit already set.)
+ *
+ * Set 8 bits, 1 stop bit, no parity.
+ *
+ * LCR<7> 0 divisor latch access bit
+ * LCR<6> 0 break control (1=send break)
+ * LCR<5> 0 stick parity (0=space, 1=mark)
+ * LCR<4> 0 parity even (0=odd, 1=even)
+ * LCR<3> 0 parity enable (1=enabled)
+ * LCR<2> 0 # stop bits (0=1, 1=1.5)
+ * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
+ */
- outreg(LCR, 0x3);
+ outreg(LCR, 0x3);
- /* Assert DTR and RTS to prevent hardware handshake problems with
+ /* Assert DTR and RTS to prevent hardware handshake problems with
serial terminals, etc. which can be connected to the serial port */
outreg(MCR, MCR_DTR | MCR_RTS);
- outreg(FCR, FIFO_ENABLE); /* Enable the FIFO */
- outreg(IER, INT_ENABLE); /* Enable appropriate interrupts */
+ outreg(FCR, FIFO_ENABLE); /* Enable the FIFO */
+ outreg(IER, INT_ENABLE); /* Enable appropriate interrupts */
}
/* Read a received character if one is available. Return -1 otherwise. */
-int serial_getc()
+int serial_getc(void)
{
if (inreg(LSR) & LSR_DR)
- {
return inreg(DataIn);
- }
+
return -1;
}
/* Transmit a character. */
void serial_putc(int c)
@@ -211,44 +205,44 @@ void serial_putc(int c)
/*
* Set the baud rate.
*/
void serial_set(unsigned long baud)
{
- unsigned char sav_lcr;
+ unsigned char sav_lcr;
- if(baud == 0)
- baud = 9600L;
+ if(baud == 0)
+ baud = 9600L;
- /*
- * Enable access to the divisor latches by setting DLAB in LCR.
- *
- */
- sav_lcr = inreg(LCR);
- outreg(LCR, LCR_DLAB | sav_lcr);
-
- /*
- * Set divisor latches.
- */
- outreg(BaudLsb, XTAL/(16*baud));
- outreg(BaudMsb, (XTAL/(16*baud)) >> 8);
-
- /*
- * Restore line control register
- */
- outreg(LCR, sav_lcr);
+ /*
+ * Enable access to the divisor latches by setting DLAB in LCR.
+ *
+ */
+ sav_lcr = inreg(LCR);
+ outreg(LCR, LCR_DLAB | sav_lcr);
+
+ /*
+ * Set divisor latches.
+ */
+ outreg(BaudLsb, XTAL/(16*baud));
+ outreg(BaudMsb, (XTAL/(16*baud)) >> 8);
+
+ /*
+ * Restore line control register
+ */
+ outreg(LCR, sav_lcr);
}
/*
* This routine is used by calc_looperms to put the UART in loopback mode.
*/
void serial_loopback(int flag)
{
if (flag)
- outreg(MCR, inreg(MCR) | MCR_LOOP); /* enable loop back mode */
+ outreg(MCR, inreg(MCR) | MCR_LOOP); /* enable loop back mode */
else
- outreg(MCR, inreg(MCR) & ~MCR_LOOP); /* disable loop back mode */
+ outreg(MCR, inreg(MCR) & ~MCR_LOOP); /* disable loop back mode */
}
/*
* These routines are used to read and write to the registers of the
* 16552. The delay routine guarantees the required recovery time between
@@ -289,35 +283,34 @@ static volatile int uart_int;
/* interface. It writes to the scratchpad reg. */
/* then reads it back. During */
/* this test all 8 data lines from the chip */
/* get written with both 1 and 0. */
/************************************************/
-static int bus_test ()
+static int bus_test (void)
{
unsigned char out, in;
int bitpos;
volatile int junk;
junk = (int) &junk; /* Don't let compiler optimize or "registerize" */
outreg(SCR,0); /* Clear scratchpad register */
- for (bitpos = 0; bitpos < 8; bitpos++)
- {
- out = 1 << bitpos;
+ for (bitpos = 0; bitpos < 8; bitpos++) {
+ out = 1 << bitpos;
- outreg(SCR,out); /* Write data to scratchpad reg. */
+ outreg(SCR,out); /* Write data to scratchpad reg. */
- junk = ~0; /* Force data lines high */
+ junk = ~0; /* Force data lines high */
- in = inreg(SCR); /* Read data */
+ in = inreg(SCR); /* Read data */
- printf ("%02X ", in);
+ printf ("%02X ", in);
- /* make sure it's what we wrote */
- if (in != out)
- return (0);
+ /* make sure it's what we wrote */
+ if (in != out)
+ return (0);
}
outreg(SCR,0); /* Clear scratchpad register */
printf ("\n");
return (1);
@@ -325,11 +318,11 @@ static int bus_test ()
/************************************************/
/* DISABLE_UART_INTS */
/* This routine disables uart interrupts */
/************************************************/
-static void disable_uart_ints ()
+static void disable_uart_ints (void)
{
outreg(IER,0); /* Make the uart shut up */
}
/************************************************/
@@ -338,99 +331,96 @@ static void disable_uart_ints ()
/* must return 1 to indicate that an interrupt */
/* was serviced. */
/************************************************/
static void uart_isr (int unused)
{
- unsigned char iir;
+ unsigned char iir;
disable_uart_ints ();
uart_int = 1;
- /* read the IIR to clear the interrupt */
- iir = inreg(IIR);
+ /* read the IIR to clear the interrupt */
+ iir = inreg(IIR);
return ;
}
/************************************************/
/* INIT_UART */
/* This routine initializes the 16550 interrupt */
/* and uart registers and initializes the uart */
/* count. */
/************************************************/
-static void init_uart ()
+static void init_uart (void)
{
- outreg(IER,0x02); /* Enable Tx Empty interrupt -
- should generate an interrupt since Tx is
- empty to begin with */
+ outreg(IER,0x02); /* Enable Tx Empty interrupt -
+ should generate an interrupt since Tx is
+ empty to begin with */
}
/****************************************/
/* UART DIAGNOSTIC TEST */
/****************************************/
-void uart_test ()
+void uart_test (MENU_ARG arg)
{
-volatile int loop;
-int looplim;
-int int_id;
-unsigned long* reg_ptr;
-int i, baud;
-
-/*11/01/00 */
-char info[] = {"Move Console Cable back to Connector J9 and hit <CR> to exit test"};
-int index;
+ volatile int loop;
+ int looplim;
+ int int_id;
+ int i, baud;
+
+ /*11/01/00 */
+ char info[] = {"Move Console Cable back to Connector J9 and hit <CR> to exit test"};
+ int index;
looplim = 400000;
- /* perform tests on both UARTs */
- for (uart_unit = 0; uart_unit < 2; uart_unit++)
- {
+ /* perform tests on both UARTs */
+ for (uart_unit = 0; uart_unit < 2; uart_unit++) {
- if (uart_unit == 0)
- int_id = UART1_INT_ID;
- else
- int_id = UART2_INT_ID;
+ if (uart_unit == 0)
+ int_id = UART1_INT_ID;
+ else
+ int_id = UART2_INT_ID;
- if (!bus_test ())
- printf ("\nERROR: bus_test for UART Unit %d failed\n", uart_unit);
- else
- {
- printf ("\nbus_test for UART Unit %d passed\n", uart_unit);
+ if (!bus_test ())
+ printf ("\nERROR: bus_test for UART Unit %d failed\n", uart_unit);
+ else {
+ printf ("\nbus_test for UART Unit %d passed\n", uart_unit);
- uart_int = 0;
+ uart_int = 0;
- isr_connect (int_id, uart_isr, 0);
+ isr_connect (int_id, uart_isr, 0);
- if (enable_external_interrupt(int_id) != OK)
- printf("ERROR enabling UART UINT %d interrupt!\n", uart_unit);
+ if (enable_external_interrupt(int_id) != OK)
+ printf("ERROR enabling UART UINT %d interrupt!\n", uart_unit);
- init_uart ();
+ init_uart ();
- loop = 0;
-
- while (!uart_int && (loop < looplim))
- loop++;
- if (!uart_int)
- printf ("UART Unit %d INTERRUPT test failed %X\n", uart_unit, loop) ;
- else
- printf ("UART Unit %d INTERRUPT test passed\n", uart_unit);
-
- serial_putc(' ');
- }
-
- /* disable UART interrupt */
- if (disable_external_interrupt(int_id)!= OK)
- printf("ERROR disabling UART UNIT %d interrupt!\n", uart_unit);
+ loop = 0;
- /* disconnect test handler */
- isr_disconnect (int_id);
+ while (!uart_int && (loop < looplim))
+ loop++;
+ if (!uart_int)
+ printf ("UART Unit %d INTERRUPT test failed %X\n", uart_unit, loop) ;
+ else
+ printf ("UART Unit %d INTERRUPT test passed\n", uart_unit);
+ serial_putc(' ');
}
-/* 11/01/00 */
-/* #if 0 */ /* writing to port 2 doesnt work yet... */
+ /* disable UART interrupt */
+ if (disable_external_interrupt(int_id)!= OK)
+ printf("ERROR disabling UART UNIT %d interrupt!\n", uart_unit);
+
+ /* disconnect test handler */
+ isr_disconnect (int_id);
+
+ }
+
+ /* 11/01/00 */
+ /* #if 0 */ /* writing to port 2 doesnt work yet... */
#if 1 /* writing to port 2 doesnt work yet... */
/*
printf ("\nMove the Console Cable to the 2nd Serial Port,\n");
printf ("Connector J10,\n");
@@ -439,58 +429,54 @@ int index;
printf ("Connector J9,\n");
printf ("and hit <CR> to exit test\n");
*/
/* 10/30/00 */
- uart_unit = DFLTPORT; /* test J10, the PCI-700 GDB port */
+ uart_unit = DFLTPORT; /* test J10, the PCI-700 GDB port */
- printf ("\nMove the Console Cable to the 2nd Serial Port, Connector J10,\n");
+ printf ("\nMove the Console Cable to the 2nd Serial Port, Connector J10,\n");
printf ("and Hit <CR> when the cable is connected.\n");
- printf ("The alphabet should print on the screen.\n\n");
+ printf ("The alphabet should print on the screen.\n\n");
/* 11/01/00 */
/*
printf ("After alphabet prints, move Console Cable back to 1st Serial Port,\n");
printf ("Connector J9,\n");
printf ("and hit <CR> to exit test\n");
*/
- baud = 115200;
- serial_init();
+ baud = 115200;
+ serial_init();
serial_set(baud?baud:115200L);
/* while (serial_getc() == -1); */
- while (serial_getc() != 0x0d); /* wait for a carriage return character to start test */
+ while (serial_getc() != 0x0d); /* wait for a carriage return character to start test */
/*
while (1)
{
for ( i = 65; i <= 90; i++ )
serial_putc(i);
}
*/
- for ( i = 65; i <= 90; i++ ) /* transmit the alphabet */
- serial_putc(i);
+ for ( i = 65; i <= 90; i++ ) /* transmit the alphabet */
+ serial_putc(i);
- serial_putc(10); /* transmit a New Line */
- serial_putc(13); /* transmit a Carriage Return */
- serial_putc(10); /* transmit a New Line */
-
- for (index=0; info[index] != '\0'; index++) /* transmit some instructions to the user */
- {
- serial_putc(info[index]);
- }
+ serial_putc(10); /* transmit a New Line */
+ serial_putc(13); /* transmit a Carriage Return */
+ serial_putc(10); /* transmit a New Line */
+ for (index=0; info[index] != '\0'; index++) /* transmit some instructions to the user */
+ serial_putc(info[index]);
- /* point at default port before returning */
-/* uart_unit = DFLTPORT; */
+ /* point at default port before returning */
+ /* uart_unit = DFLTPORT; */
- (void)hexIn();
+ (void)hexIn();
#endif
- printf ("\n\nUART tests done.\n");
-
+ printf ("\n\nUART tests done.\n");
printf ("Press return to continue.\n");
(void) hexIn();
}
Index: hal/arm/xscale/iq80310/current/src/diag/cycduart.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/cycduart.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 cycduart.h
--- hal/arm/xscale/iq80310/current/src/diag/cycduart.h 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/cycduart.h 13 Nov 2002 15:41:04 -0000
@@ -154,9 +154,9 @@
* FCR<2> 1 clear xmit fifo
* FCR<1> 1 clear recv fifo
* FCR<0> 1 turn on fifo mode
*/
#define FIFO_ENABLE 0x07
-#define INT_ENABLE (IER_RLS) /* default interrupt mask */
+#define INT_ENABLE (IER_RLS) /* default interrupt mask */
Index: hal/arm/xscale/iq80310/current/src/diag/diag.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/diag.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 diag.c
--- hal/arm/xscale/iq80310/current/src/diag/diag.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/diag.c 13 Nov 2002 15:41:04 -0000
@@ -52,10 +52,11 @@
//
//==========================================================================
#define DEFINE_VARS
#include <redboot.h>
+#include <cyg/io/eth/eth_drv.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_cache.h>
#include CYGHWR_MEMORY_LAYOUT_H
@@ -84,45 +85,43 @@ void do_hdwr_diag(int arg, char *argv[])
// All others should already be disabled.
__chan = CYGACC_CALL_IF_DEBUG_PROCS();
if (__chan)
CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_DISABLE);
- // Reset secondary PCI bus
- *(volatile cyg_uint16 *)BCR_ADDR |= 0x40; // reset secondary bus
- *(volatile cyg_uint16 *)BCR_ADDR &= ~0x40; // release reset
-
+ HAL_INTERRUPT_MASK(eth_drv_int_vector());
+
hdwr_diag();
}
void __disableDCache(void)
{
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
}
-void __enableDCache()
+void __enableDCache(void)
{
HAL_DCACHE_ENABLE();
}
-void _flushICache()
+void _flushICache(void)
{
HAL_ICACHE_INVALIDATE_ALL();
}
-void __enableICache()
+void __enableICache(void)
{
HAL_ICACHE_ENABLE();
}
-void __disableICache()
+void __disableICache(void)
{
HAL_ICACHE_DISABLE();
}
-void _enableFiqIrq()
+void _enableFiqIrq(void)
{
asm ("mrc p15, 0, r0, c13, c0, 1;"
"orr r0, r0, #0x2000;"
"mrc p15, 0, r0, c13, c0, 1;"
"mrc p13, 0, r0, c0, c0, 0;"
@@ -130,25 +129,25 @@ void _enableFiqIrq()
"mcr p13, 0, r0, c0, c0, 0;"
: : );
}
-void _enable_timer()
+void _enable_timer(void)
{
asm("ldr r1, =0x00000005;"
"mcr p14, 0, r1, c0, c0, 0 ;"
: : : "r1" );
}
-void _disable_timer()
+void _disable_timer(void)
{
asm("ldr r1, =0x00000000;"
"mcr p14, 0, r1, c0, c0, 0 ;"
: : : "r1" );
}
-void _usec_delay()
+void _usec_delay(void)
{
asm ("ldr r2, =0x258;" /* 1 microsec = 600 clocks (600 MHz CPU core) */
"0: mrc p14, 0, r0, c1, c0, 0;" /*read CCNT into r0 */
"cmp r2, r0;" /* compare the current count */
"bpl 0b;" /* stay in loop until count is greater */
@@ -156,11 +155,11 @@ void _usec_delay()
"orr r1, r1, #4;" /* clear the timer */
"mcr p14, 0, r1, c0, c0, 0 ;"
: : : "r0","r1","r2");
}
-void _msec_delay()
+void _msec_delay(void)
{
asm ("ldr r2, =0x927c0;" /* 1 millisec = 600,000 clocks (600 MHz CPU core) */
"0: mrc p14, 0, r0, c1, c0, 0;" /*read CCNT into r0 */
"cmp r2, r0;" /* compare the current count */
"bpl 0b;" /* stay in loop until count is greater */
@@ -168,45 +167,12 @@ void _msec_delay()
"orr r1, r1, #4;" /* clear the timer */
"mcr p14, 0, r1, c0, c0, 0 ;"
: : : "r0","r1","r2");
}
-unsigned int _read_timer()
+unsigned int _read_timer(void)
{
unsigned x;
asm("mrc p14, 0, %0, c1, c0, 0;" : "=r"(x) : );
return x;
}
-#if 0
-FUNC_START _read_intstr
- mrc p13, 0, r0, c4, c0, 0
-
- mov pc, lr
-FUNC_END _read_intstr
-
-
-FUNC_START _read_cpsr
- mrs r0, cpsr
-
- mov pc, lr
-FUNC_END _read_cpsr
-
-
-FUNC_START _cspr_enable_fiq_int
- mrs r0, cpsr
- bic r0, r0, #0x40
- msr cpsr, r0
-
- mov pc, lr
-FUNC_END _cspr_enable_fiq_int
-
-
-FUNC_START _cspr_enable_irq_int
- mrs r0, cpsr
- bic r0, r0, #0x80
- msr cpsr, r0
-
- mov pc, lr
-FUNC_END _cspr_enable_irq_int
-
-#endif
Index: hal/arm/xscale/iq80310/current/src/diag/ether_test.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/ether_test.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ether_test.c
--- hal/arm/xscale/iq80310/current/src/diag/ether_test.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/ether_test.c 13 Nov 2002 15:41:05 -0000
@@ -45,38 +45,35 @@
// Description:
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
-
+#include <redboot.h>
+#include <cyg/io/pci_hw.h>
+#include <cyg/io/pci.h>
#include "pci_bios.h"
#include "iq80310.h"
#include "ether_test.h"
/* Forward declarations */
-static int i557SelfTest ();
-static int i557Init ();
+static int i557SelfTest (void);
+static int i557Init (void);
static int i557Config (UINT8 loopBackMode);
-static int i557AddrSet ();
-static int i557RUStart ();
-static void setUpPacket ();
-static int txPacket ();
-static char *malloc ();
-static void bzero ();
-static void Wait();
-static int waitForRxInt();
-static int get_ether_addr();
+static int i557AddrSet (void);
+static int i557RUStart (void);
+static void setUpPacket (char *p);
+static int txPacket (char *p);
+static char *malloc (int n);
+static int waitForRxInt(void);
+static int get_ether_addr(int unit, UINT8 *buf, int print_flag);
/* Externals */
-//void printf();
-void bcopy();
-extern void sgets();
-extern int atod();
+extern long decIn(void);
+extern void sgets(char *s);
extern int enable_external_interrupt (int int_id);
extern int isr_connect(int int_num, void (*handler)(int), int arg);
extern STATUS pci_isr_connect (int intline, int bus, int device, int (*handler)(int), int arg);
-extern ULONG sys_read_config_dword (UINT32 busno,UINT32 devno,UINT32 funcno,UINT32 offset,UINT32 *data);
extern void delay_ms(int msecs);
extern int eeprom_read (UINT32 pci_base,/* PCI Base address */
int eeprom_addr, /* word offset from start of eeprom */
UINT16 *p_data,/* where to put data in memory */
@@ -103,45 +100,31 @@ static int forever_flag = FALSE;
static UINT32 phy_id = 0;
/* 82557 required data structures which must be allocated */
static struct rfd *pRfd;
static union cmdBlock *pCmdBlock;
-static char *pPacketBuf;
+static char *pPacketBuf;
#define SPEED_NOLINK 0
-#define SPEED_10M 10
-#define SPEED_100M 100
+#define SPEED_10M 10
+#define SPEED_100M 100
static int link_speed = SPEED_NOLINK;
UINT8 unit_intpin;
int unit_devno, unit_busno, unit_funcno;
-#define BUSY_WAIT_LIMIT 0xf000 /* the upper limit on a busy wait
- for command completion, etc. */
-
-#if 0
-/* names for MDI registers */
-static char *mdi_reg_name [] =
- {
- "MDI Control Register ",
- "MDI Status Register ",
- "MDI PHY Identification Register (Word 1) ",
- "MDI PHY Identification Register (Word 2) ",
- "MDI Auto-Negotiation Advertisement Register ",
- "MDI Auto-Negotiation Link Partner Ability Register ",
- "MDI Auto-Negotiation Expansion Register ",
- };
-#endif
+#define BUSY_WAIT_LIMIT 0xf000 /* the upper limit on a busy wait
+ for command completion, etc. */
static void mask_557_ints (void)
{
- pSCB->cmdStat.bits.m = 1;
+ pSCB->cmdStat.bits.m = 1;
}
static void unmask_557_ints (void)
{
- pSCB->cmdStat.bits.m = 0;
+ pSCB->cmdStat.bits.m = 0;
}
/*****************************************************************************
* pci_ether_test - i8255x PCI Ethernet test
*
@@ -150,797 +133,709 @@ static void unmask_557_ints (void)
* controller that is to be tested.
*
*/
void pci_ether_test (UINT32 busno, UINT32 devno, UINT32 funcno)
{
- volatile int i;
- int ntimes;
- int broadcom_flag = FALSE;
- UINT16 phy_addr_reg, temp1, temp2;
- char inputLine[80];
-
- count = 0;
-
- /* read the PCI BAR for the Ethernet controller */
- if (sys_read_config_dword(busno, devno, funcno, 0x10, &adapter[0]) == ERROR)
- {
- printf ("Error Reading Adapter PCI Address\n");
- return;
- }
+ volatile int i;
+ int ntimes;
+ int broadcom_flag = FALSE;
+ UINT16 phy_addr_reg, temp1, temp2;
+ cyg_pci_device_id devid;
+
+ count = 0;
- /* strip off BAR indicator bits */
- adapter[0] &= 0xfffffff0;
+ devid = CYG_PCI_DEV_MAKE_ID(busno, CYG_PCI_DEV_MAKE_DEVFN(devno,funcno));
- unit_devno = devno;
- unit_busno = busno;
- unit_funcno = funcno;
+ /* read the PCI BAR for the Ethernet controller */
+ cyg_pci_read_config_uint32(devid, 0x10, &adapter[0]);
- /* pointer to on-chip SCB */
- pSCB = (struct SCBtype *)(adapter[0] + SCB_OFFSET);
+ /* strip off BAR indicator bits */
+ adapter[0] &= 0xfffffff0;
- unit_intpin = INTA;
+ unit_devno = devno;
+ unit_busno = busno;
+ unit_funcno = funcno;
- printf ("PCI Base Address = 0x%X\n", adapter[0]);
- printf ("PCI Interrupt Pin = 0x%02X\n", unit_intpin);
+ /* pointer to on-chip SCB */
+ pSCB = (struct SCBtype *)(adapter[0] + SCB_OFFSET);
- /* Initialize malloc's memory pool pointer */
- mem_pool = (char *) ETHER_MEM_POOL;
+ unit_intpin = INTA;
+ printf ("PCI Base Address = 0x%X\n", adapter[0]);
+ printf ("PCI Interrupt Pin = 0x%02X\n", unit_intpin);
+
+ /* Initialize malloc's memory pool pointer */
+ mem_pool = (char *) ETHER_MEM_POOL;
- /* Start the timer for delay implementation
- printf("Starting timer... ");
- StartTimer(); */
- printf("Done.\n Resetting chip... ");
-
- /* reset the 82557 to start with a clean slate */
- resetChip();
- printf("Done.\n");
-
- /* Get the UUT's ethernet address */
- if (get_ether_addr (0, node_address, TRUE) == ERROR)
- {
- printf("Error Reading Adapter Ethernet Address\n");
- return;
- }
+ /* Start the timer for delay implementation
+ printf("Starting timer... ");
+ StartTimer(); */
+ printf("Done.\n Resetting chip... ");
+
+ /* reset the 82557 to start with a clean slate */
+ resetChip();
+ printf("Done.\n");
+
+ /* Get the UUT's ethernet address */
+ if (get_ether_addr (0, node_address, TRUE) == ERROR) {
+ printf("Error Reading Adapter Ethernet Address\n");
+ return;
+ }
+
+ temp1 = readMDI(0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_ID_1);
+ temp2 = readMDI(0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_ID_2);
+ phy_id = ((temp1 << 16) | temp2);
- temp1 = readMDI (0 ,MDI_DEFAULT_PHY_ADDR, MDI_PHY_ID_1);
- temp2 = readMDI (0 ,MDI_DEFAULT_PHY_ADDR, MDI_PHY_ID_2);
- phy_id = ((temp1 << 16) | temp2);
-
- if ((phy_id & 0xfffffff0) == I82555_PHY_ID)
- {
- printf ("Intel 82555/558 PHY detected...\n");
+ if ((phy_id & 0xfffffff0) == I82555_PHY_ID) {
+ printf ("Intel 82555/558 PHY detected...\n");
- /* dummy read for reliable status */
- (void)readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
+ /* dummy read for reliable status */
+ (void)readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
- temp1 = readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
- printf ("Status Register Link Status is %s\n", (temp1 & MDI_STAT_LINK) ? "UP" : "DOWN");
+ temp1 = readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
+ printf ("Status Register Link Status is %s\n", (temp1 & MDI_STAT_LINK) ? "UP" : "DOWN");
- phy_addr_reg = readMDI (0, MDI_DEFAULT_PHY_ADDR, I82555_STATCTRL_REG);
+ phy_addr_reg = readMDI (0, MDI_DEFAULT_PHY_ADDR, I82555_STATCTRL_REG);
- if (temp1 & MDI_STAT_LINK) /* speed only valid with good LNK */
- {
- printf ("Connect Speed is %s\n", (phy_addr_reg & I82555_100_MBPS) ? "100Mbps" : "10Mbps");
- link_speed = (phy_addr_reg & I82555_100_MBPS) ? SPEED_100M : SPEED_10M;
- }
- else
- printf ("Connect Speed is NOT VALID\n");
- }
+ if (temp1 & MDI_STAT_LINK) { /* speed only valid with good LNK */
+ printf ("Connect Speed is %s\n", (phy_addr_reg & I82555_100_MBPS) ? "100Mbps" : "10Mbps");
+ link_speed = (phy_addr_reg & I82555_100_MBPS) ? SPEED_100M : SPEED_10M;
+ } else
+ printf ("Connect Speed is NOT VALID\n");
+ }
- if ((phy_id & 0xfffffff0) == ICS1890_PHY_ID)
- {
- printf ("Integrated Circuit Systems ICS1890 PHY detected...\n");
- printf ("Revision = %c\n", 'A' + (phy_id & REVISION_MASK));
-
- /* dummy read for reliable status */
- (void)readMDI (0, MDI_DEFAULT_PHY_ADDR, ICS1890_QUICKPOLL_REG);
- temp1 = readMDI (0, MDI_DEFAULT_PHY_ADDR, ICS1890_QUICKPOLL_REG);
- printf ("Status Register Link Status is %s\n", (temp1 & QUICK_LINK_VALID) ? "UP" : "DOWN");
-
- if (temp1 & QUICK_LINK_VALID) /* speed only valid with good LNK */
- {
- printf ("Connect Speed is %s\n", (temp1 & QUICK_100_MBPS) ? "100Mbps" : "10Mbps");
- link_speed = (temp1 & QUICK_100_MBPS) ?
- SPEED_100M : SPEED_10M;
- }
- else printf ("Connect Speed is NOT VALID\n");
- }
+ if ((phy_id & 0xfffffff0) == ICS1890_PHY_ID) {
+ printf ("Integrated Circuit Systems ICS1890 PHY detected...\n");
+ printf ("Revision = %c\n", 'A' + (phy_id & REVISION_MASK));
+
+ /* dummy read for reliable status */
+ (void)readMDI (0, MDI_DEFAULT_PHY_ADDR, ICS1890_QUICKPOLL_REG);
+ temp1 = readMDI (0, MDI_DEFAULT_PHY_ADDR, ICS1890_QUICKPOLL_REG);
+ printf ("Status Register Link Status is %s\n", (temp1 & QUICK_LINK_VALID) ? "UP" : "DOWN");
+
+ if (temp1 & QUICK_LINK_VALID) { /* speed only valid with good LNK */
+ printf ("Connect Speed is %s\n", (temp1 & QUICK_100_MBPS) ? "100Mbps" : "10Mbps");
+ link_speed = (temp1 & QUICK_100_MBPS) ?
+ SPEED_100M : SPEED_10M;
+ } else
+ printf ("Connect Speed is NOT VALID\n");
+ }
- if ((phy_id & 0xfffffff0) == DP83840_PHY_ID)
- {
- printf ("National DP83840 PHY detected...\n");
- printf ("Revision = %c\n", 'A' + (phy_id & REVISION_MASK));
-
- /* dummy read for reliable status */
- (void)readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
- temp1 = readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
- printf ("Status Register Link Status is %s\n", (temp1 & MDI_STAT_LINK) ? "UP" : "DOWN");
-
- phy_addr_reg = readMDI (0 ,MDI_DEFAULT_PHY_ADDR, DP83840_PHY_ADDR_REG);
-
- if (temp1 & MDI_STAT_LINK) /* speed only valid with good LNK */
- {
- printf ("Connect Speed is %s\n", (phy_addr_reg & PHY_ADDR_SPEED_10_MBPS) ? "10Mbps" : "100Mbps");
- link_speed = (phy_addr_reg & PHY_ADDR_SPEED_10_MBPS) ? SPEED_10M : SPEED_100M;
- }
- else printf ("Connect Speed is NOT VALID\n");
+ if ((phy_id & 0xfffffff0) == DP83840_PHY_ID) {
+ printf ("National DP83840 PHY detected...\n");
+ printf ("Revision = %c\n", 'A' + (phy_id & REVISION_MASK));
+
+ /* dummy read for reliable status */
+ (void)readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
+ temp1 = readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
+ printf ("Status Register Link Status is %s\n", (temp1 & MDI_STAT_LINK) ? "UP" : "DOWN");
+
+ phy_addr_reg = readMDI (0 ,MDI_DEFAULT_PHY_ADDR, DP83840_PHY_ADDR_REG);
+
+ if (temp1 & MDI_STAT_LINK) { /* speed only valid with good LNK */
+ printf ("Connect Speed is %s\n", (phy_addr_reg & PHY_ADDR_SPEED_10_MBPS) ? "10Mbps" : "100Mbps");
+ link_speed = (phy_addr_reg & PHY_ADDR_SPEED_10_MBPS) ? SPEED_10M : SPEED_100M;
}
+ else printf ("Connect Speed is NOT VALID\n");
+ }
- if ((phy_id & 0xfffffff0) == I82553_PHY_ID)
- {
- printf ("Intel 82553 PHY detected...\n");
- printf ("Revision = %c\n", 'A' + (phy_id & REVISION_MASK));
- broadcom_flag = TRUE;
- }
+ if ((phy_id & 0xfffffff0) == I82553_PHY_ID) {
+ printf ("Intel 82553 PHY detected...\n");
+ printf ("Revision = %c\n", 'A' + (phy_id & REVISION_MASK));
+ broadcom_flag = TRUE;
+ }
- if (phy_id == I82553_REVAB_PHY_ID)
- {
- printf ("Intel 82553 PHY detected...\n");
- printf ("Revision = B\n");
- broadcom_flag = TRUE;
- }
+ if (phy_id == I82553_REVAB_PHY_ID) {
+ printf ("Intel 82553 PHY detected...\n");
+ printf ("Revision = B\n");
+ broadcom_flag = TRUE;
+ }
- if (broadcom_flag == TRUE)
- {
- temp2 = readMDI (0,MDI_DEFAULT_PHY_ADDR, I82553_PHY_EXT_REG0);
- printf ("Stepping = %02X\n", GET_REV_CNTR(temp2));
-
- /* dummy read for reliable status */
- (void)readMDI (0 ,MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
- temp1 = readMDI (0 ,MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
- printf ("Status Register Link Status is %s\n", (temp1 & MDI_STAT_LINK) ? "UP" : "DOWN");
-
- if (temp1 & MDI_STAT_LINK) /* speed only valid with good LNK */
- {
- printf ("Connect Speed is %s\n", (temp2 & EXT_REG0_100_MBPS) ? "100Mbps" : "10Mbps");
- link_speed = (temp2 & EXT_REG0_100_MBPS) ? SPEED_100M : SPEED_10M;
- }
- else printf ("Connect Speed is NOT VALID\n");
- }
+ if (broadcom_flag == TRUE) {
+ temp2 = readMDI (0,MDI_DEFAULT_PHY_ADDR, I82553_PHY_EXT_REG0);
+ printf ("Stepping = %02X\n", GET_REV_CNTR(temp2));
+
+ /* dummy read for reliable status */
+ (void)readMDI (0 ,MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
+ temp1 = readMDI (0 ,MDI_DEFAULT_PHY_ADDR, MDI_PHY_STAT);
+ printf ("Status Register Link Status is %s\n", (temp1 & MDI_STAT_LINK) ? "UP" : "DOWN");
+
+ if (temp1 & MDI_STAT_LINK) { /* speed only valid with good LNK */
+ printf ("Connect Speed is %s\n", (temp2 & EXT_REG0_100_MBPS) ? "100Mbps" : "10Mbps");
+ link_speed = (temp2 & EXT_REG0_100_MBPS) ? SPEED_100M : SPEED_10M;
+ } else
+ printf ("Connect Speed is NOT VALID\n");
+ }
+ printf ("\n");
- printf ("\n");
+ /* Run the built-in self test through the port register */
+ if (i557SelfTest () == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Run the built-in self test through the port register */
- if (i557SelfTest () == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ /* Reset clears the interrupt mask */
+ mask_557_ints();
- /* Reset clears the interrupt mask */
- mask_557_ints();
+ printf ("Press return to initialize ethernet controller.\n");
+ sgets (buf);
- printf ("Press return to initialize ethernet controller.\n");
- sgets (buf);
+ /* Initialize data structures */
+ if (i557Init () == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Initialize data structures */
- if (i557Init () == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ /* Set hardware address */
+ if (i557AddrSet () == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Set hardware address */
- if (i557AddrSet () == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ printf ("Press return to perform internal loopback test.\n");
+ sgets (buf);
- printf ("Press return to perform internal loopback test.\n");
- sgets (buf);
+ /* Configure for internal loopback */
+ if (i557Config (INT_LOOP_BACK) == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Configure for internal loopback */
- if (i557Config (INT_LOOP_BACK) == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ delay_ms(100);
- Wait(100);
+ /* Initialize receive buffer and enable receiver */
+ if (i557RUStart () == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Initialize receive buffer and enable receiver */
- if (i557RUStart () == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ /* Send a packet */
+ setUpPacket (pPacketBuf);
+ if (txPacket (pPacketBuf) == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Send a packet */
- setUpPacket (pPacketBuf);
- if (txPacket (pPacketBuf) == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ printf ("Press return to perform loopback through PHY.\n");
+ sgets (buf);
- printf ("Press return to perform loopback through PHY.\n");
- sgets (buf);
+ /* Configure for external loopback */
+ if (i557Config (EXT_LOOP_BACK) == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Configure for external loopback */
- if (i557Config (EXT_LOOP_BACK) == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ delay_ms(100);
- Wait(100);
+ /* Initialize receive buffer and enable receiver */
+ if (i557RUStart () == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Initialize receive buffer and enable receiver */
- if (i557RUStart () == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ /* Send a packet */
+ setUpPacket (pPacketBuf);
+ if (txPacket (pPacketBuf) == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- /* Send a packet */
- setUpPacket (pPacketBuf);
- if (txPacket (pPacketBuf) == ERROR)
- {
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ printf ("Press return to perform external loopback through\n");
+ printf ("10/100 Base T Hub. NOTE: If test duration is not forever,\n");
+ printf ("this test will work only if a properly functioning Hub\n");
+ printf ("and Twisted Pair cable are attached to the network connector\n");
+ printf ("on the front panel.\n");
+ sgets (buf);
+
+ printf ("Enter the number of times to run test (0 = forever): ");
+ ntimes = decIn();
+ printf ("\n\n");
- printf ("Press return to perform external loopback through\n");
- printf ("10/100 Base T Hub. NOTE: If test duration is not forever,\n");
- printf ("this test will work only if a properly functioning Hub\n");
- printf ("and Twisted Pair cable are attached to the network connector\n");
- printf ("on the front panel.\n");
- sgets (buf);
+ if (i557RUStart () == ERROR) {
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- printf ("Enter the number of times to run test (0 = forever): ");
- ntimes = decIn();
- printf ("\n\n");
+ setUpPacket (pPacketBuf);
-/* if (atod (inputLine, &ntimes) == FALSE)
- ntimes = 0;
-*/
- if (i557RUStart () == ERROR)
- {
+ if (ntimes == 0) {
+ forever_flag = TRUE;
+
+ while (1) {
+ if ((i557RUStart() == ERROR)||(txPacket (pPacketBuf) == ERROR)) {
+ printf ("Double-check TP cable and 10/100 Base T Hub\n");
+ printf ("Try testing them with another system\n");
+ printf ("(such as a workstation) that is working correctly.\n");
mask_557_ints (); /* Disable 557 interrupt */
return;
- }
+ }
- setUpPacket (pPacketBuf);
-
- if (ntimes == 0)
- {
- forever_flag = TRUE;
-
- while (1)
- {
- if ((i557RUStart() == ERROR)||(txPacket (pPacketBuf) == ERROR))
- {
- printf ("Double-check TP cable and 10/100 Base T Hub\n");
- printf ("Try testing them with another system\n");
- printf ("(such as a workstation) that is working correctly.\n");
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
-
- count++;
- if (((count) % 1000) == 0)
- printf("Loopback Cycle Count = %d\n", count);
- }
- }
- else
- {
- forever_flag = FALSE;
-
- for (i=0; i<ntimes; i++)
- {
- if ((i557RUStart() == ERROR)||(txPacket (pPacketBuf) == ERROR))
- {
- printf ("Double-check TP cable and 10/100 Base T Hub\n");
- printf ("Try testing them with another system\n");
- printf ("(such as a workstation) that is working correctly.\n");
- mask_557_ints (); /* Disable 557 interrupt */
- return;
- }
+ count++;
+ if (((count) % 1000) == 0)
+ printf("Loopback Cycle Count = %d\n", count);
+ }
+ } else {
+ forever_flag = FALSE;
+
+ for (i=0; i<ntimes; i++) {
+ if ((i557RUStart() == ERROR)||(txPacket (pPacketBuf) == ERROR)) {
+ printf ("Double-check TP cable and 10/100 Base T Hub\n");
+ printf ("Try testing them with another system\n");
+ printf ("(such as a workstation) that is working correctly.\n");
+ mask_557_ints (); /* Disable 557 interrupt */
+ return;
+ }
- count++;
- printf("Loopback Cycle Count = %d\n", count);
- }
+ count++;
+ printf("Loopback Cycle Count = %d\n", count);
+ }
- /* It worked! */
+ /* It worked! */
- mask_557_ints (); /* Disable 557 interrupt */
+ mask_557_ints (); /* Disable 557 interrupt */
- printf ("\nEthernet controller passed. Press return to continue.\n");
+ printf ("\nEthernet controller passed. Press return to continue.\n");
- sgets (buf);
- }
+ sgets (buf);
+ }
}
/* Perform internal self test - returns OK if sucessful, ERROR if not. */
static int i557SelfTest ()
{
-volatile struct selfTest *pSelfTestMem;
-UINT32 oldWord2;
-long delay;
-UINT32 temp;
-int rtnVal;
-
- /* reset the 82557 to start with a clean slate */
- resetChip();
-
- /* Allocate some memory for the self test */
- pSelfTestMem = (struct selfTest *) malloc (sizeof(struct selfTest));
-
- if (pSelfTestMem == NULL)
- {
- printf ("Couldn't get memory for self test.\n");
- return (ERROR);
- }
+ volatile struct selfTest *pSelfTestMem;
+ UINT32 oldWord2;
+ long delay;
+ UINT32 temp;
+ int rtnVal;
+
+ /* reset the 82557 to start with a clean slate */
+ resetChip();
+
+ /* Allocate some memory for the self test */
+ pSelfTestMem = (struct selfTest *) malloc (sizeof(struct selfTest));
+
+ if (pSelfTestMem == NULL) {
+ printf ("Couldn't get memory for self test.\n");
+ return (ERROR);
+ }
- printf ("Sending PORT* self-test command...\n");
- printf ("Local Dump address = 0x%X\n", pSelfTestMem);
+ printf ("Sending PORT* self-test command...\n");
+ printf ("Local Dump address = 0x%X\n", pSelfTestMem);
- /* Set all bits in second word, wait until it changes or a timeout */
- pSelfTestMem->u.word2 = ~0;
- oldWord2 = pSelfTestMem->u.word2;
+ /* Set all bits in second word, wait until it changes or a timeout */
+ pSelfTestMem->u.word2 = ~0;
+ oldWord2 = pSelfTestMem->u.word2;
- temp = ((UINT32) pSelfTestMem) + PORT_SELF_TEST;
+ temp = ((UINT32) pSelfTestMem) + PORT_SELF_TEST;
- portWrite (temp);
+ portWrite (temp);
- /* Wait for test completion or for timeout */
- for (delay = 0; (delay < MAX_DELAY) && (pSelfTestMem->u.word2 == oldWord2); delay++); /* Wait... */
+ /* Wait for test completion or for timeout */
+ for (delay = 0; (delay < MAX_DELAY) && (pSelfTestMem->u.word2 == oldWord2); delay++)
+ ; /* Wait... */
- /* Print results */
- printf ("Self test result: %s\n", (pSelfTestMem->u.bits.selfTest) ? "Fail" : "Pass");
- printf ("ROM content test: %s\n", (pSelfTestMem->u.bits.romTest) ? "Fail" : "Pass");
- printf ("Register test: %s\n", (pSelfTestMem->u.bits.regTest) ? "Fail" : "Pass");
- printf ("Diagnose test: %s\n", (pSelfTestMem->u.bits.diagnTest) ? "Fail" : "Pass");
- printf ("ROM signature: 0x%X\n", pSelfTestMem->romSig);
+ /* Print results */
+ printf ("Self test result: %s\n", (pSelfTestMem->u.bits.selfTest) ? "Fail" : "Pass");
+ printf ("ROM content test: %s\n", (pSelfTestMem->u.bits.romTest) ? "Fail" : "Pass");
+ printf ("Register test: %s\n", (pSelfTestMem->u.bits.regTest) ? "Fail" : "Pass");
+ printf ("Diagnose test: %s\n", (pSelfTestMem->u.bits.diagnTest) ? "Fail" : "Pass");
+ printf ("ROM signature: 0x%X\n", pSelfTestMem->romSig);
- rtnVal = pSelfTestMem->u.bits.selfTest ? ERROR : OK;
+ rtnVal = pSelfTestMem->u.bits.selfTest ? ERROR : OK;
- return (rtnVal);
+ return (rtnVal);
}
/* Initialize the 82557. */
static int i557Init (void)
{
- /* Get memory for system data structures */
- if ( ((pRfd = (struct rfd *) malloc (sizeof(struct rfd))) == NULL) ||
- ((pPacketBuf = malloc(ETHERMTU + sizeof(UINT16) + 6)) == NULL) ||
- ((pCmdBlock = (union cmdBlock *) malloc (sizeof(union cmdBlock))) == NULL) )
- {
- printf ("Memory allocation failed.\n");
- return (ERROR);
- }
+ /* Get memory for system data structures */
+ if ( ((pRfd = (struct rfd *) malloc (sizeof(struct rfd))) == NULL) ||
+ ((pPacketBuf = malloc(ETHERMTU + sizeof(UINT16) + 6)) == NULL) ||
+ ((pCmdBlock = (union cmdBlock *) malloc (sizeof(union cmdBlock))) == NULL) ) {
+ printf ("Memory allocation failed.\n");
+ return (ERROR);
+ }
- /* Set EL bits in command block and rfd so we don't fall of the end */
- pCmdBlock->nop.el = END_OF_LIST;
- pRfd->el = END_OF_LIST;
+ /* Set EL bits in command block and rfd so we don't fall of the end */
+ pCmdBlock->nop.el = END_OF_LIST;
+ pRfd->el = END_OF_LIST;
- /* Reset chip and initialize */
- printf ("Initializing... ");
+ /* Reset chip and initialize */
+ printf ("Initializing... ");
- /* Reset 82557 */
- resetChip ();
+ /* Reset 82557 */
+ resetChip ();
- /* set up the CU and RU base values to 0x0 */
- sendCommand (LOAD_CU_BASE, RU_NOP, 0);
- sendCommand (CU_NOP, LOAD_RU_BASE, 0);
+ /* set up the CU and RU base values to 0x0 */
+ sendCommand (LOAD_CU_BASE, RU_NOP, 0);
+ sendCommand (CU_NOP, LOAD_RU_BASE, 0);
- /* Initialize interrupts */
+ /* Initialize interrupts */
- /* if it is the onboard i82559, it does not use the conventional PCI
- interrupt routines because the interrupt is not multiplexed onto
- the PCI bus */
- if ((unit_busno == 2) && (unit_devno == 0) && (unit_funcno == 0))
- {
- if (isr_connect (ENET_INT_ID, (VOIDFUNCPTR)i557IntHandler, 0xdeadbeef) != OK)
- {
- printf ("Error connecting Ethernet interrupt!\n");
- return (ERROR);
- }
- if (enable_external_interrupt (ENET_INT_ID) != OK)
- {
- printf ("Error enabling Ethernet interrupt!\n");
- return (ERROR);
- }
- }
-
- else /* use regular PCI int connect scheme */
- {
- if (pci_isr_connect (unit_intpin, unit_busno, unit_devno, i557IntHandler, 0xdeadbeef) != OK)
- {
- printf ("Error connecting Ethernet interrupt!\n");
- return (ERROR);
- }
-
+ /* if it is the onboard i82559, it does not use the conventional PCI
+ interrupt routines because the interrupt is not multiplexed onto
+ the PCI bus */
+ if ((unit_busno == 2) && (unit_devno == 0) && (unit_funcno == 0)) {
+ if (isr_connect (ENET_INT_ID, (VOIDFUNCPTR)i557IntHandler, 0xdeadbeef) != OK) {
+ printf ("Error connecting Ethernet interrupt!\n");
+ return (ERROR);
+ }
+ if (enable_external_interrupt (ENET_INT_ID) != OK) {
+ printf ("Error enabling Ethernet interrupt!\n");
+ return (ERROR);
+ }
+ } else { /* use regular PCI int connect scheme */
+ if (pci_isr_connect (unit_intpin, unit_busno, unit_devno, i557IntHandler, 0xdeadbeef) != OK) {
+ printf ("Error connecting Ethernet interrupt!\n");
+ return (ERROR);
}
- unmask_557_ints();
-
- printf ("Done\n");
-
- return (OK);
+ }
+ unmask_557_ints();
+ printf ("Done\n");
+ return (OK);
}
static int initPHY (UINT32 device_type, int loop_mode)
{
-UINT16 temp_reg;
-UINT8 revision;
+ UINT16 temp_reg;
+ UINT8 revision;
- /* strip off revision and phy. id information */
- revision = (UINT8)(device_type & REVISION_MASK);
- device_type &= ~REVISION_MASK;
-
- switch (device_type)
- {
- case ICS1890_PHY_ID:
- temp_reg = readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_CTRL); /* get ready for loopback setting */
+ /* strip off revision and phy. id information */
+ revision = (UINT8)(device_type & REVISION_MASK);
+ device_type &= ~REVISION_MASK;
+
+ switch (device_type) {
+ case ICS1890_PHY_ID:
+ temp_reg = readMDI (0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_CTRL); /* get ready for loopback setting */
- switch (loop_mode)
- {
- case EXT_LOOP_BACK: /* loopback on the MII interface */
- temp_reg |= MDI_CTRL_LOOPBACK; /* MII loopback */
- break;
-
- case INT_LOOP_BACK:
- default:
- break;
- }
+ switch (loop_mode) {
+ case EXT_LOOP_BACK: /* loopback on the MII interface */
+ temp_reg |= MDI_CTRL_LOOPBACK; /* MII loopback */
+ break;
+
+ case INT_LOOP_BACK:
+ default:
+ break;
+ }
- writeMDI(0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_CTRL, temp_reg);
- break;
+ writeMDI(0, MDI_DEFAULT_PHY_ADDR, MDI_PHY_CTRL, temp_reg);
+ break;
- case DP83840_PHY_ID: /* set the Intel-specified "must set" bits */
- temp_reg = readMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_PCR_REG);
- temp_reg |= (PCR_TXREADY_SEL | PCR_FCONNECT);
- writeMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_PCR_REG, temp_reg);
-
- /* get ready for loopback setting */
- temp_reg = readMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_LOOPBACK_REG);
- temp_reg &= CLEAR_LOOP_BITS;
-
- switch (loop_mode)
- {
- case EXT_LOOP_BACK:
- temp_reg |= TWISTER_LOOPBACK;
- break;
-
- case INT_LOOP_BACK:
- default:
- break;
- }
-
- writeMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_LOOPBACK_REG, temp_reg);
- break;
-
- case I82553_PHY_ID:
- case I82553_REVAB_PHY_ID:
- case I82555_PHY_ID:
- break;
-
- default:
- return (ERROR);
- break;
- }
+ case DP83840_PHY_ID: /* set the Intel-specified "must set" bits */
+ temp_reg = readMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_PCR_REG);
+ temp_reg |= (PCR_TXREADY_SEL | PCR_FCONNECT);
+ writeMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_PCR_REG, temp_reg);
+
+ /* get ready for loopback setting */
+ temp_reg = readMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_LOOPBACK_REG);
+ temp_reg &= CLEAR_LOOP_BITS;
+
+ switch (loop_mode) {
+ case EXT_LOOP_BACK:
+ temp_reg |= TWISTER_LOOPBACK;
+ break;
+
+ case INT_LOOP_BACK:
+ default:
+ break;
+ }
+
+ writeMDI (0,MDI_DEFAULT_PHY_ADDR, DP83840_LOOPBACK_REG, temp_reg);
+ break;
+
+ case I82553_PHY_ID:
+ case I82553_REVAB_PHY_ID:
+ case I82555_PHY_ID:
+ break;
+
+ default:
+ return (ERROR);
+ break;
+ }
- return (OK);
+ return (OK);
}
/* Set hardware address of the 82557. */
static int i557AddrSet ()
{
printf ("Setting hardware ethernet address to ");
printf ("%02X:%02X:%02X:", node_address[0], node_address[1], node_address[2]);
printf ("%02X:%02X:%02X... ", node_address[3], node_address[4], node_address[5]);
- /* Set up iaSetup command block and execute */
- bzero ((char *) pCmdBlock, sizeof(union cmdBlock));
- pCmdBlock->iaSetup.code = IA_SETUP;
- pCmdBlock->iaSetup.el = END_OF_LIST;
- bcopy (node_address, pCmdBlock->iaSetup.enetAddr, sizeof(node_address));
-
- sendCommand (CU_START, RU_NOP, ((UINT32)pCmdBlock));
-
- if ((waitForInt() == ERROR) || (pCmdBlock->iaSetup.ok != 1))
- {
- printf ("failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
- printf ("C bit = %d\n",pCmdBlock->iaSetup.c);
- printf ("OK bit = %d\n",pCmdBlock->iaSetup.ok);
- return (ERROR);
- }
+ /* Set up iaSetup command block and execute */
+ memset((char *) pCmdBlock, 0, sizeof(union cmdBlock));
+ pCmdBlock->iaSetup.code = IA_SETUP;
+ pCmdBlock->iaSetup.el = END_OF_LIST;
+ memcpy(pCmdBlock->iaSetup.enetAddr, node_address, sizeof(node_address));
+
+ sendCommand (CU_START, RU_NOP, ((UINT32)pCmdBlock));
+
+ if ((waitForInt() == ERROR) || (pCmdBlock->iaSetup.ok != 1)) {
+ printf ("failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
+ printf ("C bit = %d\n",pCmdBlock->iaSetup.c);
+ printf ("OK bit = %d\n",pCmdBlock->iaSetup.ok);
+ return (ERROR);
+ }
- printf ("done.\n");
-
- return (OK);
+ printf ("done.\n");
+ return (OK);
}
/* Configure the 82557. */
static int i557Config (UINT8 loopBackMode) /* None, int, or ext 1, 2 (see etherTest.h) */
{
- printf ("\nConfiguring for ");
-
- switch (loopBackMode)
- {
- case INT_LOOP_BACK:
- printf ("internal loopback... ");
- break;
- case EXT_LOOP_BACK:
- printf ("external loopback, LPBK* active... ");
- break;
- default:
- printf ("Unknown loopback mode, exiting...\n");
- return (ERROR);
- }
+ printf ("\nConfiguring for ");
- /* Set up configure command block and execute */
- bzero ((char *) pCmdBlock, sizeof(union cmdBlock));
- pCmdBlock->configure.code = CONFIGURE;
- pCmdBlock->configure.el = END_OF_LIST;
- pCmdBlock->configure.configData[ 0] = CONFIG_BYTE_00;
- pCmdBlock->configure.configData[ 1] = CONFIG_BYTE_01;
- pCmdBlock->configure.configData[ 2] = CONFIG_BYTE_02;
- pCmdBlock->configure.configData[ 3] = CONFIG_BYTE_03;
- pCmdBlock->configure.configData[ 4] = CONFIG_BYTE_04;
- pCmdBlock->configure.configData[ 5] = CONFIG_BYTE_05;
- pCmdBlock->configure.configData[ 6] = CONFIG_BYTE_06;
- pCmdBlock->configure.configData[ 7] = CONFIG_BYTE_07;
- pCmdBlock->configure.configData[ 8] = CONFIG_BYTE_08;
- pCmdBlock->configure.configData[ 9] = CONFIG_BYTE_09;
- pCmdBlock->configure.configData[10] = CONFIG_BYTE_10 | loopBackMode;
- pCmdBlock->configure.configData[11] = CONFIG_BYTE_11;
- pCmdBlock->configure.configData[12] = CONFIG_BYTE_12;
- pCmdBlock->configure.configData[13] = CONFIG_BYTE_13;
- pCmdBlock->configure.configData[14] = CONFIG_BYTE_14;
- pCmdBlock->configure.configData[15] = CONFIG_BYTE_15;
- pCmdBlock->configure.configData[16] = CONFIG_BYTE_16;
- pCmdBlock->configure.configData[17] = CONFIG_BYTE_17;
- pCmdBlock->configure.configData[18] = CONFIG_BYTE_18;
-
- if (link_speed == SPEED_100M)
- pCmdBlock->configure.configData[19] = CONFIG_BYTE_19_100T;
- else
- {
- pCmdBlock->configure.configData[19] = CONFIG_BYTE_19_10T;
- pCmdBlock->configure.configData[20] = CONFIG_BYTE_20;
- pCmdBlock->configure.configData[21] = CONFIG_BYTE_21;
- }
-
- sendCommand (CU_START, RU_NOP, ((UINT32)pCmdBlock));
+ switch (loopBackMode) {
+ case INT_LOOP_BACK:
+ printf ("internal loopback... ");
+ break;
+ case EXT_LOOP_BACK:
+ printf ("external loopback, LPBK* active... ");
+ break;
+ default:
+ printf ("Unknown loopback mode, exiting...\n");
+ return (ERROR);
+ }
- if ((waitForInt() == ERROR) || (pCmdBlock->configure.ok != 1))
- {
- printf ("failed. Status: 0x%04X.\n",
- pSCB->cmdStat.words.status);
+ /* Set up configure command block and execute */
+ memset ((char *) pCmdBlock, 0, sizeof(union cmdBlock));
+ pCmdBlock->configure.code = CONFIGURE;
+ pCmdBlock->configure.el = END_OF_LIST;
+ pCmdBlock->configure.configData[ 0] = CONFIG_BYTE_00;
+ pCmdBlock->configure.configData[ 1] = CONFIG_BYTE_01;
+ pCmdBlock->configure.configData[ 2] = CONFIG_BYTE_02;
+ pCmdBlock->configure.configData[ 3] = CONFIG_BYTE_03;
+ pCmdBlock->configure.configData[ 4] = CONFIG_BYTE_04;
+ pCmdBlock->configure.configData[ 5] = CONFIG_BYTE_05;
+ pCmdBlock->configure.configData[ 6] = CONFIG_BYTE_06;
+ pCmdBlock->configure.configData[ 7] = CONFIG_BYTE_07;
+ pCmdBlock->configure.configData[ 8] = CONFIG_BYTE_08;
+ pCmdBlock->configure.configData[ 9] = CONFIG_BYTE_09;
+ pCmdBlock->configure.configData[10] = CONFIG_BYTE_10 | loopBackMode;
+ pCmdBlock->configure.configData[11] = CONFIG_BYTE_11;
+ pCmdBlock->configure.configData[12] = CONFIG_BYTE_12;
+ pCmdBlock->configure.configData[13] = CONFIG_BYTE_13;
+ pCmdBlock->configure.configData[14] = CONFIG_BYTE_14;
+ pCmdBlock->configure.configData[15] = CONFIG_BYTE_15;
+ pCmdBlock->configure.configData[16] = CONFIG_BYTE_16;
+ pCmdBlock->configure.configData[17] = CONFIG_BYTE_17;
+ pCmdBlock->configure.configData[18] = CONFIG_BYTE_18;
+
+ if (link_speed == SPEED_100M)
+ pCmdBlock->configure.configData[19] = CONFIG_BYTE_19_100T;
+ else {
+ pCmdBlock->configure.configData[19] = CONFIG_BYTE_19_10T;
+ pCmdBlock->configure.configData[20] = CONFIG_BYTE_20;
+ pCmdBlock->configure.configData[21] = CONFIG_BYTE_21;
+ }
- return (ERROR);
- }
+ sendCommand (CU_START, RU_NOP, ((UINT32)pCmdBlock));
- initPHY (phy_id, loopBackMode); /* set up the PHY interface appropriately */
+ if ((waitForInt() == ERROR) || (pCmdBlock->configure.ok != 1)) {
+ printf ("failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
+ return (ERROR);
+ }
- printf ("done.\n");
+ initPHY (phy_id, loopBackMode); /* set up the PHY interface appropriately */
- return (OK);
+ printf ("done.\n");
+ return (OK);
}
-static int i557RUStart ()
+static int i557RUStart (void)
{
- volatile long delay;
+ volatile long delay;
-#if 0
- printf ("Enabling receiver... ");
-#endif
+ memset((char *) pRfd, 0, sizeof(struct rfd));
- bzero ((char *) pRfd, sizeof(struct rfd));
+ /* Set end-of-list bit in the rfd so we don't fall off the end */
+ pRfd->el = END_OF_LIST;
+ pRfd->s = 1;
+ pRfd->sf = 0; /* Simplified mode */
+ pRfd->rbdAddr = (UINT8 *) 0xffffffff; /* No RBD */
+ /* buffer size: */
+ pRfd->size = sizeof (pRfd->rxData) + sizeof (pRfd->destAddr) + sizeof (pRfd->sourceAddr) + sizeof (pRfd->length);
- /* Set end-of-list bit in the rfd so we don't fall off the end */
- pRfd->el = END_OF_LIST;
- pRfd->s = 1;
- pRfd->sf = 0; /* Simplified mode */
- pRfd->rbdAddr = (UINT8 *) 0xffffffff; /* No RBD */
- /* buffer size: */
- pRfd->size = sizeof (pRfd->rxData) + sizeof (pRfd->destAddr) + sizeof (pRfd->sourceAddr) + sizeof (pRfd->length);
-
- sendCommand (CU_NOP, RU_START, ((UINT32)pRfd));
-
- /*
- * Poll, can't use waitForInt (), as this step doesn't generate interrupts.
- */
-
- i557Status = 0;
-
- /* Wait for timeout (i557Status changes) or RU_STAT is RU_READY */
- for (delay = 0; (delay < MAX_DELAY) && (pSCB->cmdStat.bits.rus != RU_READY); delay++)
- ; /* Wait... */
-
- if (pSCB->cmdStat.bits.rus != RU_READY)
- {
- printf ("failed. Status: 0x%04X.\n",
- pSCB->cmdStat.words.status);
- return (ERROR);
- }
+ sendCommand (CU_NOP, RU_START, ((UINT32)pRfd));
-#if 0
- printf ("done. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
-#endif
+ /*
+ * Poll, can't use waitForInt (), as this step doesn't generate interrupts.
+ */
- return (OK);
+ i557Status = 0;
+
+ /* Wait for timeout (i557Status changes) or RU_STAT is RU_READY */
+ for (delay = 0; (delay < MAX_DELAY) && (pSCB->cmdStat.bits.rus != RU_READY); delay++)
+ ; /* Wait... */
+
+ if (pSCB->cmdStat.bits.rus != RU_READY) {
+ printf ("failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
+ return (ERROR);
+ }
+
+ return (OK);
}
/*
* Get packet ready to send out over the network. Buffer should be
* ETHERMTU + sizeof(enet_addr) + sizeof(UINT16)
*/
static void setUpPacket (char *pBuf)/* Where to put it */
{
- bcopy (node_address, pBuf, sizeof(node_address));
- pBuf += sizeof(node_address); /* skip dest. address */
-
- *((UINT16 *) pBuf) = 0;
- pBuf += sizeof(UINT16); /* skip length field */
+ memcpy (pBuf, node_address, sizeof(node_address));
+ pBuf += sizeof(node_address); /* skip dest. address */
+
+ *((UINT16 *) pBuf) = 0;
+ pBuf += sizeof(UINT16); /* skip length field */
- makePacket (pBuf, ETHERMTU);
+ makePacket (pBuf, ETHERMTU);
}
/* Send and verify a packet using the current loopback mode. */
static int txPacket (char *pBuf) /* Dest addr, ethertype, buffer */
{
- int status = OK;
+ int status = OK;
- /* Set up transmit command block and execute */
- bzero ((char *) pCmdBlock, sizeof(union cmdBlock));
- pCmdBlock->transmit.code = TRANSMIT;
- pCmdBlock->transmit.el = END_OF_LIST;
- pCmdBlock->transmit.sf = 0; /* Simplified mode */
- pCmdBlock->transmit.tbdAddr = (UINT8 *) 0xffffffff; /* No TBD */
- pCmdBlock->transmit.eof = 1; /* Entire frame here */
- /* # bytes to tx: */
- pCmdBlock->transmit.tcbCount = sizeof (pCmdBlock->transmit.destAddr) + sizeof (pCmdBlock->transmit.length) +
- sizeof (pCmdBlock->transmit.txData);
+ /* Set up transmit command block and execute */
+ memset((char *) pCmdBlock, 0, sizeof(union cmdBlock));
+ pCmdBlock->transmit.code = TRANSMIT;
+ pCmdBlock->transmit.el = END_OF_LIST;
+ pCmdBlock->transmit.sf = 0; /* Simplified mode */
+ pCmdBlock->transmit.tbdAddr = (UINT8 *) 0xffffffff; /* No TBD */
+ pCmdBlock->transmit.eof = 1; /* Entire frame here */
+ /* # bytes to tx: */
+ pCmdBlock->transmit.tcbCount = sizeof (pCmdBlock->transmit.destAddr) + sizeof (pCmdBlock->transmit.length) +
+ sizeof (pCmdBlock->transmit.txData);
#if 0
- printf ("destAddr size = %d\n", sizeof (pCmdBlock->transmit.destAddr));
- printf ("length size = %d\n", sizeof (pCmdBlock->transmit.length));
- printf ("Transmitting %d bytes\n", pCmdBlock->transmit.tcbCount);
+ printf ("destAddr size = %d\n", sizeof (pCmdBlock->transmit.destAddr));
+ printf ("length size = %d\n", sizeof (pCmdBlock->transmit.length));
+ printf ("Transmitting %d bytes\n", pCmdBlock->transmit.tcbCount);
#endif
- bcopy (pBuf, pCmdBlock->transmit.destAddr, sizeof(node_address) + sizeof(UINT16) + ETHERMTU);
+ memcpy (pCmdBlock->transmit.destAddr, pBuf, sizeof(node_address) + sizeof(UINT16) + ETHERMTU);
- rxSem = 0; /* no Receive interrupt */
+ rxSem = 0; /* no Receive interrupt */
- sendCommand (CU_START, RU_NOP, ((UINT32)pCmdBlock));
+ sendCommand (CU_START, RU_NOP, ((UINT32)pCmdBlock));
- if (waitForInt() == ERROR)
- {
- printf ("No Transmit Interrupt\n");
- status = ERROR;
- }
+ if (waitForInt() == ERROR) {
+ printf ("No Transmit Interrupt\n");
+ status = ERROR;
+ }
- if (pCmdBlock->transmit.ok != 1)
- {
- printf ("tx failed. Status: 0x%04X.\n",
+ if (pCmdBlock->transmit.ok != 1) {
+ printf ("tx failed. Status: 0x%04X.\n",
pSCB->cmdStat.words.status);
- status = ERROR;
- }
+ status = ERROR;
+ }
- if (status == ERROR)
- {
- printf ("Transmit OK = %d\n", pCmdBlock->transmit.ok);
- return (ERROR);
- }
+ if (status == ERROR) {
+ printf ("Transmit OK = %d\n", pCmdBlock->transmit.ok);
+ return (ERROR);
+ }
#if 1
- if (waitForRxInt() == ERROR)
- {
- printf ("No Receive Interrupt\n");
- status = ERROR;
- }
+ if (waitForRxInt() == ERROR) {
+ printf ("No Receive Interrupt\n");
+ status = ERROR;
+ }
- if (pRfd->ok != 1)
- {
- printf ("rx failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
- status = ERROR;
- }
+ if (pRfd->ok != 1) {
+ printf ("rx failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
+ status = ERROR;
+ }
#if 1
- /* If RU still ready, hang for receive interrupt */
- if (pSCB->cmdStat.bits.rus == RU_READY)
- {
- if (waitForRxInt() == ERROR)
- {
- printf ("No Receive Interrupt\n");
- status = ERROR;
- }
-
- if (pRfd->ok != 1)
- {
- printf ("rx failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
- status = ERROR;
- }
+ /* If RU still ready, hang for receive interrupt */
+ if (pSCB->cmdStat.bits.rus == RU_READY) {
+ if (waitForRxInt() == ERROR) {
+ printf ("No Receive Interrupt\n");
+ status = ERROR;
}
-#endif
- if (status == ERROR)
- {
- printf ("\nTransmit Stats:\n");
- printf ("---------------\n");
- printf ("Transmit OK = %d\n", pCmdBlock->transmit.ok);
-
- printf ("\nReceive Stats:\n");
- printf ("---------------\n\n");
- printf ("Receive OK = %d\n", pRfd->ok);
- printf ("CRC Error = %d\n", pRfd->crcErr);
- printf ("Alignment Error = %d\n", pRfd->alignErr);
- printf ("Resource Error = %d\n", pRfd->noRsrc);
- printf ("DMA Overrun Error = %d\n", pRfd->dmaOverrun);
- printf ("Frame Too Short Error = %d\n", pRfd->frameTooshort);
- printf ("Receive Collision Error = %d\n", pRfd->rxColl);
- return (ERROR);
+ if (pRfd->ok != 1) {
+ printf ("rx failed. Status: 0x%04X.\n", pSCB->cmdStat.words.status);
+ status = ERROR;
}
+ }
+#endif
+
+ if (status == ERROR) {
+ printf ("\nTransmit Stats:\n");
+ printf ("---------------\n");
+ printf ("Transmit OK = %d\n", pCmdBlock->transmit.ok);
+
+ printf ("\nReceive Stats:\n");
+ printf ("---------------\n\n");
+ printf ("Receive OK = %d\n", pRfd->ok);
+ printf ("CRC Error = %d\n", pRfd->crcErr);
+ printf ("Alignment Error = %d\n", pRfd->alignErr);
+ printf ("Resource Error = %d\n", pRfd->noRsrc);
+ printf ("DMA Overrun Error = %d\n", pRfd->dmaOverrun);
+ printf ("Frame Too Short Error = %d\n", pRfd->frameTooshort);
+ printf ("Receive Collision Error = %d\n", pRfd->rxColl);
+ return (ERROR);
+ }
#if 0
- printf ("Packet Actual Size = %d\n", pRfd->actCount);
+ printf ("Packet Actual Size = %d\n", pRfd->actCount);
#endif
- if (checkPacket (pCmdBlock->transmit.txData, pRfd->rxData, ETHERMTU) == ERROR)
- {
- printf ("data verify error.\n");
- return (ERROR);
- }
+ if (checkPacket (pCmdBlock->transmit.txData, pRfd->rxData, ETHERMTU) == ERROR) {
+ printf ("data verify error.\n");
+ return (ERROR);
+ }
- if (forever_flag == FALSE) printf ("data OK.\n");
+ if (forever_flag == FALSE)
+ printf ("data OK.\n");
#endif
- return (OK);
+ return (OK);
}
/*
* "Poor Man's Malloc" - return a pointer to a block of memory at least
* The block returned will have been zeroed.
*/
static char *malloc (int numBytes) /* number of bytes needed */
{
- volatile char *rtnPtr; /* ptr to return to caller */
- long new_mem_pool; /* For figuring new pool base address */
+ volatile char *rtnPtr; /* ptr to return to caller */
+ long new_mem_pool; /* For figuring new pool base address */
- rtnPtr = mem_pool; /* Return pointer to start of free pool */
+ rtnPtr = mem_pool; /* Return pointer to start of free pool */
- /* Now calculate new base of free memory pool (round to >= 16 bytes) */
- new_mem_pool = (UINT32) mem_pool;
- new_mem_pool = ((new_mem_pool + numBytes + 0x10) & (~((UINT32) 0x0f)));
- mem_pool = (volatile char *) new_mem_pool;
+ /* Now calculate new base of free memory pool (round to >= 16 bytes) */
+ new_mem_pool = (UINT32) mem_pool;
+ new_mem_pool = ((new_mem_pool + numBytes + 0x10) & (~((UINT32) 0x0f)));
+ mem_pool = (volatile char *) new_mem_pool;
- bzero (rtnPtr, numBytes);
+ memset(rtnPtr, 0, numBytes);
- return ((char *) rtnPtr);
-}
-
-
-/* "Poor Man's bzero" - zero's a block of memory. */
-static void bzero (volatile char *ptr, long num_bytes)
-{
-volatile long i; /* loop counter */
-
- /* zero out space */
- for (i = 0; i < num_bytes; *ptr++ = 0, i++)
- ;
+ return ((char *) rtnPtr);
}
/*
* Write "value" to PORT register of PRO/100.
*/
static void portWrite (UINT32 value)
{
- *PORT_REG(adapter[0]) = value;
+ *PORT_REG(adapter[0]) = value;
}
/******************************************************************************
*
@@ -951,131 +846,116 @@ static void portWrite (UINT32 value)
* of the SCB automatically forces the '557 to look at the various data
* structures which make up its interface.
*/
static void sendCommand (UINT8 cuc, UINT8 ruc, UINT32 scb_general_ptr)
{
- register CMD_STAT_U temp_cmdStat;
- volatile union cmdBlock *pBlock = (union cmdBlock *)scb_general_ptr;
- volatile int loop_ctr;
+ register CMD_STAT_U temp_cmdStat;
+ volatile union cmdBlock *pBlock = (union cmdBlock *)scb_general_ptr;
+ volatile int loop_ctr;
- /* Mask adapter interrupts to prevent the interrupt handler from
- playing with the SCB */
- mask_557_ints();
+ /* Mask adapter interrupts to prevent the interrupt handler from
+ playing with the SCB */
+ mask_557_ints();
- /* must wait for the Command Unit to become idle to prevent
+ /* must wait for the Command Unit to become idle to prevent
us from issueing a CU_START to an active Command Unit */
- for (loop_ctr = BUSY_WAIT_LIMIT; loop_ctr > 0; loop_ctr--)
- {
+ for (loop_ctr = BUSY_WAIT_LIMIT; loop_ctr > 0; loop_ctr--) {
if ((pSCB->cmdStat.words.status & SCB_S_CUMASK) == SCB_S_CUIDLE)
break;
}
- if (loop_ctr == 0)
- {
+ if (loop_ctr == 0) {
printf("sendCommand: CU won't go idle, command ignored\n");
- unmask_557_ints();
+ unmask_557_ints();
return;
}
- /* when setting the command word, read the current word from
- the SCB and preserve the upper byte which contains the interrupt
- mask bit */
- temp_cmdStat.words.command = (pSCB->cmdStat.words.command & 0xff00);
- temp_cmdStat.words.status = 0;
-
- /* set up the Command and Receive unit commands */
- temp_cmdStat.bits.cuc = cuc & 0x07;
- temp_cmdStat.bits.ruc = ruc & 0x07;
-
- /* Clear flag */
- waitSem = 0;
-
- /* write the General Pointer portion of the SCB first */
- pSCB->scb_general_ptr = scb_general_ptr;
-
- /* write the Command Word of the SCB */
- pSCB->cmdStat.words.command = temp_cmdStat.words.command;
-
- /* only wait for command which will complete immediately */
- if ((scb_general_ptr != 0/* NULL*/) && (ruc != RU_START))
- {
- /* wait for command acceptance and completion */
- for (loop_ctr = BUSY_WAIT_LIMIT; loop_ctr > 0; loop_ctr--)
- {
- if ((pSCB->cmdStat.bits.cuc == 0) && (pBlock->nop.c == 1))
- break;
- }
- if (loop_ctr == 0)
- {
- printf("sendCommand: Timeout on command complete\n");
- printf("Cmd Complete bit = %02X\n", pBlock->nop.c);
- printf("CU command = 0x%02X\n", cuc);
- printf("RU command = 0x%02X\n", ruc);
- printf("SCB Gen Ptr = 0x%X\n", scb_general_ptr);
- printf("scb status = 0x%04X\n", pSCB->cmdStat.words.status);
- printf("scb command = 0x%04X\n", pSCB->cmdStat.words.command);
- }
+ /* when setting the command word, read the current word from
+ the SCB and preserve the upper byte which contains the interrupt
+ mask bit */
+ temp_cmdStat.words.command = (pSCB->cmdStat.words.command & 0xff00);
+ temp_cmdStat.words.status = 0;
+
+ /* set up the Command and Receive unit commands */
+ temp_cmdStat.bits.cuc = cuc & 0x07;
+ temp_cmdStat.bits.ruc = ruc & 0x07;
+
+ /* Clear flag */
+ waitSem = 0;
+
+ /* write the General Pointer portion of the SCB first */
+ pSCB->scb_general_ptr = scb_general_ptr;
+
+ /* write the Command Word of the SCB */
+ pSCB->cmdStat.words.command = temp_cmdStat.words.command;
+
+ /* only wait for command which will complete immediately */
+ if ((scb_general_ptr != 0/* NULL*/) && (ruc != RU_START)) {
+ /* wait for command acceptance and completion */
+ for (loop_ctr = BUSY_WAIT_LIMIT; loop_ctr > 0; loop_ctr--) {
+ if ((pSCB->cmdStat.bits.cuc == 0) && (pBlock->nop.c == 1))
+ break;
+ }
+ if (loop_ctr == 0) {
+ printf("sendCommand: Timeout on command complete\n");
+ printf("Cmd Complete bit = %02X\n", pBlock->nop.c);
+ printf("CU command = 0x%02X\n", cuc);
+ printf("RU command = 0x%02X\n", ruc);
+ printf("SCB Gen Ptr = 0x%X\n", scb_general_ptr);
+ printf("scb status = 0x%04X\n", pSCB->cmdStat.words.status);
+ printf("scb command = 0x%04X\n", pSCB->cmdStat.words.command);
}
+ }
#if 0
- /* DEBUG */
- printf("scb command = 0x%04X\n", pSCB->cmdStat.words.command);
- printf("scb status = 0x%04X\n", pSCB->cmdStat.words.status);
+ /* DEBUG */
+ printf("scb command = 0x%04X\n", pSCB->cmdStat.words.command);
+ printf("scb status = 0x%04X\n", pSCB->cmdStat.words.status);
#endif
- unmask_557_ints();
- return;
+ unmask_557_ints();
+ return;
}
/*
* Do a port reset on 82557.
*/
-static void resetChip ()
+static void resetChip (void)
{
- portWrite (PORT_RESET); /* bits 4-31 not used for reset */
+ portWrite (PORT_RESET); /* bits 4-31 not used for reset */
- /* wait 5 msec for device to stabilize */
- Wait(5);
+ /* wait 5 msec for device to stabilize */
+ delay_ms(5);
}
/*
* Setup contents of a packet.
*/
static void makePacket (UINT8 *pPacket, int length)
{
-int byteNum; /* Current byte number */
+ int byteNum; /* Current byte number */
- for (byteNum = 0; byteNum < length; byteNum++)
- *pPacket++ = byteNum + ' ';
+ for (byteNum = 0; byteNum < length; byteNum++)
+ *pPacket++ = byteNum + ' ';
}
/*
* Verify contents of a received packet to what was transmitted.
* Returns OK if they match, ERROR if not.
*/
-static int checkPacket (pTxBuffer, pRxBuffer, length)
-UINT8 *pTxBuffer; /* Pointer data that was transmitted */
-UINT8 *pRxBuffer; /* Pointer data that was received */
-int length; /* How many bytes to check */
+static int checkPacket (UINT8 *pTxBuffer, UINT8 *pRxBuffer, int length)
{
-int byteNum; /* Current byte number */
+ int byteNum; /* Current byte number */
-#if 0
- printf ("\n");
- printf ("Transmit Buffer at 0x%08X\n", pTxBuffer);
- printf ("Receive Buffer at 0x%08X\n", pRxBuffer);
-#endif
- for (byteNum = 0; byteNum < length; byteNum++)
- {
- if (*pTxBuffer++ != *pRxBuffer++)
- {
- printf("Error at byte 0x%x\n", byteNum);
- printf("Expected 0x%02X, got 0x%02X\n", *(pTxBuffer - 1), *(pRxBuffer - 1));
- return (ERROR);
- }
+ for (byteNum = 0; byteNum < length; byteNum++) {
+ if (*pTxBuffer++ != *pRxBuffer++) {
+ printf("Error at byte 0x%x\n", byteNum);
+ printf("Expected 0x%02X, got 0x%02X\n", *(pTxBuffer - 1), *(pRxBuffer - 1));
+ return (ERROR);
+ }
}
return (OK);
}
@@ -1085,227 +965,181 @@ int byteNum; /* Current byte number */
* channel attention. It then updates the global status variable
* and gives the semaphore to wake up the main routine.
*/
int i557IntHandler (int arg) /* should return int */
{
-register CMD_STAT_U temp_cmdStat;
-register int rxFlag = FALSE;
+ register CMD_STAT_U temp_cmdStat;
+ register int rxFlag = FALSE;
temp_cmdStat.words.status = pSCB->cmdStat.words.status;
/* check to see if it was the PRO/100 */
- if (temp_cmdStat.words.status & I557_INT)
- {
- /* Wait for command word to clear - indicates no pending commands */
- while (pSCB->cmdStat.words.command)
- ;
+ if (temp_cmdStat.words.status & I557_INT) {
+ /* Wait for command word to clear - indicates no pending commands */
+ while (pSCB->cmdStat.words.command)
+ ;
- /* Update global status variable */
- i557Status = temp_cmdStat.words.status;
+ /* Update global status variable */
+ i557Status = temp_cmdStat.words.status;
-#if 0
- printf ("i557IntHandler: i557Status = 0x%04x\n", i557Status);
-#endif
+ /* If the interrupt was due to a received frame... */
+ if (temp_cmdStat.bits.statack_fr)
+ rxFlag = TRUE;
- /* If the interrupt was due to a received frame... */
- if (temp_cmdStat.bits.statack_fr)
- rxFlag = TRUE;
-
- temp_cmdStat.words.status = temp_cmdStat.words.status & I557_INT;
-
- /* Acknowledge interrupt by setting ack bits */
- pSCB->cmdStat.words.status = temp_cmdStat.words.status;
-
- /* Wait for command word to clear - indicates IACK accepted */
- while (pSCB->cmdStat.words.command)
- ;
+ temp_cmdStat.words.status = temp_cmdStat.words.status & I557_INT;
-#if 0
- /* DEBUG */
- printf ("give waitSem\n");
-#endif
+ /* Acknowledge interrupt by setting ack bits */
+ pSCB->cmdStat.words.status = temp_cmdStat.words.status;
- /* Update global status variable and unblock task */
- waitSem = 1;
+ /* Wait for command word to clear - indicates IACK accepted */
+ while (pSCB->cmdStat.words.command)
+ ;
- if (rxFlag == TRUE)
- rxSem = 1;
+ /* Update global status variable and unblock task */
+ waitSem = 1;
- return(1); /* serviced - return 1 */
- }
-
- return(0); /* nothing serviced - return 0 */
+ if (rxFlag == TRUE)
+ rxSem = 1;
+
+ return(1); /* serviced - return 1 */
+ }
+ return(0); /* nothing serviced - return 0 */
}
/*
* Take the semaphore and block until i557 interrupt or timeout.
* Returns OK if an interrupt occured, ERROR if a timeout.
*/
-static int waitForInt()
+static int waitForInt(void)
{
-int num_ms = 0;
+ int num_ms = 0;
- while ((waitSem == 0) && (num_ms != 2000)) /* wait max 2secs for the interrupt */
- {
- delay_ms(1);
- num_ms++;
- }
-
- if (!waitSem)
- {
- printf("Wait error!\n");
- return (ERROR);
+ while ((waitSem == 0) && (num_ms != 2000)) { /* wait max 2secs for the interrupt */
+ delay_ms(1);
+ num_ms++;
}
- else
- return (OK);
-
+
+ if (!waitSem) {
+ printf("Wait error!\n");
+ return (ERROR);
+ } else
+ return (OK);
}
-static int waitForRxInt()
+static int waitForRxInt(void)
{
-int num_ms = 0;
-
- while ((rxSem == 0) && (num_ms != 2000)) /* wait max 2secs for the interrupt */
- {
- delay_ms(1);
- num_ms++;
- }
+ int num_ms = 0;
- if (!rxSem)
- {
- printf("Rx Wait error!\n");
- return (ERROR);
+ while ((rxSem == 0) && (num_ms != 2000)) { /* wait max 2secs for the interrupt */
+ delay_ms(1);
+ num_ms++;
}
- else
- return (OK);
+
+ if (!rxSem) {
+ printf("Rx Wait error!\n");
+ return (ERROR);
+ } else
+ return (OK);
}
static UINT16 readMDI (int unit, UINT8 phyAdd, UINT8 regAdd)
{
+ register MDI_CONTROL_U mdiCtrl;
+ int num_ms = 0;
-register MDI_CONTROL_U mdiCtrl;
-int num_ms = 0;
+ /* prepare for the MDI operation */
+ mdiCtrl.bits.ready = MDI_NOT_READY;
+ mdiCtrl.bits.intEnab = MDI_POLLED; /* no interrupts */
+ mdiCtrl.bits.op = MDI_READ_OP;
+ mdiCtrl.bits.phyAdd = phyAdd & 0x1f;
+ mdiCtrl.bits.regAdd = regAdd & 0x1f;
+
+ /* start the operation */
+ *MDI_CTL_REG(adapter[unit]) = mdiCtrl.word;
+ /* delay a bit */
+ delay_ms(1);
- /* prepare for the MDI operation */
- mdiCtrl.bits.ready = MDI_NOT_READY;
- mdiCtrl.bits.intEnab = MDI_POLLED; /* no interrupts */
- mdiCtrl.bits.op = MDI_READ_OP;
- mdiCtrl.bits.phyAdd = phyAdd & 0x1f;
- mdiCtrl.bits.regAdd = regAdd & 0x1f;
+ /* poll for completion */
+ mdiCtrl.word = *MDI_CTL_REG(adapter[unit]);
- /* start the operation */
- *MDI_CTL_REG(adapter[unit]) = mdiCtrl.word;
-
- /* delay a bit */
- Wait (1);
-
- /* poll for completion */
+ while ((mdiCtrl.bits.ready == MDI_NOT_READY) && (num_ms != 2000)) { /* wait max 2secs */
mdiCtrl.word = *MDI_CTL_REG(adapter[unit]);
-
- while ((mdiCtrl.bits.ready == MDI_NOT_READY) && (num_ms != 2000)) /* wait max 2secs */
- {
- mdiCtrl.word = *MDI_CTL_REG(adapter[unit]);
- delay_ms(1);
- num_ms++;
- }
+ delay_ms(1);
+ num_ms++;
+ }
- if (num_ms >= 2000)
- {
- printf ("readMDI Timeout!\n");
- return (-1);
- }
- else
- return ((UINT16)mdiCtrl.bits.data);
+ if (num_ms >= 2000) {
+ printf ("readMDI Timeout!\n");
+ return (-1);
+ } else
+ return ((UINT16)mdiCtrl.bits.data);
}
static void writeMDI (int unit, UINT8 phyAdd, UINT8 regAdd, UINT16 data)
{
-
-register MDI_CONTROL_U mdiCtrl;
-int num_ms = 0;
-
+ register MDI_CONTROL_U mdiCtrl;
+ int num_ms = 0;
- /* prepare for the MDI operation */
- mdiCtrl.bits.ready = MDI_NOT_READY;
- mdiCtrl.bits.intEnab = MDI_POLLED; /* no interrupts */
- mdiCtrl.bits.op = MDI_WRITE_OP;
- mdiCtrl.bits.phyAdd = phyAdd & 0x1f;
- mdiCtrl.bits.regAdd = regAdd & 0x1f;
- mdiCtrl.bits.data = data & 0xffff;
+ /* prepare for the MDI operation */
+ mdiCtrl.bits.ready = MDI_NOT_READY;
+ mdiCtrl.bits.intEnab = MDI_POLLED; /* no interrupts */
+ mdiCtrl.bits.op = MDI_WRITE_OP;
+ mdiCtrl.bits.phyAdd = phyAdd & 0x1f;
+ mdiCtrl.bits.regAdd = regAdd & 0x1f;
+ mdiCtrl.bits.data = data & 0xffff;
+
+ /* start the operation */
+ *MDI_CTL_REG(adapter[unit]) = mdiCtrl.word;
- /* start the operation */
- *MDI_CTL_REG(adapter[unit]) = mdiCtrl.word;
+ /* delay a bit */
+ delay_ms(1);
- /* delay a bit */
- Wait (1);
+ /* poll for completion */
+ mdiCtrl.word = *MDI_CTL_REG(adapter[unit]);
- /* poll for completion */
+ while ((mdiCtrl.bits.ready == MDI_NOT_READY) && (num_ms != 2000)) {
mdiCtrl.word = *MDI_CTL_REG(adapter[unit]);
-
- while ((mdiCtrl.bits.ready == MDI_NOT_READY) && (num_ms != 2000))
- {
- mdiCtrl.word = *MDI_CTL_REG(adapter[unit]);
- delay_ms(1);
- num_ms++;
- }
- if (num_ms >= 2000)
- printf ("writeMDI Timeout!\n");
+ delay_ms(1);
+ num_ms++;
+ }
+ if (num_ms >= 2000)
+ printf ("writeMDI Timeout!\n");
- return;
-}
-
-
-static void Wait (int msecs)
-{
- delay_ms(msecs);
+ return;
}
-
-static int get_ether_addr (
- int unit,
- UINT8 *buffer,
- int print_flag /* TRUE to print the information */
- )
+static int get_ether_addr (int unit,
+ UINT8 *buffer,
+ int print_flag) /* TRUE to print the information */
{
- UINT16 temp_node_addr[3] = {0,0,0};
- register int i;
+ UINT16 temp_node_addr[3] = {0,0,0};
+ register int i;
/* Get the adapter's node address */
- if (eeprom_read (adapter[unit],IA_OFFSET,temp_node_addr,3) != OK)
- {
- printf ("Error reading the IA address from Serial EEPROM.\n");
- return (ERROR);
+ if (eeprom_read (adapter[unit],IA_OFFSET,temp_node_addr,3) != OK) {
+ printf ("Error reading the IA address from Serial EEPROM.\n");
+ return (ERROR);
}
buffer[0] = (UINT8)(temp_node_addr[0] & 0x00ff);
buffer[1] = (UINT8)((temp_node_addr[0] & 0xff00)>>8);
buffer[2] = (UINT8)(temp_node_addr[1] & 0x00ff);
buffer[3] = (UINT8)((temp_node_addr[1] & 0xff00)>>8);
buffer[4] = (UINT8)(temp_node_addr[2] & 0x00ff);
buffer[5] = (UINT8)((temp_node_addr[2] & 0xff00)>>8);
- if (print_flag == TRUE)
- {
+ if (print_flag == TRUE) {
printf("Ethernet Address = [ ");
- for (i=0; i<6; i++)
- {
+ for (i=0; i<6; i++) {
printf("0x%02X ", buffer[i]);
}
printf("]\n\n");
}
return (OK);
-}
-
-
-void bcopy(UINT32* src, UINT32* dst, int num_bytes)
-{
-int i;
- for (i = 0; i < num_bytes; i++)
- *dst++ = *src++;
}
Index: hal/arm/xscale/iq80310/current/src/diag/ether_test.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/ether_test.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ether_test.h
--- hal/arm/xscale/iq80310/current/src/diag/ether_test.h 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/ether_test.h 13 Nov 2002 15:41:06 -0000
@@ -90,58 +90,58 @@
/* Individual Address offset into '557's serial eeprom */
#define IA_OFFSET 0
/* Command codes for the command fields of command descriptor blocks */
-#define NOP 0
+#define NOP 0
#define IA_SETUP 1
#define CONFIGURE 2
#define MC_SETUP 3
#define TRANSMIT 4
-#define TDR 5
+#define TDR 5
#define DUMP 6
#define DIAGNOSE 7
/* Commands for CUC in command word of SCB */
-#define CU_NOP 0
-#define CU_START 1
-#define CU_RESUME 2
+#define CU_NOP 0
+#define CU_START 1
+#define CU_RESUME 2
#define LOAD_DUMPCTR_ADDR 4 /* Load Dump Counters Address */
#define DUMP_STAT_COUNTERS 5 /* Dump Statistical Counters */
#define LOAD_CU_BASE 6 /* Load CU Base Register */
#define DUMP_RESET_COUNTERS 7 /* Dump and Reset Statistical
Counters */
/* Commands for RUC in command word of SCB */
-#define RU_NOP 0
-#define RU_START 1
-#define RU_RESUME 2
-#define RU_ABORT 4
-#define LOAD_HDS 5 /* Load Header Data Size */
+#define RU_NOP 0
+#define RU_START 1
+#define RU_RESUME 2
+#define RU_ABORT 4
+#define LOAD_HDS 5 /* Load Header Data Size */
#define LOAD_RU_BASE 6 /* Load RU Base Register */
-#define RBD_RESUME 7 /* Resume frame reception */
+#define RBD_RESUME 7 /* Resume frame reception */
/* Misc. defines */
#define END_OF_LIST 1
#define BUSY 1
/* RU Status field */
-#define RU_IDLE 0x0
+#define RU_IDLE 0x0
#define RU_SUSPENDED 0x1
#define RU_NORESOURCE 0x2
-#define RU_READY 0x4
+#define RU_READY 0x4
#define RU_SUSP_NORBD 0x5
#define RU_NORSRC_NORBD 0x6
#define RU_READY_NORBD 0xc
/* Mask for interrupt status bits in SCB - six possible sources */
#define I557_INT 0xfc00
/* MDI definitions */
-#define MDI_WRITE_OP 0x01
-#define MDI_READ_OP 0x02
-#define MDI_NOT_READY 0
-#define MDI_POLLED 0
+#define MDI_WRITE_OP 0x01
+#define MDI_READ_OP 0x02
+#define MDI_NOT_READY 0
+#define MDI_POLLED 0
#define MDI_DEFAULT_PHY_ADDR 1 /* when only one PHY */
/* PHY device register addresses */
/* generic register addresses */
@@ -182,72 +182,72 @@
#define PHY_ADDR_CON_STATUS (1 << 5)
#define PHY_ADDR_SPEED_10_MBPS (1 << 6)
#define PHY_ADDR_SPEED_100_MBPS (0 << 6)
#define DP83840_LOOPBACK_REG 0x18
-#define TWISTER_LOOPBACK (0x1 << 8)
-#define REMOTE_LOOPBACK (0x2 << 8)
-#define CLEAR_LOOP_BITS ~(TWISTER_LOOPBACK | REMOTE_LOOPBACK)
+#define TWISTER_LOOPBACK (0x1 << 8)
+#define REMOTE_LOOPBACK (0x2 << 8)
+#define CLEAR_LOOP_BITS ~(TWISTER_LOOPBACK | REMOTE_LOOPBACK)
/* 82553 specific register information */
#define I82553_PHY_EXT_REG0 0x10
#define EXT_REG0_100_MBPS (1 << 1)
#define GET_REV_CNTR(n) ((n & 0x00e0) >> 5)
#define I82553_PHY_EXT_REG1 0x14
/* MDI Control Register bits */
-#define MDI_CTRL_COLL_TEST (1 << 7)
+#define MDI_CTRL_COLL_TEST (1 << 7)
#define MDI_CTRL_FULL_DUPLEX (1 << 8)
#define MDI_CTRL_RESTART_AUTO (1 << 9)
-#define MDI_CTRL_ISOLATE (1 << 10)
-#define MDI_CTRL_POWER_DOWN (1 << 11)
-#define MDI_CTRL_AUTO_ENAB (1 << 12)
-#define MDI_CTRL_AUTO_DISAB (0 << 12)
-#define MDI_CTRL_100_MBPS (1 << 13)
-#define MDI_CTRL_10_MBPS (0 << 13)
-#define MDI_CTRL_LOOPBACK (1 << 14)
-#define MDI_CTRL_RESET (1 << 15)
+#define MDI_CTRL_ISOLATE (1 << 10)
+#define MDI_CTRL_POWER_DOWN (1 << 11)
+#define MDI_CTRL_AUTO_ENAB (1 << 12)
+#define MDI_CTRL_AUTO_DISAB (0 << 12)
+#define MDI_CTRL_100_MBPS (1 << 13)
+#define MDI_CTRL_10_MBPS (0 << 13)
+#define MDI_CTRL_LOOPBACK (1 << 14)
+#define MDI_CTRL_RESET (1 << 15)
/* MDI Status Register bits */
-#define MDI_STAT_EXTENDED (1 << 0)
-#define MDI_STAT_JABBER (1 << 1)
-#define MDI_STAT_LINK (1 << 2)
+#define MDI_STAT_EXTENDED (1 << 0)
+#define MDI_STAT_JABBER (1 << 1)
+#define MDI_STAT_LINK (1 << 2)
#define MDI_STAT_AUTO_CAPABLE (1 << 3)
-#define MDI_STAT_REMOTE_FLT (1 << 4)
+#define MDI_STAT_REMOTE_FLT (1 << 4)
#define MDI_STAT_AUTO_COMPLETE (1 << 5)
#define MDI_STAT_10BASET_HALF (1 << 11)
#define MDI_STAT_10BASET_FULL (1 << 12)
-#define MDI_STAT_TX_HALF (1 << 13)
-#define MDI_STAT_TX_FULL (1 << 14)
-#define MDI_STAT_T4_CAPABLE (1 << 15)
+#define MDI_STAT_TX_HALF (1 << 13)
+#define MDI_STAT_TX_FULL (1 << 14)
+#define MDI_STAT_T4_CAPABLE (1 << 15)
/*
* Structure allignments. All addresses passed to the 557 must be
* even (bit 0 = 0), EXCEPT for addresses passed by the PORT*
* function (self-test address & dump address, which must be 16-byte aligned.
*/
#define SELF_TEST_ALIGN 16
-#define DUMP_ALIGN 16
-#define DEF_ALIGN 4
+#define DUMP_ALIGN 16
+#define DEF_ALIGN 4
/*
* Bit definitions for the configure command. NOTE: Byte offsets are
* offsets from the start of the structure (8 and up) to correspond
* with the offsets in the PRO/100 PCI Adapter manual.
*/
/* Byte 0 */
-#define BYTE_COUNT 0x16 /* use all 22 configure bytes */
+#define BYTE_COUNT 0x16 /* use all 22 configure bytes */
#define CONFIG_BYTE_00 (BYTE_COUNT)
/* Byte 1 */
#define RX_FIFO_LIMIT 0x08
#define CONFIG_BYTE_01 (RX_FIFO_LIMIT)
/* Byte 2 */
-#define ADAPT_IFS 0x00
+#define ADAPT_IFS 0x00
#define CONFIG_BYTE_02 (ADAPT_IFS)
/* Byte 3 - must be 0x00 */
#define CONFIG_BYTE_03 (0x00)
@@ -259,16 +259,16 @@
#define TX_DMA_BCOUNT 0x00
#define DMA_BCOUNT_ENAB 0x80
#define CONFIG_BYTE_05 (DMA_BCOUNT_ENAB | TX_DMA_BCOUNT)
/* Byte 6 */
-#define NO_LATE_SCB 0x00
-#define NO_TNO_INT 0x00 /* no interrupt on xmit failure */
-#define INT_CU_IDLE 0x08 /* interrupt when CU goes idle */
+#define NO_LATE_SCB 0x00
+#define NO_TNO_INT 0x00 /* no interrupt on xmit failure */
+#define INT_CU_IDLE 0x08 /* interrupt when CU goes idle */
#define NO_SV_BAD_FRAME 0x00 /* don't save bad frames */
#define DISCARD_RX_OVER 0x00 /* discard overrun frames */
-#define BYTE6_REQUD 0x32 /* required "1" bits */
+#define BYTE6_REQUD 0x32 /* required "1" bits */
#define CONFIG_BYTE_06 (NO_LATE_SCB | NO_TNO_INT | INT_CU_IDLE |\
NO_SV_BAD_FRAME | DISCARD_RX_OVER | BYTE6_REQUD)
/* Byte 7 */
@@ -297,23 +297,23 @@
#define LIN_PRIORITY 0 /* normal CSMA/CD */
#define CONFIG_BYTE_11 (LIN_PRIORITY)
/* Byte 12 */
#define LIN_PRIORITY_MODE 0
-#define IF_SPACING 96 /* inter-frame spacing */
+#define IF_SPACING 96 /* inter-frame spacing */
#define CONFIG_BYTE_12 (IF_SPACING | LIN_PRIORITY_MODE)
/* Byte 13 */
#define CONFIG_BYTE_13 (0x00)
/* Byte 14 */
#define CONFIG_BYTE_14 (0xf2)
/* Byte 15 */
-#define PROM_MODE 0 /* not promiscuous */
-#define BROADCAST 0 /* disabled */
-#define CRS 0x80 /* CDT = carrier */
+#define PROM_MODE 0 /* not promiscuous */
+#define BROADCAST 0 /* disabled */
+#define CRS 0x80 /* CDT = carrier */
#define BYTE15_REQUD 0x48 /* required "1" bits */
#define CONFIG_BYTE_15 (PROM_MODE | BROADCAST | CRS | BYTE15_REQUD)
/* Byte 16 */
#define CONFIG_BYTE_16 (0x00)
@@ -323,18 +323,18 @@
/* Byte 18 */
#define STRIPPING_DISABLE 0x00
#define STRIPPING_ENABLE 0x01
#define PADDING_ENABLE 0x02
-#define XFER_CRC 0x04 /* store CRC */
-#define NO_XFER_CRC 0x00
+#define XFER_CRC 0x04 /* store CRC */
+#define NO_XFER_CRC 0x00
#define BYTE18_REQUD 0xf0 /* required "1" bits */
#define CONFIG_BYTE_18 (NO_XFER_CRC | PADDING_ENABLE | STRIPPING_ENABLE | BYTE18_REQUD)
/* Byte 19 */
#define NO_FORCE_FDX 0x00
-#define FORCE_FDX 0x40
+#define FORCE_FDX 0x40
#define FDX_PIN_ENAB 0x80
#define CONFIG_BYTE_19_10T FORCE_FDX
#define CONFIG_BYTE_19_100T NO_FORCE_FDX
/* Byte 20 */
@@ -576,16 +576,16 @@ struct rfd {
UINT16 length; /* 802.3 packet length (from packet) */
UINT8 rxData[ETHERMTU]; /* optional data (simplified mode) */
};
/* Forward declarations */
-static void portWrite ();
-static void resetChip ();
-static void makePacket ();
-static int checkPacket ();
+static void portWrite (UINT32 val);
+static void resetChip (void);
+static void makePacket (UINT8 *, int);
+static int checkPacket (UINT8 *, UINT8 *, int);
static int i557IntHandler (int);
-static int waitForInt();
+static int waitForInt(void);
static void sendCommand (UINT8 cuc,
UINT8 ruc,
UINT32 scb_general_ptr);
Index: hal/arm/xscale/iq80310/current/src/diag/external_timer.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/external_timer.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 external_timer.c
--- hal/arm/xscale/iq80310/current/src/diag/external_timer.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/external_timer.c 13 Nov 2002 15:41:06 -0000
@@ -46,451 +46,375 @@
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
+#include <redboot.h>
+#include <cyg/hal/hal_iop310.h> // Hardware definitions
+#include <cyg/hal/hal_intr.h> // Interrupt names
#include "iq80310.h"
-
+#include "test_menu.h"
extern int enable_external_interrupt (int int_id);
extern int disable_external_interrupt (int int_id);
-
extern int isr_connect(int int_num, void (*handler)(int), int arg);
extern int isr_disconnect(int int_num);
-
-
-/* 01/05/01 jwf */
-/* extern void _restart_tmr(); */
-
+extern char xgetchar(void);
volatile int timer_ticks;
-
/* interrupt handler for the PAL-based external timer */
void ext_timer_handler (int arg)
{
- /* increment tick counter */
- timer_ticks++;
+ /* increment tick counter */
+ timer_ticks++;
- /* to clear the timer interrupt, clear the timer interrupt
- enable, then re-set the int. enable bit */
-/* 01/05/01 jwf */
-/* _restart_tmr(); */
+ /* to clear the timer interrupt, clear the timer interrupt
+ enable, then re-set the int. enable bit */
+ /* 01/05/01 jwf */
+ /* _restart_tmr(); */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_INT_ENAB();
+ EXT_TIMER_INT_DISAB();
+ EXT_TIMER_INT_ENAB();
- return;
+ return;
}
/* timer count must be written 8 bits at a time */
void write_timer_count (UINT32 count)
{
- UINT8 cnt_word;
+ UINT8 cnt_word;
- /* first ensure that there are only 22 bits of count data */
- count &= 0x003fffff;
+ /* first ensure that there are only 22 bits of count data */
+ count &= 0x003fffff;
- /* grab least significant 8 bits of timer value */
- cnt_word = (UINT8)(count & 0xff);
- *TIMER_LA0_REG_ADDR = cnt_word;
-
- /* grab next 8 bits of timer value */
- count = (count >> 8);
- cnt_word = (UINT8)(count & 0xff);
- *TIMER_LA1_REG_ADDR = cnt_word;
-
- /* grab last 6 bits of timer value */
- count = (count >> 8);
- cnt_word = (UINT8)(count & 0x3f);
- *TIMER_LA2_REG_ADDR = cnt_word;
+ /* grab least significant 8 bits of timer value */
+ cnt_word = (UINT8)(count & 0xff);
+ *TIMER_LA0_REG_ADDR = cnt_word;
+
+ /* grab next 8 bits of timer value */
+ count = (count >> 8);
+ cnt_word = (UINT8)(count & 0xff);
+ *TIMER_LA1_REG_ADDR = cnt_word;
+
+ /* grab last 6 bits of timer value */
+ count = (count >> 8);
+ cnt_word = (UINT8)(count & 0x3f);
+ *TIMER_LA2_REG_ADDR = cnt_word;
- return;
+ return;
}
/* timer must be read 6 bits at a time */
UINT32 read_timer_count (void)
{
- UINT8 timer_cnt0, timer_cnt1, timer_cnt2, timer_cnt3;
- UINT8 timer_byte0, timer_byte1, timer_byte2;
- UINT32 count;
-
- /* first read latches the count */
- timer_cnt0 = (*TIMER_LA0_REG_ADDR & TIMER_COUNT_MASK);
- timer_cnt1 = (*TIMER_LA1_REG_ADDR & TIMER_COUNT_MASK);
- timer_cnt2 = (*TIMER_LA2_REG_ADDR & TIMER_COUNT_MASK);
- timer_cnt3 = (*TIMER_LA3_REG_ADDR & 0xf); /* only 4 bits in most sig. */
-
- /* now build up the count value */
- timer_byte0 = (((timer_cnt0 & 0x20) >> 1) | (timer_cnt0 & 0x1f));
- timer_byte1 = (((timer_cnt1 & 0x20) >> 1) | (timer_cnt1 & 0x1f));
- timer_byte2 = (((timer_cnt2 & 0x20) >> 1) | (timer_cnt2 & 0x1f));
+ UINT8 timer_cnt0, timer_cnt1, timer_cnt2, timer_cnt3;
+ UINT8 timer_byte0, timer_byte1, timer_byte2;
+ UINT32 count;
+
+ /* first read latches the count */
+ timer_cnt0 = (*TIMER_LA0_REG_ADDR & TIMER_COUNT_MASK);
+ timer_cnt1 = (*TIMER_LA1_REG_ADDR & TIMER_COUNT_MASK);
+ timer_cnt2 = (*TIMER_LA2_REG_ADDR & TIMER_COUNT_MASK);
+ timer_cnt3 = (*TIMER_LA3_REG_ADDR & 0xf); /* only 4 bits in most sig. */
+
+ /* now build up the count value */
+ timer_byte0 = (((timer_cnt0 & 0x20) >> 1) | (timer_cnt0 & 0x1f));
+ timer_byte1 = (((timer_cnt1 & 0x20) >> 1) | (timer_cnt1 & 0x1f));
+ timer_byte2 = (((timer_cnt2 & 0x20) >> 1) | (timer_cnt2 & 0x1f));
- count = ((timer_cnt3 << 18) | (timer_byte2 << 12) | (timer_byte1 << 6) |
- timer_byte0);
+ count = ((timer_cnt3 << 18) | (timer_byte2 << 12) | (timer_byte1 << 6) |
+ timer_byte0);
- return (count);
+ return (count);
}
/* 12/18/00 jwf */
/* This test reads the timer la0-la3 registers on the fly while an up count is in progress. */
void counter_test (void)
{
+ /* ff max, b0-b7, b0-b7 contain timer load data */
+ unsigned char TmrLa0Write=0xff;
+ /* ff max, b8-b15, b0-b7 contain timer load data */
+ unsigned char TmrLa1Write=0xff;
+ /* 3f max, b16-b21, b0-b5 contain timer load data */
+ unsigned char TmrLa2Write=0x3f;
+ unsigned char TmrLa3Write=0x00; /* x - don't care */
+ unsigned long int TmrLa0Read=0;
+ unsigned long int TmrLa1Read=0;
+ unsigned long int TmrLa2Read=0;
+ unsigned long int TmrLa3Read=0;
+ unsigned long int temp3=0;
+ unsigned long int temp4=0;
+ unsigned long int CntInit=0;
+ unsigned long int CurrentCount;
+ unsigned long int LastCount = 0;
+ unsigned long int LastLastCount = 0;
+ char Error = FALSE;
+ unsigned long int sample;
+ unsigned long int index;
+ const int MAX_N_PASSES = 10; /* N times the counter shall wrap around */
+ /* N samples to cover the full range of count,
+ 0x3fffff/0x40 = 0xffff <--> 65535d, use 65536 to guarantee
+ a counter wrap around occurs */
+ const unsigned long int MAX_N_SAMPLES = 65536;
+ /* allocate 4 bytes per sample for a 0x0 - 0x3fffff count range to
+ hold contents of registers LA0-LA3 */
+ unsigned long int MAX_N_SIZE = MAX_N_PASSES * MAX_N_SAMPLES * 4;
+ unsigned char *data;
+
+ // Arbitrarily pick a spot in memory.
+ // RedBoot won't ever use more than 1MB.
+ data = (unsigned char *) MEMBASE_DRAM + (1*1024*1024);
- unsigned char TmrLa0Write=0xff; /* ff max, b0-b7, b0-b7 contain timer load data */
- unsigned char TmrLa1Write=0xff; /* ff max, b8-b15, b0-b7 contain timer load data */
- unsigned char TmrLa2Write=0x3f; /* 3f max, b16-b21, b0-b5 contain timer load data */
- unsigned char TmrLa3Write=0x00; /* x - don't care */
-
- unsigned long int TmrLa0Read=0;
- unsigned long int TmrLa1Read=0;
- unsigned long int TmrLa2Read=0;
- unsigned long int TmrLa3Read=0;
-
- unsigned long int temp3=0;
- unsigned long int temp4=0;
-
- unsigned long int CntInit=0;
-
- unsigned long int CurrentCount;
- unsigned long int LastCount;
- unsigned long int LastLastCount;
-
- char Error = FALSE; /* This flag indicates a test pass(FALSE) or fail(TRUE) condition */
-
- unsigned long int sample;
- unsigned long int index;
-
- const int MAX_N_PASSES = 10; /* N times the counter shall wrap around */
- const unsigned long int MAX_N_SAMPLES = 65536; /* N samples to cover the full range of count, 0x3fffff/0x40 = 0xffff <--> 65535d, use 65536 to guarantee a counter wrap around occurs */
- unsigned long int MAX_N_SIZE = MAX_N_PASSES * MAX_N_SAMPLES * 4; /* allocate 4 bytes per sample for a 0x0 - 0x3fffff count range to hold contents of registers LA0-LA3 */
- unsigned char *data;
+ if (data != NULL) {
+ printf("Allocated %d bytes\n", MAX_N_SIZE);
- // Arbitrarily pick a spot in memory.
- // RedBoot won't ever use more than 1MB.
- data = (unsigned char *) MEMBASE_DRAM + (1*1024*1024); /* sample storage area */
-
- if( data != NULL )
- {
- printf( "Allocated %d bytes\n", MAX_N_SIZE );
-
- /* load control data to disable timer enable b0=0 and timer disable interrupt b1=0, write to timer enable port */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
-
- /* write timer la0 port count data */
- *TIMER_LA0_REG_ADDR = TmrLa0Write;
-
- /* write timer la1 port count data */
- *TIMER_LA1_REG_ADDR = TmrLa1Write;
-
- /* write timer la2 port count data */
- *TIMER_LA2_REG_ADDR = TmrLa2Write;
-
- /* write timer la3 port count data */
- *TIMER_LA3_REG_ADDR = TmrLa3Write;
-
- CntInit = TmrLa0Write + (TmrLa1Write << 8 ) + (TmrLa2Write << 16 );
-
- printf("Timer load data = 0x%x\n", CntInit );
-
- printf("Reading Timer registers LA0-LA3 on the fly...\n");
-
- /* load control data to enable timer counter and write control data to start the counter */
- EXT_TIMER_CNT_ENAB();
+ /* load control data to disable timer enable b0=0 and timer disable
+ interrupt b1=0, write to timer enable port */
+ EXT_TIMER_INT_DISAB();
+ EXT_TIMER_CNT_DISAB();
- /* sample the timer counter on the fly and store LA0-3 register contents in an array */
- for ( sample=0, index=0 ; sample < ( MAX_N_PASSES * MAX_N_SAMPLES ) ; sample++, index += 4)
+ /* write timer la0 port count data */
+ *TIMER_LA0_REG_ADDR = TmrLa0Write;
- {
+ /* write timer la1 port count data */
+ *TIMER_LA1_REG_ADDR = TmrLa1Write;
- /* read LSB register first to latch 22 bits data into four la registers */
- data[index] = *TIMER_LA0_REG_ADDR; /* bits 0 1 2 3 4 6 contain count data b0-b5 */
+ /* write timer la2 port count data */
+ *TIMER_LA2_REG_ADDR = TmrLa2Write;
- data[index+1] = *TIMER_LA1_REG_ADDR; /* bits 0 1 2 3 4 6 contain count data b6-b11 */
+ /* write timer la3 port count data */
+ *TIMER_LA3_REG_ADDR = TmrLa3Write;
- data[index+2] = *TIMER_LA2_REG_ADDR; /* bits 0 1 2 3 4 6 contain count data b12-b17 */
+ CntInit = TmrLa0Write + (TmrLa1Write << 8 ) + (TmrLa2Write << 16 );
- data[index+3] = *TIMER_LA3_REG_ADDR; /* bits 0 1 2 3 contain count data b18-b21 */
-
- }
+ printf("Timer load data = 0x%x\n", CntInit );
- printf("Checking for errors...\n" );
+ printf("Reading Timer registers LA0-LA3 on the fly...\n");
- /* Assemble and check recorded register data for errors */
- for ( sample=0, index=0 ; sample < ( MAX_N_PASSES * MAX_N_SAMPLES ) ; sample++, index += 4)
+ /* load control data to enable timer counter and write control data
+ to start the counter */
+ EXT_TIMER_CNT_ENAB();
- {
+ /* sample the timer counter on the fly and store LA0-3 register
+ contents in an array */
+ /* read LSB register first to latch 22 bits data into four la
+ registers */
+ for (sample=0, index=0; sample < (MAX_N_PASSES * MAX_N_SAMPLES); sample++, index += 4) {
+ /* bits 0 1 2 3 4 6 contain count data b0-b5 */
+ data[index] = *TIMER_LA0_REG_ADDR;
+ /* bits 0 1 2 3 4 6 contain count data b6-b11 */
+ data[index+1] = *TIMER_LA1_REG_ADDR;
+ /* bits 0 1 2 3 4 6 contain count data b12-b17 */
+ data[index+2] = *TIMER_LA2_REG_ADDR;
+ /* bits 0 1 2 3 contain count data b18-b21 */
+ data[index+3] = *TIMER_LA3_REG_ADDR;
+ }
- /* Assembles counter data that was read on the fly */
- /* xbxbbbbb */
- /* 01000000 = 0x40 */
- /* 00011111 = 0x1F */
- data[index] &= 0x7f; /* mask all unused bits */
- temp3=data[index];
- temp4=data[index];
- temp3 &= 0x40; /* isolate bit 6 */
- temp3 = temp3 >> 1; /* shift bit 6 to bit 5 */
- temp4 &= 0x1f; /* isolate bits 0-4 */
- TmrLa0Read = temp3 + temp4;
-
- data[index+1] &= 0x7f; /* mask all unused bits */
- temp3=data[index+1];
- temp4=data[index+1];
- temp3 &= 0x40; /* isolate bit 6 */
- temp3 = temp3 >> 1; /* shift bit 6 to bit 5 */
- temp4 &= 0x1f; /* isolate bits 0-4 */
- TmrLa1Read = temp3 + temp4;
-
- data[index+2] &= 0x7f; /* mask all unused bits */
- temp3=data[index+2];
- temp4=data[index+2];
- temp3 &= 0x40; /* isolate bit 6 */
- temp3 = temp3 >> 1; /* shift bit 6 to bit 5 */
- temp4 &= 0x1f; /* isolate bits 0-4 */
- TmrLa2Read = temp3 + temp4;
-
- data[index+3] &= 0x0f; /* mask all unused bits */
- TmrLa3Read = data[index+3];
-
- /* sum timer count data */
- CurrentCount = TmrLa0Read + (TmrLa1Read << 6 ) + (TmrLa2Read << 12 ) + (TmrLa3Read << 18 );
-
- if ( sample == 0 )
- {
- LastLastCount = 0;
- LastCount = CurrentCount;
- }
-
- if (sample == 1 )
-
- {
- LastLastCount = LastCount;
- LastCount = CurrentCount;
- }
-
- if ( sample > 1 ) /* check for data anomaly, is count value read 2 samples ago greater than the count value read 1 sample ago */
- {
- /* print error value (LastCount) positioned in between the previous and current values */
- if ( ( LastLastCount > LastCount ) && ( CurrentCount > LastLastCount ) ) /* show error only, do not show a counter wrap around reading, print error value (LastCount) positioned in between the previous and current values */
- {
- printf("0x%x 0x%x 0x%x \n", LastLastCount, LastCount, CurrentCount );
- Error = TRUE; /* set flag to error condition */
- }
- LastLastCount = LastCount;
- LastCount = CurrentCount;
- }
+ printf("Checking for errors...\n" );
+ /* Assemble and check recorded register data for errors */
+ for (sample=0, index=0; sample < (MAX_N_PASSES * MAX_N_SAMPLES) ;sample++, index += 4) {
+ /* Assembles counter data that was read on the fly */
+ /* xbxbbbbb */
+ /* 01000000 = 0x40 */
+ /* 00011111 = 0x1F */
+ data[index] &= 0x7f; /* mask all unused bits */
+ temp3=data[index];
+ temp4=data[index];
+ temp3 &= 0x40; /* isolate bit 6 */
+ temp3 = temp3 >> 1; /* shift bit 6 to bit 5 */
+ temp4 &= 0x1f; /* isolate bits 0-4 */
+ TmrLa0Read = temp3 + temp4;
+
+ data[index+1] &= 0x7f; /* mask all unused bits */
+ temp3=data[index+1];
+ temp4=data[index+1];
+ temp3 &= 0x40; /* isolate bit 6 */
+ temp3 = temp3 >> 1; /* shift bit 6 to bit 5 */
+ temp4 &= 0x1f; /* isolate bits 0-4 */
+ TmrLa1Read = temp3 + temp4;
+
+ data[index+2] &= 0x7f; /* mask all unused bits */
+ temp3=data[index+2];
+ temp4=data[index+2];
+ temp3 &= 0x40; /* isolate bit 6 */
+ temp3 = temp3 >> 1; /* shift bit 6 to bit 5 */
+ temp4 &= 0x1f; /* isolate bits 0-4 */
+ TmrLa2Read = temp3 + temp4;
+
+ data[index+3] &= 0x0f; /* mask all unused bits */
+ TmrLa3Read = data[index+3];
+
+ /* sum timer count data */
+ CurrentCount = TmrLa0Read + (TmrLa1Read << 6)
+ + (TmrLa2Read << 12) + (TmrLa3Read << 18);
+
+ if (sample == 0) {
+ LastLastCount = 0;
+ LastCount = CurrentCount;
+ }
+
+ if (sample == 1) {
+ LastLastCount = LastCount;
+ LastCount = CurrentCount;
+ }
+
+ /* check for data anomaly, is count value read 2 samples ago
+ greater than the count value read 1 sample ago */
+ if (sample > 1) {
+ /* print error value (LastCount) positioned in between the
+ previous and current values */
+ if (LastLastCount > LastCount && CurrentCount > LastLastCount) {
+ /* show error only, do not show a counter wrap around
+ reading, print error value (LastCount) positioned in
+ between the previous and current values */
+ printf("0x%x 0x%x 0x%x \n", LastLastCount, LastCount, CurrentCount );
+ Error = TRUE; /* set flag to error condition */
}
-
- /* load control data to stop timer b0=0 and reset timer interrupt b1=0 */
- EXT_TIMER_CNT_DISAB();
-
- } /* end if( data != NULL ) */
-
- else /* data = NULL */
- {
- printf( "Cannot allocate memory.\n" );
- }
-
- if ( Error == TRUE )
- {
- printf("Timer LA0-3 register read test FAILED.\n");
- }
- else
- {
- printf("Timer LA0-3 register read test PASSED.\n");
+ LastLastCount = LastCount;
+ LastCount = CurrentCount;
+ }
}
+ /* load control data to stop timer and reset timer interrupt */
+ EXT_TIMER_CNT_DISAB();
+ } else
+ printf( "Cannot allocate memory.\n" );
-} /* end counter_test() */
+ if (Error == TRUE)
+ printf("Timer LA0-3 register read test FAILED.\n");
+ else
+ printf("Timer LA0-3 register read test PASSED.\n");
+}
/* initialize timer for diagnostic use */
-void init_external_timer()
+void init_external_timer(void)
{
+#if 0
+ /* disable timer in case it was running */
+ EXT_TIMER_INT_DISAB();
+ EXT_TIMER_CNT_DISAB();
+
+ timer_ticks = 0;
+
+ /* connect the timer ISR */
+ isr_connect (TIMER_INT_ID, ext_timer_handler, 0);
+
+ /* enable the external interrupt */
+ if (enable_external_interrupt(TIMER_INT_ID) != OK)
+ printf("ERROR enabling EXT TIMER interrupt!\n");
+#else
+ hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
+#endif
- /* disable timer in case it was running */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
-
- timer_ticks = 0;
-
- /* connect the timer ISR */
- isr_connect (TIMER_INT_ID, ext_timer_handler, 0);
-
- /* enable the external interrupt */
- if (enable_external_interrupt(TIMER_INT_ID) != OK)
- printf("ERROR enabling EXT TIMER interrupt!\n");
}
/* uninitialize timer after diagnostics */
-void uninit_external_timer()
+void uninit_external_timer(void)
{
-
- /* disable timer */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
-
- /* disable and disconnect timer interrupts */
- disable_external_interrupt(TIMER_INT_ID);
- isr_disconnect (TIMER_INT_ID);
+#if 0
+ /* disable timer */
+ EXT_TIMER_INT_DISAB();
+ EXT_TIMER_CNT_DISAB();
+
+ /* disable and disconnect timer interrupts */
+ disable_external_interrupt(TIMER_INT_ID);
+ isr_disconnect (TIMER_INT_ID);
+#endif
}
/* 02/02/01 jwf */
/* delay_ms - delay specified number of milliseconds */
void delay_ms(int num_ms)
{
-UINT32 count;
-int num_ticks;
-
- timer_ticks = 0;
-
- if (num_ms < 10)
- num_ticks = 1;
- else
- {
- /* num_ms must be multiple of 10 - round up */
- num_ticks = num_ms / 10;
- if (num_ms % 10)
- num_ticks++; /* round up */
- }
-
- /* for the test we will setup the timer to generate a 10msec tick */
- count = EXT_TIMER_10MSEC_COUNT;
-
- /* write the initial count to the timer */
- write_timer_count (count);
-
- /* enable the interrupt at the timer */
- EXT_TIMER_INT_ENAB();
-
- /* enable the timer to count */
- EXT_TIMER_CNT_ENAB();
-
- while (timer_ticks < num_ticks)
- ;
-
- /* disable timer */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
-
+ HAL_DELAY_US(num_ms * 1000);
}
/* test the 32 bit timer inside the CPLD, U17 */
-void timer_test (void)
+void timer_test (MENU_ARG arg)
{
- volatile int i;
- UINT32 count;
-
+ volatile int i;
+ UINT32 count;
- /***** Perform 10 second count at 100 ticks/sec ****/
+ /***** Perform 10 second count at 100 ticks/sec ****/
- /* for the test we will setup the timer to generate a 10msec tick */
- count = EXT_TIMER_10MSEC_COUNT;
+ /* for the test we will setup the timer to generate a 10msec tick */
+ count = EXT_TIMER_10MSEC_COUNT;
- /* write the initial count to the timer */
- write_timer_count (count);
+ /* write the initial count to the timer */
+ write_timer_count (count);
- /* enable the interrupt at the timer */
- EXT_TIMER_INT_ENAB();
+ /* enable the interrupt at the timer */
+ EXT_TIMER_INT_ENAB();
- /* enable the timer to count */
- EXT_TIMER_CNT_ENAB();
+ /* enable the timer to count */
+ EXT_TIMER_CNT_ENAB();
- printf ("Counting at %d Ticks Per Second.\n", TICKS_10MSEC);
- printf ("Numbers should appear on 1 second increments...\n");
+ printf ("Counting at %d Ticks Per Second.\n", TICKS_10MSEC);
+ printf ("Numbers should appear on 1 second increments...\n");
- for (i = 0; i < 10; i++)
- {
- while (timer_ticks < TICKS_10MSEC)
- ;
- printf ("%d ", i);
- timer_ticks = 0;
- }
+ for (i = 0; i < 10; i++) {
+ while (timer_ticks < TICKS_10MSEC)
+ ;
+ printf ("%d ", i);
+ timer_ticks = 0;
+ }
- printf ("\nDone\n\n");
+ printf ("\nDone\n\n");
- /* disable timer */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
+ /* disable timer */
+ EXT_TIMER_INT_DISAB();
+ EXT_TIMER_CNT_DISAB();
- /***** Perform 10 second count at 200 ticks/sec ****/
+ /***** Perform 10 second count at 200 ticks/sec ****/
- count = EXT_TIMER_5MSEC_COUNT;
- write_timer_count (count);
+ count = EXT_TIMER_5MSEC_COUNT;
+ write_timer_count (count);
- timer_ticks = 0;
+ timer_ticks = 0;
- /* enable the interrupt at the timer */
- EXT_TIMER_INT_ENAB();
+ /* enable the interrupt at the timer */
+ EXT_TIMER_INT_ENAB();
- /* enable the timer to count */
- EXT_TIMER_CNT_ENAB();
+ /* enable the timer to count */
+ EXT_TIMER_CNT_ENAB();
- printf ("Counting at %d Ticks Per Second.\n", TICKS_5MSEC);
- printf ("Numbers should appear on 1 second increments...\n");
+ printf ("Counting at %d Ticks Per Second.\n", TICKS_5MSEC);
+ printf ("Numbers should appear on 1 second increments...\n");
- for (i = 0; i < 10; i++)
- {
- while (timer_ticks < TICKS_5MSEC)
- ;
- printf ("%d ", i);
- timer_ticks = 0;
- }
+ for (i = 0; i < 10; i++) {
+ while (timer_ticks < TICKS_5MSEC)
+ ;
+ printf ("%d ", i);
+ timer_ticks = 0;
+ }
- printf ("\nDone\n\n");
+ printf ("\nDone\n\n");
- /* disable timer */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
+ /* disable timer */
+ EXT_TIMER_INT_DISAB();
+ EXT_TIMER_CNT_DISAB();
-/* 12/18/00 jwf */
- uninit_external_timer(); /* disable interrupt */
- counter_test();
- init_external_timer(); /* enable interrupt */
+ /* 12/18/00 jwf */
+ uninit_external_timer(); /* disable interrupt */
+ counter_test();
+ init_external_timer(); /* enable interrupt */
- printf("\nExternal Timer Test Done\n");
+ printf("\nExternal Timer Test Done\n");
-/* 12/18/00 jwf */
- printf("\n\nStrike <CR> to exit this test." );
- while (xgetchar() != 0x0d);
+ /* 12/18/00 jwf */
+ printf("\n\nStrike <CR> to exit this test." );
+ while (xgetchar() != 0x0d);
- return;
+ return;
} /* end timer_test() */
-
-/* 02/07/01 jwf */
-/* Use the CPLD 22 bit timer to generate a variable delay time */
-/* set up the timer to generate a t msec tick, where ( 0mS < t < 127mS ) */
-/* count=(33MHZ)(t/1 timer interrupt) where ( 0x0 < count <= 0x3fffff ) */
-/* set total number of timer interrupts to num_tmr_int */
-/* generate t(delay)=(count)(num_tmr_int) */
-void time_delay (UINT32 count, volatile int num_tmr_int)
-{
-
- /* write the initial count to the timer */
- write_timer_count (count);
-
- /* enable the interrupt at the timer */
- EXT_TIMER_INT_ENAB();
-
- /* enable the timer to count */
- EXT_TIMER_CNT_ENAB();
-
- /* generate tmr_int timer interrupts */
- while (timer_ticks < num_tmr_int);
-
- timer_ticks = 0;
-
- /* disable timer */
- EXT_TIMER_INT_DISAB();
- EXT_TIMER_CNT_DISAB();
-
-} /* end time_delay() */
Index: hal/arm/xscale/iq80310/current/src/diag/flash.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/flash.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 flash.c
--- hal/arm/xscale/iq80310/current/src/diag/flash.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/flash.c 13 Nov 2002 15:41:06 -0000
@@ -52,72 +52,72 @@
#ifdef CYGPKG_IO_FLASH
#include <cyg/io/flash.h>
#include "iq80310.h" /* 80310 chip set specific */
#include "7_segment_displays.h"
+#include "test_menu.h"
typedef unsigned char FLASH_TYPE;
#define MASK 0xff /* for 1 bank */
/* 28F016S5/28F640J3A Command Definitions - First Bus Cycle */
-#define RESET_CMD (0xffffffff & MASK)
-#define WRITE_TO_BUF_CMD (0xe8e8e8e8 & MASK)
-#define WRITE_CONFIRM_CMD (0xd0d0d0d0 & MASK)
-#define READ_ID_CMD (0x90909090 & MASK)
-#define READ_STAT_REG (0x70707070 & MASK)
-#define CLEAR_STAT_REG (0x50505050 & MASK)
-#define ERASE_CMD (0x20202020 & MASK)
-#define PROGRAM_CMD (0x40404040 & MASK)
-#define BEP_SUSPEND (0xb0b0b0b0 & MASK)
-#define BEP_RESUME (0xd0d0d0d0 & MASK)
-#define LOCK_CMD (0x60606060 & MASK)
+#define RESET_CMD (0xffffffff & MASK)
+#define WRITE_TO_BUF_CMD (0xe8e8e8e8 & MASK)
+#define WRITE_CONFIRM_CMD (0xd0d0d0d0 & MASK)
+#define READ_ID_CMD (0x90909090 & MASK)
+#define READ_STAT_REG (0x70707070 & MASK)
+#define CLEAR_STAT_REG (0x50505050 & MASK)
+#define ERASE_CMD (0x20202020 & MASK)
+#define PROGRAM_CMD (0x40404040 & MASK)
+#define BEP_SUSPEND (0xb0b0b0b0 & MASK)
+#define BEP_RESUME (0xd0d0d0d0 & MASK)
+#define LOCK_CMD (0x60606060 & MASK)
#define CLEAR_LOCK_BIT_SETUP (0x60606060 & MASK) /* 10/06/00 */
/* 28F016S5/28F640J3A Command Definitions - Second Bus Cycle */
-#define ERASE_CONFIRM (0xd0d0d0d0 & MASK)
-#define LOCK_BLOCK_CONFIRM (0x01010101 & MASK)
-#define MASTER_LOCK_CONFIRM (0xf1f1f1f1 & MASK) /* DO NOT EVER set master enable bit!!! */
+#define ERASE_CONFIRM (0xd0d0d0d0 & MASK)
+#define LOCK_BLOCK_CONFIRM (0x01010101 & MASK)
+#define MASTER_LOCK_CONFIRM (0xf1f1f1f1 & MASK) /* DO NOT EVER set master enable bit!!! */
#define UNLOCK_BLOCK_CONFIRM (0xd0d0d0d0 & MASK)
#define CLEAR_LOCK_BIT_CONFIRM (0xd0d0d0d0 & MASK) /* 10/06/00 */
/* Flash category definitions */
#define SECTOR_PROG 0
#define BLOCK_PROG 1
/* status register bits */
-#define WSM_READY (FLASH_TYPE) (1 << 7)
-#define WSM_BUSY (FLASH_TYPE) (0 << 7)
-#define BE_SUSPENDED (FLASH_TYPE) (1 << 6)
-#define BE_COMPLETED (FLASH_TYPE) (0 << 6)
-#define ERASE_UNLOCK_ERROR (FLASH_TYPE) (1 << 5)
+#define WSM_READY (FLASH_TYPE) (1 << 7)
+#define WSM_BUSY (FLASH_TYPE) (0 << 7)
+#define BE_SUSPENDED (FLASH_TYPE) (1 << 6)
+#define BE_COMPLETED (FLASH_TYPE) (0 << 6)
+#define ERASE_UNLOCK_ERROR (FLASH_TYPE) (1 << 5)
#define ERASE_UNLOCK_SUCCESS (FLASH_TYPE) (0 << 5)
#define CLEAR_LOCK_BIT_ERROR (FLASH_TYPE) (1 << 5) /* 10/06/00 */
#define CLEAR_LOCK_BIT_SUCCESS (FLASH_TYPE) (0 << 5) /* 10/06/00 */
-#define PROGRAM_LOCK_ERROR (FLASH_TYPE) (1 << 4)
+#define PROGRAM_LOCK_ERROR (FLASH_TYPE) (1 << 4)
#define PROGRAM_LOCK_SUCCESS (FLASH_TYPE) (0 << 4)
-#define SET_LOCK_BIT_ERROR (FLASH_TYPE) (1 << 4) /* 10/17/00 */
+#define SET_LOCK_BIT_ERROR (FLASH_TYPE) (1 << 4) /* 10/17/00 */
#define SET_LOCK_BIT_SUCCESS (FLASH_TYPE) (0 << 4) /* 10/17/00 */
-#define VPP_LOW_DETECT (FLASH_TYPE) (1 << 3)
-#define VPP_OK (FLASH_TYPE) (0 << 3)
-#define PROGRAM_SUSPENDED (FLASH_TYPE) (1 << 2)
-#define PROGRAM_COMPLETED (FLASH_TYPE) (0 << 2)
-#define DEVICE_PROTECTED (FLASH_TYPE) (1 << 1)
-#define DEVICE_UNLOCKED (FLASH_TYPE) (0 << 1)
+#define VPP_LOW_DETECT (FLASH_TYPE) (1 << 3)
+#define VPP_OK (FLASH_TYPE) (0 << 3)
+#define PROGRAM_SUSPENDED (FLASH_TYPE) (1 << 2)
+#define PROGRAM_COMPLETED (FLASH_TYPE) (0 << 2)
+#define DEVICE_PROTECTED (FLASH_TYPE) (1 << 1)
+#define DEVICE_UNLOCKED (FLASH_TYPE) (0 << 1)
/* Other Intel 28F016S5/28F640J3A definitions */
-#define CMD_SEQ_ERR (FLASH_TYPE) (ERASE_UNLOCK_ERROR | PROGRAM_LOCK_ERROR)
+#define CMD_SEQ_ERR (FLASH_TYPE) (ERASE_UNLOCK_ERROR | PROGRAM_LOCK_ERROR)
#define ALL_FLASH_STATUS (FLASH_TYPE) (0xfe)
-#define UNKNOWN_ERR (FLASH_TYPE) (0xff)
+#define UNKNOWN_ERR (FLASH_TYPE) (0xff)
#define TEST_BUF_LONGS 16384
#define TEST_BUF_CHARS 65536
#define MADE_BY_INTEL (0x89898989 & MASK) /* Manufacturer Code, read at address 0, note that address bit A0 is not used in x8 or x16 mode when obtaining identifier code */
-/*#define I28F016S5 (0xAAAAAAAA & MASK)*/ /* 28F016S5 */
-#define I28F640J3A (0x17171717 & MASK) /* Device Code, read at address 1, note that bit address A0 is not used in x8 or x16 mode when obtaining identifier code */
+#define I28F640J3A (0x17171717 & MASK) /* Device Code, read at address 1, note that bit address A0 is not used in x8 or x16 mode when obtaining identifier code */
/*#define FLASH_BLOCK_SIZE 0x10000*/ /* 28F016S5 */
#define FLASH_BLOCK_SIZE 0x20000 /* 28F640J3A */
#define BLOCK_LOCKED 1
@@ -131,792 +131,250 @@ typedef unsigned char FLASH_TYPE;
unsigned long *flash_buffer = (unsigned long *)0xa1000000;
-extern void _flushICache();
-extern void _enableICache();
-extern void _disableICache();
-extern void _switchMMUpageTables();
-
-
-extern void _usec_delay();
-extern void _msec_delay();
+extern void _flushICache(void);
+extern void _enableICache(void);
+extern void _disableICache(void);
+extern void _switchMMUpageTables(void);
+extern void _usec_delay(void);
+extern void _msec_delay(void);
unsigned long eeprom_size;
unsigned long flash_base;
-ADDR flash_addr=FLASH_ADDR, eeprom_prog_first, eeprom_prog_last;
+ADDR eeprom_prog_first, eeprom_prog_last;
-extern long hexIn();
-extern char * sgets();
+extern long hexIn(void);
+extern char *sgets(char *s);
/* forward declarations */
-void init_eeprom() RAM_FUNC_SECT;
-int reserved_check(ADDR addr, unsigned long length) RAM_FUNC_SECT;
-int is_eeprom(ADDR addr, unsigned long length) RAM_FUNC_SECT;
+void init_eeprom(void) RAM_FUNC_SECT;
int check_eeprom(ADDR addr, unsigned long length) RAM_FUNC_SECT;
-int lock_breeze() RAM_FUNC_SECT;
int check_bstat(int block_num) RAM_FUNC_SECT;
int set_all_lock_bits(void) RAM_FUNC_SECT; /* 10/11/00 added */
int clear_all_lock_bits(ADDR addr) RAM_FUNC_SECT; /* 10/06/00 added */
-int check_erase_unlock(volatile FLASH_TYPE *flash) RAM_FUNC_SECT;
-int check_op_status(int cmd, volatile FLASH_TYPE *flash) RAM_FUNC_SECT;
int erase_eeprom(ADDR addr, unsigned long length) RAM_FUNC_SECT;
-int check_program_lock(volatile FLASH_TYPE *flash) RAM_FUNC_SECT;
int write_eeprom(ADDR start_addr, const void *data_arg, int data_size) RAM_FUNC_SECT;
-void flash_test(void) RAM_FUNC_SECT;
-void delay_and_flush(void) RAM_FUNC_SECT;
-void do_nothing(void) RAM_FUNC_SECT;
+void flash_test(MENU_ARG arg) RAM_FUNC_SECT;
void display_val(int num) RAM_FUNC_SECT;
void display_out (int msb_flag, unsigned char val) RAM_FUNC_SECT;
-void check_lock_bit_status(void) RAM_FUNC_SECT;
#define MSB_DISPLAY_REG (volatile unsigned char *)0xfe840000
#define LSB_DISPLAY_REG (volatile unsigned char *)0xfe850000
void display_out (int msb_flag, unsigned char val)
{
-/* unsigned char *ledPtr; */
- volatile unsigned char *ledPtr;
- unsigned char SevSegDecode;
-
- if (msb_flag) ledPtr = MSB_DISPLAY_REG;
- else ledPtr = LSB_DISPLAY_REG;
-
- switch (val)
- {
- case 0:
- SevSegDecode = ZERO;
- break;
-
- case 1:
- SevSegDecode = ONE;
- break;
-
- case 2:
- SevSegDecode = TWO;
- break;
-
- case 3:
- SevSegDecode = THREE;
- break;
-
- case 4:
- SevSegDecode = FOUR;
- break;
-
- case 5:
- SevSegDecode = FIVE;
- break;
-
- case 6:
- SevSegDecode = SIX;
- break;
-
- case 7:
- SevSegDecode = SEVEN;
- break;
-
- case 8:
- SevSegDecode = EIGHT;
- break;
-
- case 9:
- SevSegDecode = NINE;
- break;
-
- case 10:
- SevSegDecode = LETTER_A;
- break;
-
- case 11:
- SevSegDecode = LETTER_B;
- break;
-
- case 12:
- SevSegDecode = LETTER_C;
- break;
-
- case 13:
- SevSegDecode = LETTER_D;
- break;
-
- case 14:
- SevSegDecode = LETTER_E;
- break;
-
- case 15:
- SevSegDecode = LETTER_F;
- break;
+ volatile unsigned char *ledPtr;
- default:
- SevSegDecode = DECIMAL_POINT;
+ if (msb_flag)
+ ledPtr = MSB_DISPLAY_REG;
+ else
+ ledPtr = LSB_DISPLAY_REG;
- }
- *ledPtr = SevSegDecode;
+ *ledPtr = SevSegDecode[val & 0xf];
}
void display_val (int number)
{
- unsigned char disp_val = number % 256;
- unsigned char msb, lsb;
-
- lsb = disp_val & 0x0f;
- msb = (disp_val & 0xf0) >> 4;
-
- display_out (0, lsb);
- display_out (1, msb);
-}
-
-/* Used in write to buffer routine */
-void do_nothing (void)
-{
-
- volatile int i;
- for (i = 0; i < 50; i++); /* Rev 2.0B and Rev 2.0C */
-/* for (i = 0; i < 100; i++); */ /* Rev 2.0A */
-}
-
-
-void delay_and_flush (void)
-{
+ unsigned char disp_val = number % 256;
+ unsigned char msb, lsb;
- do_nothing();
-
- _flushICache();
+ lsb = disp_val & 0x0f;
+ msb = (disp_val & 0xf0) >> 4;
+ display_out (0, lsb);
+ display_out (1, msb);
}
-
/********************************************************/
-/* INIT FLASH */
-/* */
+/* INIT FLASH */
+/* */
/* This routine initializes the variables for timing */
/* with any board configuration. This is used to get */
-/* exact timing every time. */
+/* exact timing every time. */
/********************************************************/
-
-void init_eeprom()
+void init_eeprom(void)
{
-#if 1
- unsigned char MfgCode=MADE_BY_INTEL;
- unsigned char DevCode=I28F640J3A;
-
- eeprom_size = 0x800000;
-#else
- unsigned char MfgCode=0;
- unsigned char DevCode=0;
-
- flash_addr = FLASH_ADDR;
-
- flash_base = FLASH_BASE_ADDR;
-
- /* Set defaults */
- eeprom_size = 0;
+ unsigned char MfgCode=MADE_BY_INTEL;
+ unsigned char DevCode=I28F640J3A;
- /* Note: the PCI-700 platform has only 1 memory bank */
+ eeprom_size = 0x800000;
-/*
- *( volatile unsigned char * ) FLASH_BASE_ADDR = RESET_CMD;
- printf( "Wrote 1rst Read Array Command\n");
-*/
-
- *FLASH_P2V(FLASH_BASE_ADDR) = RESET_CMD; /* issue read array command */
- delay_and_flush(); /* wait for Flash to re-enter Read Array mode */
-
-
- *FLASH_P2V(FLASH_BASE_ADDR) = READ_ID_CMD; /* issue read id command */
-
- MfgCode = *FLASH_P2V(FLASH_BASE_ADDR); /* read a manufacturer code at addr 0, address bit A0 is not used */
-
- DevCode = *FLASH_P2V(DEV_CODE_ADDR); /* read a device code at addr 1 */
-
- if (MfgCode == (MADE_BY_INTEL))
- {
- switch ( DevCode ) /* device code stored in addr 1, address bit A0 is not used, must shift 0x00000001<<1=0x00000002 */
- {
- case I28F640J3A:
- eeprom_size += 0x800000 * FLASH_WIDTH; /* I28F640J3A */
- break;
- default:
- break;
- }
- }
-
- *FLASH_P2V(FLASH_BASE_ADDR) = READ_ID_CMD; /* issue 2nd read id command */
-
- *FLASH_P2V(FLASH_BASE_ADDR) = RESET_CMD; /* issue read array command */
-
- delay_and_flush(); /* wait for Flash to re-enter Read Array mode */
-#endif
-
- printf( "\nManufacturer Code = 0x%x\n", MfgCode);
- printf( "Device Code = %x\n", DevCode);
- printf( "Flash Memory size = 0x%x\n", eeprom_size);
+ printf( "\nManufacturer Code = 0x%x\n", MfgCode);
+ printf( "Device Code = %x\n", DevCode);
+ printf( "Flash Memory size = 0x%x\n", eeprom_size);
return;
}
/********************************************************/
-/* RESERVED AREA CHECK */
-/* */
-/* returns TRUE if the address falls into the */
-/* reserved system area */
-/* returns FALSE if the address is outside */
-/* the reserved system area */
-/********************************************************/
-int reserved_check(ADDR addr, unsigned long length)
-{
-
- /* check start address */
- if ( ( addr >= RESERVED_AREA1 ) && ( addr <= ( FLASH_BLK4_BASE_ADDR - 1 ) ) )
- return TRUE;
-
-
- /* must be outside the area */
- else
- return FALSE;
-}
-
-/********************************************************/
-/* IS EEPROM */
-/* Check if memory is Flash */
-/* */
-/* returns TRUE if it is; FALSE if not eeprom ; */
-/* returns ERROR bad addr or partial eeprom */
-/* */
-/********************************************************/
-int is_eeprom(ADDR addr, unsigned long length)
-{
- ADDR eeprom_end = flash_addr + eeprom_size - 1;
- ADDR block_end = addr + length - 1;
-
- /* Check for wrap: if the address and length given wrap past
- * the end of memory, it is an error. */
- if (block_end < addr)
- return ERR;
- if (addr >= flash_addr && block_end <= eeprom_end)
- return TRUE;
- if (addr > eeprom_end || block_end < flash_addr)
- return FALSE;
- /* If the block was partly within the Flash, it is an error. */
- return ERR;
-}
-
-
-/********************************************************/
-/* CHECK EEPROM */
-/* Check if Flash is Blank */
-/* */
+/* CHECK EEPROM */
+/* Check if Flash is Blank */
+/* */
/* returns OK if it is; returns ERROR and sets cmd_stat */
/* to an error code if memory region is not Flash or if */
-/* it is not blank. */
-/* */
+/* it is not blank. */
+/* */
/********************************************************/
int check_eeprom(ADDR addr, unsigned long length)
{
-
FLASH_TYPE *p, *end;
- if (eeprom_size == 0)
- {
- cmd_stat = E_NO_FLASH;
- return ERR;
- }
-
- if (addr == NO_ADDR)
- {
- addr = FLASH_BLK4_BASE_ADDR; /* start at base address of block */
-
- length = eeprom_size - RESERVED_AREA_SIZE;
+ if (eeprom_size == 0) {
+ cmd_stat = E_NO_FLASH;
+ return ERR;
+ }
+
+ if (addr == NO_ADDR) {
+ addr = FLASH_BLK4_BASE_ADDR; /* start at base address of block */
+ length = eeprom_size - RESERVED_AREA_SIZE;
+ } else if (length == 0)
+ length = 1;
+
+ p = (FLASH_TYPE *)addr;
+
+ end = (FLASH_TYPE *)FLASH_TOP_ADDR;
+ /* search for first non blank address starting at base address of Flash Block 2 */
+ while (p != end) {
+ if (*FLASH_P2V(p) != 0xff) {
+ eeprom_prog_first = (ADDR)p; /* found first non blank memory cell */
+
+ /* now find last non blank memory cell starting from top of Flash memory */
+ for (p = end - 1; *FLASH_P2V(p) == 0xff; --p)
+ ;
+ eeprom_prog_last = (ADDR)p; /* found last non blank memory cell */
+
+ cmd_stat = E_EEPROM_PROG;
- }
- else if (length == 0)
- length = 1;
-
-/* Original */
-/* if (is_eeprom(addr, length) != 1) */
-/*
- if (is_eeprom(addr, length) != TRUE)
- {
- cmd_stat = E_EEPROM_ADDR;
- return ERR;
- }
-*/
-
- p = (FLASH_TYPE *)addr;
-
-/* Original */
-/* end = p + length; */
- /* find first non_blank address */
-/* while (p != end) */
-/* { */
-/* if (*p != 0xff) */
-/* { */
-/* cmd_stat = E_EEPROM_PROG; */
-/* eeprom_prog_first = (ADDR)p; */
-
- /* find last non_blank address */
-/* for (p = end; *--p == 0xff; ); */
-/* eeprom_prog_last = (ADDR)p; */
-/* return ERR; */
-/* } */
-/* p++; */
-/* } */
-/* return OK; */
-
- end = (FLASH_TYPE *)FLASH_TOP_ADDR;
- /* search for first non blank address starting at base address of Flash Block 2 */
- while (p != end)
- {
- if (*FLASH_P2V(p) != 0xff)
- {
-
- eeprom_prog_first = (ADDR)p; /* found first non blank memory cell */
-
- /* now find last non blank memory cell starting from top of Flash memory */
- for (p = end - 1; *FLASH_P2V(p) == 0xff; --p);
-
- eeprom_prog_last = (ADDR)p; /* found last non blank memory cell */
-
- cmd_stat = E_EEPROM_PROG;
-
- return ERR;
+ return ERR;
}
- p++;
- }
- return OK;
-}
-
-/********************************************************/
-/* LOCK BREEZE FLASH AREA */
-/* */
-/* Lock the Flash ROM blocks which contain the Breeze */
-/* Development environment to prevent inadvertent */
-/* erasure/reprogramming. */
-/* */
-/* RETURNS: 1 = success, 0 = failure */
-/********************************************************/
-int lock_breeze()
-{
- void *err_addr;
-
- if (flash_lock((void *)BREEZE_BLOCK_0, NUM_BREEZE_BLOCKS*FLASH_BLOCK_SIZE, (void **)&err_addr) != 0) {
- cmd_stat = E_EEPROM_FAIL;
- return (BLOCK_UNLOCKED);
- }
- return(BLOCK_LOCKED);
-}
-
-
-/********************************************************/
-/* CHECK BLOCK STATUS */
-/* */
-/* Check the lock status of a flash block */
-/* */
-/* Input: block number to check */
-/* -1 = master lock */
-/* */
-/* Returns: 1 = locked, 0 = unlocked */
-/* 2 = invalid block number */
-/********************************************************/
-#if 0
-int check_bstat(int block_num)
-{
- volatile FLASH_TYPE *lock_data_addr;
- FLASH_TYPE lock_data;
-
- /* shut the compiler up */
- lock_data_addr = 0x00000000;
-
- /* derive the address for block lock configuration data */
- if ((block_num >= 0) && (block_num <= NUM_FLASH_BLOCKS))
- lock_data_addr = (FLASH_TYPE*)(FLASH_ADDR + (FLASH_BLOCK_SIZE * block_num) + 2);
- else if (block_num == -1)
- lock_data_addr = (FLASH_TYPE*)(FLASH_ADDR + 3);
- else
- return (2);
-
- lock_data_addr = FLASH_P2V(lock_data_addr);
-
- /* read block lock configuration data from address */
- *lock_data_addr = READ_ID_CMD;
-
- lock_data = *lock_data_addr;
-
- /* reset flash to read mode */
- *lock_data_addr = RESET_CMD;
- delay_and_flush(); /* wait for Flash to re-enter Read Array mode */
-
- /* now check data to see if block is indeed locked */
- if (lock_data & BLOCK_LOCKED)
- return (BLOCK_LOCKED);
- else
- return (BLOCK_UNLOCKED);
-}
-#endif
-
-/********************************************************/
-/* CHECK ERASE OR UNLOCK STATUS */
-/* */
-/* Check the status of erase or unlock operation */
-/* using the Status Register of the Flash */
-/* */
-/* Returns: OK - Erase successful */
-/* VPP_LOW_DETECT - Vpp low detected */
-/* ERASE_UNLOCK_ERROR - Erase / Unlock error */
-/* CMD_SEQ_ERR - Command sequencing error */
-/* UNKNOWN_ERR - Unknown error condition */
-/* */
-/********************************************************/
-#if 0
-int check_erase_unlock(volatile FLASH_TYPE *flash)
-{
- FLASH_TYPE stat;
- flash = FLASH_P2V(flash);
- *flash = READ_STAT_REG ;
- stat = *flash;
-
- /* poll and wait for Write State Machine Ready */
- while ((stat & WSM_READY) == WSM_BUSY)
- {
- stat = *flash;
- }
-
- /* now check completion status */
- if (stat & VPP_LOW_DETECT)
- {
- *flash = CLEAR_STAT_REG;
- return VPP_LOW_DETECT;
- }
- if ((stat & CMD_SEQ_ERR) == CMD_SEQ_ERR)
- {
- *flash = CLEAR_STAT_REG;
- return CMD_SEQ_ERR;
+ p++;
}
- if (stat & ERASE_UNLOCK_ERROR)
- {
- *flash = CLEAR_STAT_REG;
- return ERASE_UNLOCK_ERROR;
- }
- if ((stat & ALL_FLASH_STATUS) == WSM_READY)
- {
- *flash = CLEAR_STAT_REG;
- return OK;
- }
- else
- {
- *flash = CLEAR_STAT_REG;
- return UNKNOWN_ERR;
- }
-}
-#endif
-
-/********************************************************/
-/* CHECK OPERATION STATUS */
-/* */
-/* Check the status of an operation */
-/* using the Status Register of the Flash */
-/* */
-/* if the "cmd" argument flag is TRUE, then a */
-/* READ_STAT_REG command should be issued first */
-/* */
-/* Returns: */
-/* OK - Operation successful */
-/* value of Status register - Otherwise */
-/* */
-/********************************************************/
-#if 0
-int check_op_status(int cmd, volatile FLASH_TYPE *flash)
-{
- FLASH_TYPE stat;
-
- flash = FLASH_P2V(flash);
-
- if (cmd == TRUE)
- {
- *flash = READ_STAT_REG;
- }
-
- stat = *flash;
-
- /* poll and wait for Write State Machine Ready */
- while ((stat & WSM_READY) == WSM_BUSY)
- {
- stat = *flash;
- }
-
- /* now check completion status */
- if ((stat & ALL_FLASH_STATUS) == WSM_READY)
- {
- *flash = CLEAR_STAT_REG;
- return OK;
- }
- else
- {
- *flash = CLEAR_STAT_REG;
- return stat;
- }
-}
-#endif
-
-#if 0
-/* used for debugging only */
-/* check block lock configuration and display status of 64 blocks, 1=locked, 0=unlocked */
-void check_lock_bit_status (void)
-{
-
- int block;
-
- volatile FLASH_TYPE *block_addr;
-
- /* address bit A0 is not used when obtaining identifier codes */
-
-/* 11/01/00 */
-/* unsigned long addr = 0x2<<1; */
- unsigned long addr = 0x4;
-
- unsigned char block_lock_status[64];
-
- block_addr = (volatile FLASH_TYPE *) addr;
-
-/* printf("Checking lock status of %d blocks, 1=locked, 0=unlocked...\n", block ); */
-
- /* address bit A0 is not used when obtaining identifier codes */
- for (block=0; block<=63; block++)
- {
-
- *FLASH_P2V(block_addr) = READ_ID_CMD;
-
- block_lock_status[block] = *FLASH_P2V(block_addr);
-
- *FLASH_P2V(block_addr) = RESET_CMD;
-
- do_nothing();
-
-/* 11/01/00 */
- do_nothing();
-
- block_lock_status[block] &= 0x01; /* Checking lock status of block, 1=locked, 0=unlocked */
-
- block_addr = (volatile FLASH_TYPE *)((unsigned long)block_addr + (unsigned long)FLASH_BLOCK_SIZE); /* block address offset for byte wide data storage */
- }
-
-
- for (block=0; block<=63; block++)
- {
- if (block == 32)
- {
- printf("\n\r");
- }
- printf("%d ", block_lock_status[block] );
- }
- printf("\nDone!\n\n" );
-
-/** return; **/
+ return OK;
}
-#endif
/********************************************************/
-/* SET ALL LOCK BITS */
-/* */
+/* SET ALL LOCK BITS */
+/* */
/* returns OK if successful; otherwise returns ERROR */
-/* and sets cmd_stat to an error code */
+/* and sets cmd_stat to an error code */
/* The 28F640J3A is divided into 64, 128Kbyte blocks */
/* This routine sets a lock bit in the block specified */
-/* by a given address */
+/* by a given address */
/********************************************************/
int set_all_lock_bits()
{
- unsigned long addr = 0x0;
+ unsigned long addr = 0x0;
void *err_addr;
- int stat;
+ int stat;
- if ((stat = flash_lock((void *)addr, 4 * FLASH_BLOCK_SIZE, (void **)&err_addr)) != 0) {
- return stat;
- }
- return( OK );
+ if ((stat = flash_lock((void *)addr, 4 * FLASH_BLOCK_SIZE, (void **)&err_addr)) != 0)
+ return stat;
+
+ return( OK );
}
/********************************************************/
-/* CLEAR ALL LOCK BITS */
-/* */
+/* CLEAR ALL LOCK BITS */
+/* */
/* returns OK if successful; otherwise returns ERROR */
-/* and sets cmd_stat to an error code */
+/* and sets cmd_stat to an error code */
/* The 28F640J3A is divided into 64, 128Kbyte blocks */
-/* This routine clears all block lock bits */
+/* This routine clears all block lock bits */
/********************************************************/
int clear_all_lock_bits(ADDR addr)
{
void *err_addr;
- int stat;
+ int stat;
if ((stat = flash_unlock((void *)0, eeprom_size, (void **)&err_addr)) != 0)
- return stat;
- return OK;
+ return stat;
+ return OK;
}
/********************************************************/
-/* ERASE EEPROM */
-/* */
-/* returns OK if erase was successful, */
-/* otherwise returns ERROR */
-/* and sets cmd_stat to an error code */
-/* */
+/* ERASE EEPROM */
+/* */
+/* returns OK if erase was successful, */
+/* otherwise returns ERROR */
+/* and sets cmd_stat to an error code */
+/* */
/********************************************************/
int erase_eeprom(ADDR addr, unsigned long length)
{
void *err_addr;
- int num_blocks;
-
- /********************************************************/
- /* The 28F640J3A is divided into 64, 128Kbyte blocks */
- /* each of which must be individually erased. */
- /* This routine and erases a whole number of blocks */
- /********************************************************/
-
- /* don't erase boot area even if entire eeprom is specified */
- if (addr == NO_ADDR)
- {
- /* 10/06/00 *//* Original */
- /*addr = flash_addr;*/
- addr = FLASH_BLK4_BASE_ADDR;
+ int num_blocks;
- length = eeprom_size - RESERVED_AREA_SIZE;
- }
-
- /* Original */
- /* check for reserved area if one is used */
- /* check to see if the address is within the reserved area */
-/*
- if (reserved_check(addr, length) == TRUE)
- {
- cmd_stat = E_EEPROM_ADDR;
-
- return ERR;
- }
-*/
-
-
- if (length == 0)
- {
-
- /* 10/06/00 */
- printf( "erase_eeprom, return OK, length=0\n");
-
- return OK;
- }
+ /********************************************************/
+ /* The 28F640J3A is divided into 64, 128Kbyte blocks */
+ /* each of which must be individually erased. */
+ /* This routine and erases a whole number of blocks */
+ /********************************************************/
+
+ /* don't erase boot area even if entire eeprom is specified */
+ if (addr == NO_ADDR) {
+ addr = FLASH_BLK4_BASE_ADDR;
+ length = eeprom_size - RESERVED_AREA_SIZE;
+ }
+
+ if (length == 0) {
+ /* 10/06/00 */
+ printf( "erase_eeprom, return OK, length=0\n");
+ return OK;
+ }
- /* start address must be block-aligned */
- if ((addr % FLASH_BLOCK_SIZE) != 0)
- {
- cmd_stat = E_EEPROM_ADDR;
-
- printf( "erase_eeprom, addr = 0x%x\n", addr);
- printf( "erase_eeprom, FLASH_BLOCK_SIZE = 0x%x\n", FLASH_BLOCK_SIZE);
- printf( "erase_eeprom, return ERR, (addr %% FLASH_BLOCK_SIZE) = %d\n", addr % FLASH_BLOCK_SIZE);
+ /* start address must be block-aligned */
+ if ((addr % FLASH_BLOCK_SIZE) != 0) {
+ cmd_stat = E_EEPROM_ADDR;
+ printf( "erase_eeprom, addr = 0x%x\n", addr);
+ printf( "erase_eeprom, FLASH_BLOCK_SIZE = 0x%x\n", FLASH_BLOCK_SIZE);
+ printf( "erase_eeprom, return ERR, (addr %% FLASH_BLOCK_SIZE) = %d\n", addr % FLASH_BLOCK_SIZE);
- return ERR;
- }
+ return ERR;
+ }
/* figure out how many blocks require erasure - round up using integer division */
- if (length % FLASH_BLOCK_SIZE) /* non-multiple, round up */
- num_blocks = (length + FLASH_BLOCK_SIZE) / FLASH_BLOCK_SIZE;
- else /* multiple number of blocks */
- num_blocks = length / FLASH_BLOCK_SIZE;
-
- if (eeprom_size == 0)
- {
- cmd_stat = E_NO_FLASH;
- return ERR;
- }
+ if (length % FLASH_BLOCK_SIZE) /* non-multiple, round up */
+ num_blocks = (length + FLASH_BLOCK_SIZE) / FLASH_BLOCK_SIZE;
+ else /* multiple number of blocks */
+ num_blocks = length / FLASH_BLOCK_SIZE;
- /* Original */
- /* If it's already erased, don't bother */
- /*if (check_eeprom(addr, length) == OK)*/
- /* return OK;*/
- /* check_bstat(int block_num); */
-
- if (flash_erase((void *)addr, num_blocks * FLASH_BLOCK_SIZE, (void **)&err_addr) != 0) {
- cmd_stat = E_EEPROM_FAIL;
- return ERR;
- }
-
- return OK;
-}
-
-
-/********************************************************/
-/* CHECK PROGRAM OR LOCK STATUS */
-/* */
-/* Check the status of program or lock operations */
-/* using the Status Register of the Flash */
-/* */
-/* Returns: OK - Write successful */
-/* VPP_LOW_DETECT - Vpp low detected */
-/* PROGRAM_LOCK_ERROR - Write error */
-/* UNKNOWN_ERR - Unknown error condition */
-/* */
-/********************************************************/
-#if 0
-int check_program_lock(volatile FLASH_TYPE *flash)
-{
- FLASH_TYPE stat;
- flash = FLASH_P2V(flash);
- *flash = READ_STAT_REG;
- stat = *flash;
-
- /* poll and wait for Write State Machine Ready */
- while (!(stat & WSM_READY))
- stat = *flash;
-
- /* now check completion status */
- if (stat & VPP_LOW_DETECT)
- {
- *flash = CLEAR_STAT_REG;
- return VPP_LOW_DETECT;
+ if (eeprom_size == 0) {
+ cmd_stat = E_NO_FLASH;
+ return ERR;
}
- if (stat & PROGRAM_LOCK_ERROR)
- {
- *flash = CLEAR_STAT_REG;
- return PROGRAM_LOCK_ERROR;
+ if (flash_erase((void *)addr, num_blocks * FLASH_BLOCK_SIZE, (void **)&err_addr) != 0) {
+ cmd_stat = E_EEPROM_FAIL;
+ return ERR;
}
- if ((stat & ALL_FLASH_STATUS) == (WSM_READY | PROGRAM_LOCK_SUCCESS))
- {
- *flash = CLEAR_STAT_REG;
- return OK;
- }
- else
- {
- *flash = CLEAR_STAT_REG;
- return UNKNOWN_ERR;
- }
+ return OK;
}
-#endif
+
/********************************************************/
-/* WRITE EEPROM */
-/* */
+/* WRITE EEPROM */
+/* */
/* returns OK if successful; otherwise returns ERROR */
-/* and sets cmd_stat to an error code */
-/* */
+/* and sets cmd_stat to an error code */
+/* */
/********************************************************/
int
write_eeprom(ADDR start_addr, const void *data_arg, int data_size)
{
void *err_addr;
- if (flash_program(start_addr, data_arg, data_size, &err_addr) != 0) {
- cmd_stat = E_EEPROM_FAIL;
- return ERR;
- }
- return OK;
+ if (flash_program((void *)start_addr, data_arg, data_size, &err_addr) != 0) {
+ cmd_stat = E_EEPROM_FAIL;
+ return ERR;
+ }
+ return OK;
}
/*****************************************************************************
*
@@ -927,76 +385,25 @@ write_eeprom(ADDR start_addr, const void
* from the System code or from the Factory code (can't write over MON960).
*
* This test basically does a Longword Address test to the Flash area.
*
*/
-void flash_test(void)
+void flash_test(MENU_ARG arg)
{
- ADDR start_addr = (ADDR)flash_addr; /* Original */
+ ADDR start_addr = (ADDR)FLASH_ADDR; /* Original */
int i;
- unsigned long *f_ptr = (unsigned long *)flash_addr;
+ unsigned long *f_ptr = (unsigned long *)FLASH_ADDR;
int bytes_written = 0;
unsigned long flash_data;
char answer[20];
/* 10/31/00 */
- int status;
+ int status;
-#if 0
- printf ("Disabling Instruction Cache... ");
- _disableICache(); /* disable instruction cache */
- printf ("Done\n\n");
-
- /* switch the MMU over to use RAM-based page table entries */
- printf ("Switching MMU to RAM-based page table... ");
- _switchMMUpageTables();
- printf ("Done\n\n");
-#endif
-
-
-/* 10/31/00 */
-/*
- check_lock_bit_status();
-
- printf ("Setting Block Lock Bits... \n");
- printf("Do you wish to continue? (y/n)\n");
- sgets(answer);
- printf("\n");
- if ((answer[0] != 'y') && (answer[0] != 'Y'))
- return;
- if( (status = set_all_lock_bits() ) == OK )
- printf("Done!\n");
- else
- {
- printf("Error!\n");
- printf( "error status = 0x%x\n", status );
- }
-
- check_lock_bit_status();
-
- printf ("\nClearing Block Lock Bits... \n");
- printf("Do you wish to continue? (y/n)\n");
- sgets(answer);
- printf("\n");
- if ((answer[0] != 'y') && (answer[0] != 'Y'))
- return;
- if( ( status=clear_all_lock_bits(NO_ADDR) ) == OK )
- printf("Done!\n");
- else
- {
- printf("Error!\n");
- printf( "error status = 0x%x\n", status );
- }
-
- check_lock_bit_status();
-*/
-/* 10/31/00 */
-
-
- init_eeprom();
+ init_eeprom();
printf("***********************************\n");
printf("*** WARNING ***\n");
printf("*** This test is destructive to ***\n");
printf("*** all contents of the FLASH! ***\n");
@@ -1004,154 +411,121 @@ void flash_test(void)
printf("\nDo you wish to continue? (y/n)\n");
sgets(answer);
printf("\n\n");
if ((answer[0] != 'y') && (answer[0] != 'Y'))
- return;
-
+ return;
- printf ("FLASH begins at 0x%X\n", flash_addr);
+ printf ("FLASH begins at 0x%X\n", FLASH_ADDR);
printf ("Total FLASH size = 0x%X\n\n", eeprom_size);
-
printf ("Checking FLASH ...\n");
if (check_eeprom(NO_ADDR, 0) == OK)
printf("FLASH is erased\n\n");
else
- {
printf("FLASH is programmed between 0x%X and 0x%X\n\n",
eeprom_prog_first, eeprom_prog_last);
- }
-
printf ("\nClearing Block Lock Bits... \n");
- if(clear_all_lock_bits(NO_ADDR)==OK)
+ if(clear_all_lock_bits(NO_ADDR)==OK)
printf("Done!\n\n");
- else
+ else
printf("Error!\n\n");
-/* check_lock_bit_status(); */
-
printf ("Erasing FLASH...\n");
if (erase_eeprom(NO_ADDR, 0) != OK)
printf("Error on erase_eeprom()\n\n");
else
printf("Done Erasing FLASH!\n\n");
- (ADDR)flash_addr = FLASH_BLK4_BASE_ADDR;
- (ADDR)start_addr = (ADDR)flash_addr;
+ (ADDR)start_addr = (ADDR)FLASH_BLK4_BASE_ADDR;
printf ("Writing Longword Data to FLASH...\n");
/* write to all of available Flash ROM. Don't do this thousands of times
- since the Flash has only 100,000 write cycles in its lifespan */
+ since the Flash has only 100,000 write cycles in its lifespan */
- while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE))
- {
- flash_data = (unsigned long)start_addr;
- for (i=0; i<TEST_BUF_LONGS; i++)
- {
+ while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE)) {
+ flash_data = (unsigned long)start_addr;
+ for (i=0; i<TEST_BUF_LONGS; i++) {
flash_buffer[i] = flash_data; /* put address in buffer */
- flash_data += 4; /* increment address */
- }
- if (write_eeprom (start_addr, (void *)flash_buffer,
- TEST_BUF_CHARS) != OK)
- {
+ flash_data += 4; /* increment address */
+ }
+ if (write_eeprom (start_addr, (void *)flash_buffer, TEST_BUF_CHARS) != OK) {
printf("Error on write_eeprom()\n");
goto finish;
}
start_addr = (unsigned long)start_addr + TEST_BUF_CHARS;
bytes_written += TEST_BUF_CHARS;
}
printf ("Write Complete, Verifying Data...\n");
bytes_written = 0;
- (ADDR)flash_addr = FLASH_BLK4_BASE_ADDR;
- f_ptr = (unsigned long *)flash_addr;
+ f_ptr = (unsigned long *)FLASH_BLK4_BASE_ADDR;
- while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE))
- {
- if (*f_ptr != (unsigned long)f_ptr)
- {
- printf ("Data verification error at 0x%X\n",
- (unsigned long)f_ptr);
+ while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE)) {
+ if (*f_ptr != (unsigned long)f_ptr) {
+ printf ("Data verification error at 0x%X\n", (unsigned long)f_ptr);
printf ("Expected 0x%X Got 0x%X\n", (unsigned long)f_ptr, *f_ptr);
goto finish;
}
f_ptr++;
bytes_written += 4;
}
printf ("Done Verifying Longword Data!\n\n");
-
printf ("Checking FLASH...\n");
if (check_eeprom(NO_ADDR, 0) == OK)
printf("FLASH is erased\n\n");
else
- {
printf("FLASH is programmed between 0x%X and 0x%X\n\n",
eeprom_prog_first, eeprom_prog_last);
- }
-
printf ("Erasing FLASH...\n");
if (erase_eeprom(NO_ADDR, 0) != OK)
printf("Error on erase_eeprom()\n\n");
else
printf("Done Erasing FLASH!\n\n");
-
printf ("Checking FLASH...\n");
if (check_eeprom(NO_ADDR, 0) == OK)
printf("FLASH is erased\n\n");
else
- {
printf("FLASH is programmed between 0x%X and 0x%X\n\n",
- eeprom_prog_first, eeprom_prog_last);
- }
-
+ eeprom_prog_first, eeprom_prog_last);
/* reinitialize variables */
bytes_written = 0;
- (ADDR)flash_addr = FLASH_BLK4_BASE_ADDR;
-
- start_addr = (ADDR)flash_addr;
- f_ptr = (unsigned long *)flash_addr;
+ start_addr = (ADDR)FLASH_BLK4_BASE_ADDR;
+ f_ptr = (unsigned long *)FLASH_BLK4_BASE_ADDR;
printf ("Writing Inverted Longword Data to FLASH...\n");
/* write to all of available Flash ROM. Don't do this thousands of times
- since the Flash has only 100,000 write cycles in its lifespan */
+ since the Flash has only 100,000 write cycles in its lifespan */
- while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE))
- {
- flash_data = (unsigned long)start_addr;
- for (i=0; i<TEST_BUF_LONGS; i++)
- {
+ while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE)) {
+ flash_data = (unsigned long)start_addr;
+ for (i=0; i<TEST_BUF_LONGS; i++) {
flash_buffer[i] = ~flash_data; /* put address BAR in buffer */
- flash_data += 4; /* increment address */
- }
- if (write_eeprom (start_addr, (void *)flash_buffer,
- TEST_BUF_CHARS) != OK)
- {
+ flash_data += 4; /* increment address */
+ }
+ if (write_eeprom (start_addr, (void *)flash_buffer, TEST_BUF_CHARS) != OK) {
printf("Error on write_eeprom()\n");
goto finish;
}
start_addr = (unsigned long)start_addr + TEST_BUF_CHARS;
bytes_written += TEST_BUF_CHARS;
}
printf ("Write Complete, Verifying Data...\n");
bytes_written = 0;
- while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE))
- {
- if (*f_ptr != (~(unsigned long)f_ptr))
- {
- printf ("Data verification error at 0x%X\n",
- (unsigned long)f_ptr);
+ while (bytes_written < (eeprom_size - RESERVED_AREA_SIZE)) {
+ if (*f_ptr != (~(unsigned long)f_ptr)) {
+ printf ("Data verification error at 0x%X\n", (unsigned long)f_ptr);
printf ("Expected 0x%X Got 0x%X\n", (~(unsigned long)f_ptr), *f_ptr);
goto finish;
}
f_ptr++;
bytes_written += 4;
@@ -1160,69 +534,39 @@ void flash_test(void)
printf ("Checking FLASH...\n");
if (check_eeprom(NO_ADDR, 0) == OK)
printf("FLASH is erased\n\n");
- else
- {
+ else {
printf("FLASH is programmed between 0x%X and 0x%X\n\n",
- eeprom_prog_first, eeprom_prog_last);
+ eeprom_prog_first, eeprom_prog_last);
}
-
printf ("Erasing FLASH...\n");
if (erase_eeprom(NO_ADDR, 0) != OK)
printf("Error on erase_eeprom()\n\n");
else
printf("Done Erasing FLASH!\n\n");
-
printf ("Checking FLASH...\n");
if (check_eeprom(NO_ADDR, 0) == OK)
printf("FLASH is erased\n\n");
else
- {
printf("FLASH is programmed between 0x%X and 0x%X\n\n",
- eeprom_prog_first, eeprom_prog_last);
- }
-
+ eeprom_prog_first, eeprom_prog_last);
/* 11/02/00 */
- printf ("Setting Lock Bits for Blocks 0-3... \n");
- if( (status = set_all_lock_bits() ) == OK )
- {
+ printf ("Setting Lock Bits for Blocks 0-3... \n");
+ if( (status = set_all_lock_bits() ) == OK )
printf("Done!\n");
- }
- else
- {
- printf("Error!\n");
- printf( "error status = 0x%x\n", status );
- // check_lock_bit_status();
- }
-/*
- printf ("Setting Lock Bits for Blocks 0-3... \n");
- if(set_all_lock_bits()==OK)
- {
- printf("Done!\n\n");
- }
- else
- {
- printf("Error!\n\n");
- check_lock_bit_status();
- }
-*/
-/* 11/02/00 */
-
+ else
+ printf("Error! status =0x%x\n", status);
finish:
- _flushICache();
-#if 0
- _enableICache();
-#endif
+ _flushICache();
printf ("\nHit <CR> to Continue...\n");
(void)hexIn();
return;
-
}
#endif // CYGPKG_IO_FLASH
Index: hal/arm/xscale/iq80310/current/src/diag/i557_eep.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/i557_eep.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 i557_eep.c
--- hal/arm/xscale/iq80310/current/src/diag/i557_eep.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/i557_eep.c 13 Nov 2002 15:41:07 -0000
@@ -133,34 +133,33 @@ int eeprom_read (unsigned long pci_base,
int eeprom_addr, /* word offset from start of eeprom */
unsigned short *p_data,/* where to put data in memory */
int nwords /* number of 16bit words to read */
)
{
- int status; /* result code */
- int i; /* loop variable */
+ int status; /* result code */
+ int i; /* loop variable */
/*
* Make sure caller isn't requesting a read beyond the end of the
* eeprom.
*/
if ((eeprom_addr + nwords) > EEPROM_WORD_SIZE)
return (EEPROM_TO_SMALL);
/* Read in desired number of words */
- for (i = 0; i < nwords; i++, eeprom_addr++)
- {
+ for (i = 0; i < nwords; i++, eeprom_addr++) {
/* Select the serial EEPROM */
SELECT_557_EEP(pci_base);
- /* Wait CS setup time */
- eeprom_delay (SELECT_SETUP_TIME);
+ /* Wait CS setup time */
+ eeprom_delay (SELECT_SETUP_TIME);
/* Send start/read command to begin the read */
if (((status = eeprom_send_start (pci_base, EEPROM_READ)) != OK) ||
/* Send address */
- ((status = eeprom_send_addr (pci_base, eeprom_addr)) != OK))
+ ((status = eeprom_send_addr (pci_base, eeprom_addr)) != OK))
return (status);
if ((status = eeprom_get_word (pci_base, p_data++)) != OK)
return (status);
@@ -169,11 +168,10 @@ int eeprom_read (unsigned long pci_base,
/* wait the required de-select time between commands */
eeprom_delay (DESELECT_TIME);
}
-
return (OK);
}
/*-------------------------------------------------------------
* Function: int eeprom_write ()
@@ -187,13 +185,13 @@ int eeprom_write (unsigned long pci_base
int eeprom_addr, /* word offset from start of eeprom */
unsigned short *p_data,/* data source in memory */
int nwords /* number of 16bit words to read */
)
{
- int status; /* result code */
- int i; /* loop variable */
- int check_cntr;
+ int status; /* result code */
+ int i; /* loop variable */
+ int check_cntr;
unsigned short data;
/*
* Make sure caller isn't requesting a read beyond the end of the
* eeprom.
@@ -204,64 +202,60 @@ int eeprom_write (unsigned long pci_base
/* enable eeprom writes */
if ((status = eeprom_write_enable(pci_base)) != OK)
return(status);
/* Read in desired number of words */
- for (i = 0; i < nwords; i++, eeprom_addr++)
- {
+ for (i = 0; i < nwords; i++, eeprom_addr++) {
/* Select the serial EEPROM */
SELECT_557_EEP(pci_base);
- /* Wait CS setup time */
- eeprom_delay (SELECT_SETUP_TIME);
+ /* Wait CS setup time */
+ eeprom_delay (SELECT_SETUP_TIME);
/* Send start/write command to begin the read */
if (((status = eeprom_send_start (pci_base, EEPROM_WRITE)) != OK) ||
/* Send address */
- ((status = eeprom_send_addr (pci_base, eeprom_addr)) != OK))
- return (status);
+ ((status = eeprom_send_addr (pci_base, eeprom_addr)) != OK))
+ return (status);
- data = *p_data++;
- if ((status = eeprom_put_word (pci_base, data)) != OK)
- return (status);
+ data = *p_data++;
+ if ((status = eeprom_put_word (pci_base, data)) != OK)
+ return (status);
/* De-Select the serial EEPROM */
DESELECT_557_EEP(pci_base);
- /* wait the required de-select time between commands */
- eeprom_delay (DESELECT_TIME);
+ /* wait the required de-select time between commands */
+ eeprom_delay (DESELECT_TIME);
- /* Re-Select the serial EEPROM */
+ /* Re-Select the serial EEPROM */
SELECT_557_EEP(pci_base);
- /* now that the write command/data have been clocked into the EEPROM
- we must wait for the BUSY indicator (DO driven low) to indicate
- READY (DO driven high) */
- check_cntr = 0;
-
- while (1)
- {
- check_cntr++;
-
- if (get_sda_line (pci_base) == HIGH) break; /* programming complete */
-
- if (check_cntr > 100000) /* timeout */
- {
- /* De-Select the serial EEPROM */
- DESELECT_557_EEP(pci_base);
- /* wait the required de-select time between commands */
- eeprom_delay (DESELECT_TIME);
-
- return (EEPROM_ERROR);
- }
- }
+ /* now that the write command/data have been clocked into the EEPROM
+ we must wait for the BUSY indicator (DO driven low) to indicate
+ READY (DO driven high) */
+ check_cntr = 0;
- /* De-Select the serial EEPROM */
- DESELECT_557_EEP(pci_base);
+ while (1) {
+ check_cntr++;
+ if (get_sda_line (pci_base) == HIGH) break; /* programming complete */
+
+ if (check_cntr > 100000) { /* timeout */
+ /* De-Select the serial EEPROM */
+ DESELECT_557_EEP(pci_base);
/* wait the required de-select time between commands */
eeprom_delay (DESELECT_TIME);
+ return (EEPROM_ERROR);
+ }
+ }
+
+ /* De-Select the serial EEPROM */
+ DESELECT_557_EEP(pci_base);
+
+ /* wait the required de-select time between commands */
+ eeprom_delay (DESELECT_TIME);
}
/* disable eeprom writes */
if ((status = eeprom_write_disable(pci_base)) != OK)
return(status);
@@ -282,18 +276,18 @@ int eeprom_write_enable (unsigned long p
int status; /* result code */
/* Select the serial EEPROM */
SELECT_557_EEP(pci_base);
- /* Wait CS setup time */
- eeprom_delay (SELECT_SETUP_TIME);
+ /* Wait CS setup time */
+ eeprom_delay (SELECT_SETUP_TIME);
/* Send start/write enable command */
if (((status = eeprom_send_start (pci_base, EEPROM_EWEN)) != OK) ||
- /* Send address */
- ((status = eeprom_send_addr (pci_base, EEPROM_EWEN_OP)) != OK))
- return (status);
+ /* Send address */
+ ((status = eeprom_send_addr (pci_base, EEPROM_EWEN_OP)) != OK))
+ return (status);
/* De-Select the serial EEPROM */
DESELECT_557_EEP(pci_base);
/* wait the required de-select time between commands */
@@ -315,18 +309,18 @@ int eeprom_write_disable (unsigned long
int status; /* result code */
/* Select the serial EEPROM */
SELECT_557_EEP(pci_base);
- /* Wait CS setup time */
- eeprom_delay (SELECT_SETUP_TIME);
+ /* Wait CS setup time */
+ eeprom_delay (SELECT_SETUP_TIME);
/* Send start/write enable command */
if (((status = eeprom_send_start (pci_base, EEPROM_EWDS)) != OK) ||
/* Send address */
((status = eeprom_send_addr (pci_base, EEPROM_EWDS_OP)) != OK))
- return (status);
+ return (status);
/* De-Select the serial EEPROM */
DESELECT_557_EEP(pci_base);
/* wait the required de-select time between commands */
@@ -343,14 +337,14 @@ int eeprom_write_disable (unsigned long
* Note: this routine is a generous approximation as delays for eeproms
* are specified as minimums.
*/
void eeprom_delay (int nsec)
{
- extern void polled_delay (int usec);
+ extern void polled_delay (int usec);
- /* generously delay 1 usec. for each nsec. */
- polled_delay (nsec);
+ /* generously delay 1 usec. for each nsec. */
+ polled_delay (nsec);
}
/******************************************************************************
*
* eeprom_send_start - send a start bit with a read opcode to the '557 serial
@@ -359,35 +353,34 @@ void eeprom_delay (int nsec)
*/
static int eeprom_send_start (unsigned long pci_base, int command)
{
int op_code[2];
- switch (command)
- {
- case EEPROM_WRITE:
- op_code[0] = LOW;
- op_code[1] = HIGH;
- break;
-
- case EEPROM_READ:
- op_code[0] = HIGH;
- op_code[1] = LOW;
- break;
-
- case EEPROM_ERASE:
- op_code[0] = HIGH;
- op_code[1] = HIGH;
- break;
-
- case EEPROM_EWEN:
- case EEPROM_EWDS:
- op_code[0] = LOW;
- op_code[1] = LOW;
- break;
+ switch (command) {
+ case EEPROM_WRITE:
+ op_code[0] = LOW;
+ op_code[1] = HIGH;
+ break;
+
+ case EEPROM_READ:
+ op_code[0] = HIGH;
+ op_code[1] = LOW;
+ break;
+
+ case EEPROM_ERASE:
+ op_code[0] = HIGH;
+ op_code[1] = HIGH;
+ break;
+
+ case EEPROM_EWEN:
+ case EEPROM_EWDS:
+ op_code[0] = LOW;
+ op_code[1] = LOW;
+ break;
- default:
- return(EEPROM_INVALID_CMD);
+ default:
+ return(EEPROM_INVALID_CMD);
}
set_scl_line (pci_base, LOW);
set_sda_line (pci_base, HIGH); /* start bit */
eeprom_delay (DATA_IN_SETUP_TIME);
@@ -424,12 +417,11 @@ static int eeprom_send_addr (unsigned lo
register int i;
/* Do each address bit, MSB => LSB - after each address bit is
sent, read the EEDO bit on the '557 to check for the "dummy 0 bit"
which when set to 0, indicates that the address field is complete */
- for (i = 5; i >= 0; i--)
- {
+ for (i = 5; i >= 0; i--) {
/* If this bit is a 1, set SDA high. If 0, set it low */
if (eeprom_addr & (1 << i))
set_sda_line (pci_base, HIGH);
else
set_sda_line (pci_base, LOW);
@@ -459,21 +451,20 @@ static int eeprom_get_word (unsigned lon
unsigned short *word_addr)
{
register int i;
/* Do each data bit, MSB => LSB */
- for (i = 15; i >= 0; i--)
- {
- set_scl_line (pci_base, HIGH);
+ for (i = 15; i >= 0; i--) {
+ set_scl_line (pci_base, HIGH);
eeprom_delay (SK_HIGH_PERIOD);
- if (get_sda_line (pci_base) == HIGH)
- *word_addr |= (1 << i); /* store bit as a '1' */
- else
- *word_addr &= ~(1 << i); /* store bit as a '0' */
+ if (get_sda_line (pci_base) == HIGH)
+ *word_addr |= (1 << i); /* store bit as a '1' */
+ else
+ *word_addr &= ~(1 << i); /* store bit as a '0' */
- set_scl_line (pci_base, LOW);
+ set_scl_line (pci_base, LOW);
eeprom_delay (SK_LOW_PERIOD);
}
return (OK);
}
@@ -488,21 +479,20 @@ static int eeprom_put_word (unsigned lon
unsigned short data)
{
register int i;
/* Do each data bit, MSB => LSB */
- for (i = 15; i >= 0; i--)
- {
- if (data & (1 << i))
- set_sda_line(pci_base, HIGH);
- else
- set_sda_line(pci_base, LOW);
+ for (i = 15; i >= 0; i--) {
+ if (data & (1 << i))
+ set_sda_line(pci_base, HIGH);
+ else
+ set_sda_line(pci_base, LOW);
- eeprom_delay (DATA_IN_SETUP_TIME);
- set_scl_line (pci_base, HIGH);
+ eeprom_delay (DATA_IN_SETUP_TIME);
+ set_scl_line (pci_base, HIGH);
eeprom_delay (SK_HIGH_PERIOD);
- set_scl_line (pci_base, LOW);
+ set_scl_line (pci_base, LOW);
eeprom_delay (SK_LOW_PERIOD);
}
return (OK);
}
@@ -533,13 +523,13 @@ static void set_scl_line (unsigned long
*-------------------------------------------------------------*/
static void set_sda_line (unsigned long pci_base, /* PCI address */
int state) /* HIGH or LOW */
{
if (state == HIGH)
- EEDI_HIGH_557_EEP (pci_base);
+ EEDI_HIGH_557_EEP (pci_base);
else if (state == LOW)
- EEDI_LOW_557_EEP (pci_base);
+ EEDI_LOW_557_EEP (pci_base);
}
/*-------------------------------------------------------------
* Function: int get_sda_line ()
*
@@ -550,11 +540,11 @@ static void set_sda_line (unsigned long
static int get_sda_line (unsigned long pci_base) /* PCI address */
{
int ret_val; /* result code */
if (EEDO_557_EEP (pci_base))
- ret_val = HIGH;
+ ret_val = HIGH;
else
- ret_val = LOW;
+ ret_val = LOW;
return (ret_val);
}
Index: hal/arm/xscale/iq80310/current/src/diag/interrupts.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/interrupts.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 interrupts.c
--- hal/arm/xscale/iq80310/current/src/diag/interrupts.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/interrupts.c 13 Nov 2002 15:41:08 -0000
@@ -63,14 +63,15 @@
#include "pci_bios.h"
#include "7_segment_displays.h"
extern int(*board_fiq_handler)(void);
extern int(*board_irq_handler)(void);
-extern long _cspr_enable_fiq_int();
-extern long _cspr_enable_irq_int();
-extern long _read_cpsr();
-extern long _scrub_ecc();
+extern long _cspr_enable_fiq_int(void);
+extern long _cspr_enable_irq_int(void);
+extern long _read_cpsr(void);
+extern long _scrub_ecc(unsigned);
+extern void _flushICache(void);
#define AND_WORD(addr,val) *addr = *addr & val
@@ -81,21 +82,21 @@ extern int nmi_verbose; /* for NMI, only
extern int pci_config_cycle; /* don't handle NMI if in a config cycle */
extern int pci_config_error;
typedef struct
{
- FUNCPTR handler;
+ INTFUNCPTR handler;
int arg;
int bus;
int device;
} INT_HANDLER;
extern UINT secondary_busno;
extern UINT primary_busno;
extern STATUS pci_to_xint(int device, int intpin, int *xint);
-extern int isHost();
+extern int isHost(void);
extern int off_ppci_bus (int busno);
#define MAX_SPURIOUS_CNT 5
#define NUM_PCI_XINTS 4 /* SINTA - SINTD */
#define MAX_PCI_HANDLERS 8 /* maximum handlers per PCI Xint */
@@ -136,18 +137,18 @@ int usr_i2c_arg = 0;
void (*usr_mu_isr)(int) = NULL;
int usr_mu_arg = 0;
void (*usr_patu_isr)(int) = NULL;
int usr_patu_arg = 0;
-int ecc_int_handler();
+int ecc_int_handler(void);
/*********************************
* PCI interrupt wrappers
*/
-int sinta_handler()
+int sinta_handler(void)
{
int x, serviced = 0;
/* cycle through connected interrupt handlers to determine which caused int */
for (x = 0; x < MAX_PCI_HANDLERS; x++)
{
@@ -170,11 +171,11 @@ int sinta_handler()
return (serviced);
}
-int sintb_handler()
+int sintb_handler(void)
{
int x, serviced = 0;
/* cycle through connected interrupt handlers to determine which caused int */
for (x = 0; x < MAX_PCI_HANDLERS; x++)
@@ -198,11 +199,11 @@ int sintb_handler()
return (serviced);
}
-int sintc_handler()
+int sintc_handler(void)
{
int x, serviced = 0;
/* cycle through connected interrupt handlers to determine which caused int */
@@ -227,11 +228,11 @@ int sintc_handler()
return (serviced);
}
-int sintd_handler()
+int sintd_handler(void)
{
int x, serviced = 0;
/* cycle through connected interrupt handlers to determine which caused int */
@@ -362,11 +363,11 @@ STATUS pci_isr_disconnect (int intline,
* within the interrupt service routine before exiting.
*
* IRQ Interrupts are multiplexed from SPCI INTA - INTD, External Device Interrupts,
* and XINT6 and XINT7 Internal device interrupts.
*/
-int iq80310_irq_handler()
+int iq80310_irq_handler(void)
{
UINT8* int_status_reg;
UINT8 int_status;
int num_sources = 0;
@@ -651,11 +652,11 @@ void nmi_ecc_isr(void)
/******************************************************************************
* iq80310_fiq_handler - Interrupt dispatcher for IQ80310 FIQ Interrupts
*
*
*/
-int iq80310_fiq_handler()
+int iq80310_fiq_handler(void)
{
unsigned long nmi_status = *(volatile unsigned long *)NISR_ADDR;
unsigned long status;
int srcs_found = 0;
@@ -1096,11 +1097,11 @@ void error_print (
}
extern void __diag_IRQ(void);
extern void __diag_FIQ(void);
-void config_ints()
+void config_ints(void)
{
int xint, x;
unsigned int* pirsr_ptr = (unsigned int*)PIRSR_ADDR;
*pirsr_ptr = 0xf; /* this is an errata in the original Yavapai manual.
Index: hal/arm/xscale/iq80310/current/src/diag/io_utils.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/io_utils.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 io_utils.c
--- hal/arm/xscale/iq80310/current/src/diag/io_utils.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/io_utils.c 13 Nov 2002 15:41:08 -0000
@@ -63,121 +63,125 @@
#define ASCII_TO_DEC 48
void atod(char a, int* b)
{
- *b = (int)(a - ASCII_TO_DEC);
+ *b = (int)(a - ASCII_TO_DEC);
}
char xgetchar(void)
{
- char ch;
hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
- if (__chan)
- ch = CYGACC_COMM_IF_GETC(*__chan);
- else {
+ if (__chan == NULL)
__chan = CYGACC_CALL_IF_DEBUG_PROCS();
- ch = CYGACC_COMM_IF_GETC(*__chan);
- }
- return ch;
+
+ return CYGACC_COMM_IF_GETC(*__chan);
+}
+
+int xgetchar_timeout(char *ch, int msec)
+{
+ bool res;
+ int old_to;
+ hal_virtual_comm_table_t *__chan;
+
+ __chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+ if (__chan == NULL)
+ __chan = CYGACC_CALL_IF_DEBUG_PROCS();
+
+ old_to = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_SET_TIMEOUT, msec);
+ res = CYGACC_COMM_IF_GETC_TIMEOUT(*__chan, ch);
+ CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_SET_TIMEOUT, old_to);
+
+ return res;
}
/*
* naive implementation of "gets"
* (big difference from fgets == strips newline character)
*/
char* sgets(char *s)
{
-
- char *retval = s;
- char ch;
+ char *retval = s;
+ char ch;
- while ((ch = (char)xgetchar()))
- {
- if (ch == 0x0d) /* user typed enter */
- {
- printf("\n");
- break;
- }
- else if (ch == 0x08) /* user typed backspace */
- {
- printf ("\b");
- printf (" ");
- printf ("\b");
- s--;
- }
- else /* user typed another character */
- {
- printf("%c", ch);
- *s++ = ch;
- }
-
+ while ((ch = (char)xgetchar())) {
+ if (ch == 0x0d) { /* user typed enter */
+ printf("\n");
+ break;
}
+ if (ch == 0x08) { /* user typed backspace */
+ printf ("\b");
+ printf (" ");
+ printf ("\b");
+ s--;
+ } else { /* user typed another character */
+ printf("%c", ch);
+ *s++ = ch;
+ }
+ }
- *s = '\0';
- return retval;
+ *s = '\0';
+ return retval;
}
/* Returns true if theChar is a valid hex digit, false if not */
char ishex(char theChar)
{
- switch(theChar)
- {
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- case 'A':
- case 'a':
- case 'B':
- case 'b':
- case 'C':
- case 'c':
- case 'D':
- case 'd':
- case 'E':
- case 'e':
- case 'F':
- case 'f':
- return 1;
- default:
- return 0;
+ switch(theChar) {
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ case 'A':
+ case 'a':
+ case 'B':
+ case 'b':
+ case 'C':
+ case 'c':
+ case 'D':
+ case 'd':
+ case 'E':
+ case 'e':
+ case 'F':
+ case 'f':
+ return 1;
+ default:
+ return 0;
}
}
/* Returns true if theChar is a valid decimal digit, false if not */
char isdec(char theChar)
{
- switch(theChar)
- {
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- return 1;
- default:
- return 0;
- }
+ switch(theChar) {
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ return 1;
+ default:
+ return 0;
+ }
}
/* Convert ascii code of hex digit to number (0-15) */
-char hex2dec(char hex)
+char hex2dec(char hex)
{
if ((hex >= '0') && (hex <= '9'))
return hex - '0';
else if ((hex >= 'a') && (hex <= 'f'))
return hex - 'a' + 10;
@@ -194,65 +198,61 @@ char dec2hex(char dec)
/* Output an 8 bit number as 2 hex digits */
void hex8out(unsigned char num)
{
- printf("%02X",num);
+ printf("%02X",num);
}
/* Output an 32 bit number as 8 hex digits */
void hex32out(unsigned long num)
{
- printf("%08X",num);
+ printf("%08X",num);
}
/* Input a number as (at most 8) hex digits - returns value entered */
long hexIn(void)
{
- char input[40];
- long num;
- register int i;
-
- i = 0;
- num = 0;
-
- if (sgets (input)) /* grab a line */
- {
- num = hex2dec(input[i++]); /* Convert MSD to dec */
- while(ishex(input[i]) && input[i]) /* Get next hex digit */
- {
+ char input[40];
+ long num;
+ register int i;
+
+ i = 0;
+ num = 0;
+
+ if (sgets (input)) { /* grab a line */
+ num = hex2dec(input[i++]); /* Convert MSD to dec */
+ while(ishex(input[i]) && input[i]) { /* Get next hex digit */
num <<= 4; /* Make room for next digit */
num += hex2dec(input[i++]); /* Add it in */
}
- }
- return num;
+ }
+ return num;
}
/* Input a number as decimal digits - returns value entered */
long decIn(void)
{
char input[40];
- int num;
- int tmp;
- register int i;
+ int num;
+ int tmp;
+ register int i;
- i = 0;
- num = 0;
+ i = 0;
+ num = 0;
- if (sgets (input)) /* grab a line */
- {
+ if (sgets (input)) { /* grab a line */
atod(input[i++], &num); /* Convert MSD to decimal */
- while(isdec(input[i]) && input[i]) /* Get next decimal digit */
- {
+ while(isdec(input[i]) && input[i]) { /* Get next decimal digit */
num *= 10; /* Make room for next digit */
- atod(input[i++], &tmp);
+ atod(input[i++], &tmp);
num += tmp; /* Add it in */
}
- }
+ }
- return (num);
+ return (num);
}
Index: hal/arm/xscale/iq80310/current/src/diag/iq80310.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/iq80310.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 iq80310.h
--- hal/arm/xscale/iq80310/current/src/diag/iq80310.h 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/iq80310.h 13 Nov 2002 15:41:08 -0000
@@ -90,20 +90,21 @@
#define REDHAT_REDBOOT_OS FALSE
#else
#define REDHAT_REDBOOT_OS TRUE
#endif
-typedef int STATUS;
+typedef int STATUS;
typedef unsigned char UCHAR;
typedef unsigned char UINT8;
typedef unsigned short USHORT;
typedef unsigned short UINT16;
typedef unsigned long ULONG;
typedef unsigned int UINT;
typedef unsigned int UINT32;
-typedef int (*FUNCPTR) ();
-typedef void (*VOIDFUNCPTR) ();
+typedef int (*INTFUNCPTR) (int);
+typedef int (*FUNCPTR) (void);
+typedef void (*VOIDFUNCPTR) (int);
/* board specific definitions */
#define MEMBASE_DRAM 0xa0000000
@@ -115,19 +116,19 @@ typedef void (*VOIDFUNCPTR) ();
#define ACCESS_DELAY 5
#define DFLTPORT 0 /* channel 2 on 16C552 */
#define XTAL 1843200 /* frequency of baud rate generation crystal */
/* Backplane Detect Register */
-#define BACKPLANE_DET_REG (volatile unsigned char *)0xfe870000
+//#define BACKPLANE_DET_REG (volatile unsigned char *)0xfe870000
#define BP_HOST_BIT 0x1
/* PAL-based external timer definitions */
-#define TIMER_LA0_REG_ADDR (volatile unsigned char *)0xfe880000
-#define TIMER_LA1_REG_ADDR (volatile unsigned char *)0xfe890000
-#define TIMER_LA2_REG_ADDR (volatile unsigned char *)0xfe8a0000
-#define TIMER_LA3_REG_ADDR (volatile unsigned char *)0xfe8b0000
-#define TIMER_ENABLE_REG_ADDR (volatile unsigned char *)0xfe8c0000
+//#define TIMER_LA0_REG_ADDR (volatile unsigned char *)0xfe880000
+//#define TIMER_LA1_REG_ADDR (volatile unsigned char *)0xfe890000
+//#define TIMER_LA2_REG_ADDR (volatile unsigned char *)0xfe8a0000
+//#define TIMER_LA3_REG_ADDR (volatile unsigned char *)0xfe8b0000
+//#define TIMER_ENABLE_REG_ADDR (volatile unsigned char *)0xfe8c0000
#define TIMER_COUNT_MASK 0x5f /* 6 bits of timer data with the MSB in bit 6 not bit 5 */
#define TIMER_CNT_ENAB 0x1
#define TIMER_INT_ENAB 0x2
#define EXT_TIMER_CLK_FREQ 33000000 /* external timer runs at 33 MHz */
Index: hal/arm/xscale/iq80310/current/src/diag/memtest.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/memtest.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 memtest.c
--- hal/arm/xscale/iq80310/current/src/diag/memtest.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/memtest.c 13 Nov 2002 15:41:08 -0000
@@ -71,19 +71,17 @@ extern int quadtest(long startaddr);
extern void hex32out (unsigned int num);
#if 0
extern int printf(char*,...);
#endif
-extern load_runtime_reg();
-extern store_runtime_reg();
/* 02/02/01 jwf */
#ifndef TRUE
-#define TRUE 1
+#define TRUE 1
#endif
#ifndef FALSE
-#define FALSE 0
+#define FALSE 0
#endif
#define FAILED 1
Index: hal/arm/xscale/iq80310/current/src/diag/pci_serv.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/pci_serv.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 pci_serv.c
--- hal/arm/xscale/iq80310/current/src/diag/pci_serv.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/pci_serv.c 13 Nov 2002 15:41:08 -0000
@@ -47,21 +47,21 @@
//####DESCRIPTIONEND####
//
//===========================================================================*/
/********************************************************************************/
-/* PCI_SERV.C - PCI driver for IQ80310 */
-/* */
+/* PCI_SERV.C - PCI driver for IQ80310 */
+/* */
/* History: */
-/* 15sep00 ejb Ported to Cygmon on IQ80310 */
+/* 15sep00 ejb Ported to Cygmon on IQ80310 */
/* 18dec00 snc */
/********************************************************************************/
+#include <redboot.h>
+#include <cyg/hal/hal_iop310.h> // Hardware definitions
#include "iq80310.h"
#include "pci_bios.h"
-
-
#undef DEBUG_PCI
#define IB_MA_ERROR 0x2000
/*==========================================================================*/
@@ -73,57 +73,45 @@ ULONG memspace_limit[NUM_PCI_BUSES];
ULONG iospace_limit[NUM_PCI_BUSES];
UINT nextbus;
UINT secondary_busno = SECONDARY_BUS_NUM;
UINT primary_busno = PRIMARY_BUS_NUM;
UINT lastbus;
-unsigned long dram_size; /* global storing the size of DRAM */
+unsigned long dram_size; /* global storing the size of DRAM */
int bus0_lastbus; /* last secondary bus number behind bus 0 */
int bus1_lastbus; /* last secondary bus number behind bus 1 */
int nmi_verbose; /* global flag to indicate whether or not PCI Error messages should be
- printed. This flag is used to prevent a painful deluge of messages
- when performing PCI configuration reads/writes to possibly non-existant
- devices. */
+ printed. This flag is used to prevent a painful deluge of messages
+ when performing PCI configuration reads/writes to possibly non-existant
+ devices. */
int pci_config_error = FALSE; /* becomes TRUE if an NMI interrupt occurs due to a PCI config cycle */
-#define PRINT_ON() nmi_verbose = TRUE
+#define PRINT_ON() nmi_verbose = TRUE
#define PRINT_OFF() nmi_verbose = FALSE
/*==========================================================================*/
/* Function prototypes */
/*==========================================================================*/
-static void sys_pci_bus_init (UINT bus, UINT root_bus, PCI_DATA* pci_data);
-void print_config_space (int bus, int device, int function);
-
-
-void show_pci(void);
-void show_bus(int);
-void init_312_pci(void);
-
-typedef int (*FUNCPTR) (); /* ptr to function returning int */
typedef struct
{
- FUNCPTR handler;
- int arg;
- int bus;
- int device;
+ FUNCPTR handler;
+ int arg;
+ int bus;
+ int device;
} INT_HANDLER;
#define NUM_PCI_XINTS 4 /* XINT0 - XINT3 */
#define MAX_PCI_HANDLERS 8 /* maximum handlers per PCI Xint */
/* Table where the interrupt handler addresses are stored. */
INT_HANDLER pci_int_handlers[4][MAX_PCI_HANDLERS];
-//extern void printf();
-extern void hexIn();
-
+extern void hexIn(void);
extern int pci_config_cycle;
-
-extern void _enableFiqIrq();
+extern void _enableFiqIrq(void);
extern void config_ints(void); /* configure interrupts */
/*********************************************************************************
* pci_to_xint - convert a PCI device number and Interrupt line to an 80312 XINT
*
@@ -133,2461 +121,126 @@ extern void config_ints(void); /* config
* RETURNS: OK or ERROR if arguments are invalid
*
*/
STATUS pci_to_xint(int device, int intpin, int *xint)
{
- int device_base; /* all devices mod 4 follow same interrupt mapping scheme */
+ int device_base; /* all devices mod 4 follow same interrupt mapping scheme */
/* check validity of arguments */
- if ((intpin < INTA) || (intpin > INTD) || (device > 31))
- return (ERROR);
+ if ((intpin < INTA) || (intpin > INTD) || (device > 31))
+ return (ERROR);
- device_base = device % 4;
+ device_base = device % 4;
- /* interrupt mapping scheme as per PCI-to-PCI Bridge Specification */
- switch (device_base)
- {
- case 0:
- switch (intpin)
- {
- case INTA:
- *xint = XINT0;
- break;
- case INTB:
- *xint = XINT1;
- break;
- case INTC:
- *xint = XINT2;
- break;
- case INTD:
- *xint = XINT3;
- break;
- }
- break;
- case 1:
- switch (intpin)
- {
- case INTA:
- *xint = XINT1;
- break;
- case INTB:
- *xint = XINT2;
- break;
- case INTC:
- *xint = XINT3;
- break;
- case INTD:
- *xint = XINT0;
- break;
- }
+ /* interrupt mapping scheme as per PCI-to-PCI Bridge Specification */
+ switch (device_base) {
+ case 0:
+ switch (intpin) {
+ case INTA:
+ *xint = XINT0;
break;
- case 2:
- switch (intpin)
- {
- case INTA:
- *xint = XINT2;
- break;
- case INTB:
- *xint = XINT3;
- break;
- case INTC:
- *xint = XINT0;
- break;
- case INTD:
- *xint = XINT1;
- break;
- }
- break;
- case 3:
- switch (intpin)
- {
- case INTA:
- *xint = XINT3;
- break;
- case INTB:
- *xint = XINT0;
- break;
- case INTC:
- *xint = XINT1;
- break;
- case INTD:
- *xint = XINT2;
- break;
- }
+ case INTB:
+ *xint = XINT1;
+ break;
+ case INTC:
+ *xint = XINT2;
+ break;
+ case INTD:
+ *xint = XINT3;
break;
- }
- return (OK);
-}
-
-
-/******************************************************************************
-*
-* Checks to see if the "bus" argument identifies a PCI bus which is located
-* off of the Primary PCI bus of the board.
-*/
-int off_ppci_bus (int busno)
-{
- if (busno == primary_busno)
- return (TRUE);
- else if (busno == secondary_busno)
- return (FALSE);
- else if (busno <= bus0_lastbus)
- return (TRUE);
- else
- return (FALSE);
-}
-
-static unsigned old_abort_vec;
-
-/*************************************************************************
-* pci_cycle_cleanup - cleanup after a PCI configuration cycle
-*
-* This function will clear the various PCI abort bits if a configuration
-* cycle to a non-existant device is attempted. Covers both ATU and
-* bridge functions.
-*
-* RETURNS: OK if no PCI abort bits were set or ERROR if abort bits were
-* detected.
-*/
-static int pci_cycle_cleanup (ULONG busno)
-{
- UINT16 *pci_status_reg16;
- UINT16 pci_status16;
- UINT32 *pci_status_reg;
- UINT32 pci_status;
- UINT8 status;
- UINT8 bus_select = 0; /* quiet the compiler warning */
-
- pci_status16 = 0;
- pci_status = 0;
- status = 0;
-
- /* this if-else structure must be done in the correct order to
- ensure that the correct ATU is chosen */
- if (busno == primary_busno)
- bus_select = PRIMARY_BUS_NUM;
- else if (busno == secondary_busno)
- bus_select = SECONDARY_BUS_NUM;
- else if (busno <= bus0_lastbus)
- bus_select = PRIMARY_BUS_NUM;
- else if (busno <= bus1_lastbus)
- bus_select = SECONDARY_BUS_NUM;
- else return (ERROR);
-
-
- /* Read/clear bus status and bus interrupt status registers */
-
- switch (bus_select)
- {
- case 0: /* Primary Bus */
- pci_status_reg16 = (UINT16 *) PATUSR_ADDR;
- pci_status16 = *pci_status_reg16;
-
- if ((pci_status16 & 0xF900) == 0) goto skip1;
-
- #ifdef DEBUG_PCI
- if (pci_status16 & PARITY_ERROR) printf("Parity Error Detected - Primary Bus - ATU\n");
- if (pci_status16 & SERR_ERROR) printf("P_SERR# Asserted - Primary Bus - ATU\n");
- if (pci_status16 & MASTER_ABORT) printf("Master Abort Detected - Primary Bus - ATU\n");
- if (pci_status16 & TARGET_ABORT_M) printf("Target Abort Detected - Primary Bus - ATU is master\n");
- if (pci_status16 & TARGET_ABORT_T) printf("Target Abort Detected - Primary Bus - ATU is target\n");
- if (pci_status16 & MASTER_PAR_ERR) printf("Master Parity Error - Primary Bus - ATU\n");
- #endif
- status = 1;
- pci_status16 &= 0xF980;
- *pci_status_reg16 = pci_status16;
-
-skip1:
- pci_status_reg16 = (UINT16 *) PSR_ADDR;
- pci_status16 = *pci_status_reg16;
-
- if ((pci_status16 & 0xF900) == 0) goto skip2;
-
- #ifdef DEBUG_PCI
- if (pci_status16 & PARITY_ERROR) printf("Parity Error Detected - Primary Bus - Bridge\n");
- if (pci_status16 & SERR_ERROR) printf("P_SERR# Asserted - Primary Bus - Bridge\n");
- if (pci_status16 & MASTER_ABORT) printf("Master Abort Detected - Primary Bus - Bridge\n");
- if (pci_status16 & TARGET_ABORT_M) printf("Target Abort Detected - Primary Bus - Bridge is master\n");
- if (pci_status16 & TARGET_ABORT_T) printf("Target Abort Detected - Primary Bus - Bridge is target\n");
- if (pci_status16 & MASTER_PAR_ERR) printf("Master Parity Error - Primary Bus - Bridge\n");
- #endif
- status = 1;
- pci_status16 &= 0xF980;
- *pci_status_reg16 = pci_status16;
-
-skip2:
-
- pci_status_reg = (UINT32 *) PATUISR_ADDR;
- pci_status = *pci_status_reg;
-
- if ((pci_status & 0x0000079F) == 0) goto skip3;
-
- #ifdef DEBUG_PCI
- if (pci_status & ATU_BIST_ERR) printf("ATU BIST Error - Primary Bus\n");
- if (pci_status & IB_MA_ERROR) printf("Internal Bus Master Abort - Primary Bus - ATU\n");
- #endif
- status = 1;
- pci_status &= 0x0000079f;
- *pci_status_reg = pci_status;
-skip3:
-
- pci_status_reg = (UINT32 *) PBISR_ADDR;
- pci_status = *pci_status_reg;
-
- if ((pci_status & 0x0000003F) == 0) goto skip4;
-
- #ifdef DEBUG_PCI
- if (pci_status16 & BRIDGE_PERR) printf("Parity Error Detected - Primary Bus - Bridge\n");
- if (pci_status16 & SERR_ERROR) printf("P_SERR# Asserted - Primary Bus - Bridge\n");
- if (pci_status16 & MASTER_ABORT) printf("Master Abort Detected - Primary Bus - Bridge\n");
- if (pci_status16 & TARGET_ABORT_M) printf("Target Abort Detected - Primary Bus - Bridge is master\n");
- if (pci_status16 & TARGET_ABORT_T) printf("Target Abort Detected - Primary Bus - Bridge is target\n");
- if (pci_status16 & MASTER_PAR_ERR) printf("Master Parity Error - Primary Bus - Bridge\n");
- #endif
- status = 1;
- pci_status &= 0x0000003F;
- *pci_status_reg = pci_status;
-skip4:
- break;
-
-
- case 1: /* Secondary Bus */
- pci_status_reg16 = (UINT16 *) SATUSR_ADDR;
- pci_status16 = *pci_status_reg16;
-
- if ((pci_status16 & 0xF900) == 0) goto skip5;
- #ifdef DEBUG_PCI
- if (pci_status16 & PARITY_ERROR) printf("Parity Error Detected - Secondary Bus - ATU\n");
- if (pci_status16 & SERR_ERROR) printf("S_SERR# Asserted - Secondary Bus - ATU\n");
- if (pci_status16 & MASTER_ABORT) printf("Master Abort Detected - Secondary Bus - ATU\n");
- if (pci_status16 & TARGET_ABORT_M) printf("Target Abort Detected - Secondary Bus - ATU is master\n");
- if (pci_status16 & TARGET_ABORT_T) printf("Target Abort Detected - Secondary Bus - ATU is target\n");
- if (pci_status16 & MASTER_PAR_ERR) printf("Master Parity Error - Secondary Bus - ATU\n");
- #endif
- status = 1;
- pci_status16 &= 0xF900;
- *pci_status_reg16 = pci_status16;
-skip5:
- pci_status_reg16 = (UINT16 *) SSR_ADDR;
- pci_status16 = *pci_status_reg16;
-
- if ((pci_status16 & 0xF900) == 0) goto skip6;
-
- #ifdef DEBUG_PCI
- if (pci_status16 & PARITY_ERROR) printf("Parity Error Detected - Secondary Bus - Bridge\n");
- if (pci_status16 & SERR_ERROR) printf("S_SERR# Asserted - Secondary Bus - Bridge\n");
- if (pci_status16 & MASTER_ABORT) printf("Master Abort Detected - Secondary Bus - Bridge\n");
- if (pci_status16 & TARGET_ABORT_M) printf("Target Abort Detected - Secondary Bus - Bridge is master\n");
- if (pci_status16 & TARGET_ABORT_T) printf("Target Abort Detected - Secondary Bus - Bridge is target\n");
- if (pci_status16 & MASTER_PAR_ERR) printf("Master Parity Error - Secondary Bus - Bridge\n");
- #endif
- status = 1;
- pci_status16 &= 0xF980;
- *pci_status_reg16 = pci_status16;
-
-skip6:
- pci_status_reg = (UINT32 *) SATUISR_ADDR;
- pci_status = *pci_status_reg;
-
- if ((pci_status & 0x0000069F) == 0) goto skip7;
-
- #ifdef DEBUG_PCI
- if (pci_status & IB_MA_ERROR) printf("Internal Bus Master Abort - Secondary Bus - ATU\n");
- #endif
- status = 1;
- pci_status &= 0x0000069F;
- *pci_status_reg = pci_status;
-skip7:
- break;
-
- default: return (ERROR);
- }
-
- if (pci_config_error) /* check to see if the NMI handler during the config cycle */
- status = 1;
-
- pci_config_cycle = 0; /* turn on exception handling after pci config cycle */
-
- if (old_abort_vec)
- {
- ((volatile unsigned *)0x20)[4] = old_abort_vec;
- old_abort_vec = 0;
- _flushICache();
- }
-
- if (status) return (ERROR);
- else return (OK);
-}
-
-extern void __ignore_abort(void);
-
-/**************************************************************************
-* sys_config_setup - this function sets up a PCI configuration cycle
-*
-* This function sets up either the primary or secondary outbound configuration
-* cycle address register. It is called by all the sys_*_config_* functions.
-*
-*/
-static int sys_config_setup(ULONG busno, ULONG devno, ULONG funcno, ULONG regno, UINT32 **pci_occ_addr,
- UINT32 **pci_occ_data)
-{
-
- /* First check the parameters for sanity */
- if ((busno > 255) || (devno > 31) || (funcno> 7) || (regno > 63)) return (ERROR);
-
- if (busno == primary_busno)
- {
- *pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- *pci_occ_data = (UINT32 *) POCCDR_ADDR;
- }
- else if (busno == secondary_busno)
- {
- *pci_occ_addr = (UINT32 *) SOCCAR_ADDR;
- *pci_occ_data = (UINT32 *) SOCCDR_ADDR;
}
- else if (busno <= bus0_lastbus)
- {
- *pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- *pci_occ_data = (UINT32 *) POCCDR_ADDR;
+ break;
+ case 1:
+ switch (intpin) {
+ case INTA:
+ *xint = XINT1;
+ break;
+ case INTB:
+ *xint = XINT2;
+ break;
+ case INTC:
+ *xint = XINT3;
+ break;
+ case INTD:
+ *xint = XINT0;
+ break;
}
- else if (busno <= bus1_lastbus)
- {
- *pci_occ_addr = (UINT32 *) SOCCAR_ADDR;
- *pci_occ_data = (UINT32 *) SOCCDR_ADDR;
+ break;
+ case 2:
+ switch (intpin) {
+ case INTA:
+ *xint = XINT2;
+ break;
+ case INTB:
+ *xint = XINT3;
+ break;
+ case INTC:
+ *xint = XINT0;
+ break;
+ case INTD:
+ *xint = XINT1;
+ break;
}
- else return (ERROR);
-
- (void)pci_cycle_cleanup(busno); /* start with clean slate */
-
- pci_config_cycle = 1; /* turn off exception handling during pci config cycle */
-
- if (old_abort_vec) {
- printf("recursive config setup\n");
- while (1);
+ break;
+ case 3:
+ switch (intpin) {
+ case INTA:
+ *xint = XINT3;
+ break;
+ case INTB:
+ *xint = XINT0;
+ break;
+ case INTC:
+ *xint = XINT1;
+ break;
+ case INTD:
+ *xint = XINT2;
+ break;
}
-
- old_abort_vec = ((volatile unsigned *)0x20)[4];
- ((volatile unsigned *)0x20)[4] = (unsigned)__ignore_abort;
- _flushICache();
-
- pci_config_error = FALSE;
-
- /* turn off error messages which could be generated by non-existant devices */
- PRINT_OFF();
-
- if ((busno == PRIMARY_BUS_NUM) || (busno == SECONDARY_BUS_NUM))
- {
- /* set up the config access register for type 0 config cycles */
- **pci_occ_addr =
- (
- (1 << ((devno & 0x1f) + 16)) |
- ((funcno & 0x07) << 8) |
- ((regno & 0x3f) << 2) |
- (0) );
+ break;
}
- else
- {
- /* set up the config access register for type 1 config cycles */
- **pci_occ_addr =
- (
- ((busno & 0xff) << 16) |
- ((devno & 0x1f) << 11) |
- ((funcno& 0x07) << 8) |
- ((regno & 0x3f) << 2) |
- (1) );
- }
-
- return (OK);
-}
-
-/**************************************************************************
-* sys_read_config_byte - this function performs a PCI configuration cycle
-* and returns a byte.
-*
-* This function will read a byte from config space on the PCI bus. It is
-* a user service intended to be called through the calls interface.
-*/
-ULONG sys_read_config_byte (UINT32 busno, UINT32 devno, UINT32 funcno, UINT32 offset, UINT8 *data)
-{
- UINT32 *pci_occ_data;
- UINT32 regno;
- UINT32 *pci_occ_addr;
-
- /* initialize here to keep compiler happy */
- pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- pci_occ_data = (UINT32 *) POCCDR_ADDR;
-
- /* Register numbers are DWORD indexes */
- regno = offset / 0x4;
-
- /* Set up the cycle. */
- if (sys_config_setup (busno, devno, funcno, regno, &pci_occ_addr, &pci_occ_data) != OK)
- return (ERROR);
-
- /* Now do the read */
- *data = (UINT8)(((*pci_occ_data) >> ((offset % 0x4) * 8)) & 0xff);
-
- if (pci_cycle_cleanup (busno) == OK)
- {
- PRINT_ON();
- return (OK);
- }
- else
- {
- PRINT_ON();
- return (ERROR);
- }
-}
-
-/**************************************************************************
-* sys_read_config_word - this function performs a PCI configuration cycle
-* and returns a 16-bit word.
-*
-* This function will read a word from config space on the PCI bus. It is
-* a user service intended to be called through the calls interface.
-*/
-ULONG sys_read_config_word (UINT32 busno, UINT32 devno, UINT32 funcno, UINT32 offset, UINT16 *data)
-{
- UINT32 *pci_occ_data;
- UINT32 regno;
- UINT32 *pci_occ_addr;
-
- /* initialize here to keep compiler happy */
- pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- pci_occ_data = (UINT32 *) POCCDR_ADDR;
-
- /* Offsets must be word-aligned */
- if (offset % 0x2) return (ERROR);
-
- /* Register numbers are DWORD indexes */
- regno = offset / 0x4;
-
- /* Set up the cycle. */
- if (sys_config_setup (busno, devno, funcno, regno, &pci_occ_addr, &pci_occ_data) != OK) return (ERROR);
-
- /* Now do the read */
- *data = (UINT16)(((*pci_occ_data) >> ((offset % 0x4) * 8)) & 0xffff);
-
- if (pci_cycle_cleanup(busno) == OK)
- {
- PRINT_ON();
- return (OK);
- }
- else
- {
- PRINT_ON();
- return (ERROR);
- }
-}
-
-/**************************************************************************
-* sys_read_config_dword - this function performs a PCI configuration cycle
-* and returns a 32-bit word.
-*
-* This function will read a dword from config space on the PCI bus. It is
-* a user service intended to be called through the calls interface.
-*/
-ULONG sys_read_config_dword (
- UINT32 busno,
- UINT32 devno,
- UINT32 funcno,
- UINT32 offset,
- UINT32 *data
- )
-{
- UINT32 *pci_occ_data;
- UINT32 regno;
- UINT32 *pci_occ_addr;
-
- /* initialize here to keep compiler happy */
- pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- pci_occ_data = (UINT32 *) POCCDR_ADDR;
-
- /* Offsets must be dword-aligned */
- if (offset % 0x4) return (ERROR);
-
- /* Register numbers are DWORD indexes */
- regno = offset / 0x4;
-
- /* Set up the cycle. */
- if (sys_config_setup (busno, devno, funcno, regno, &pci_occ_addr, &pci_occ_data) != OK)
- return (ERROR);
-
- /* Now do the read */
- *data = *pci_occ_data;
-
- if (pci_cycle_cleanup (busno) == OK)
- {
- PRINT_ON();
- return (OK);
- }
- else
- {
- PRINT_ON();
- return (ERROR);
- }
-}
-
-/**************************************************************************
-* sys_write_config_byte - this function performs a PCI configuration cycle
-* and writes a byte.
-*
-* This function will write a byte to config space on the PCI bus. It is
-* a user service intended to be called through the calls interface.
-*/
-ULONG sys_write_config_byte (
- UINT32 busno,
- UINT32 devno,
- UINT32 funcno,
- UINT32 offset,
- UINT8 *data
- )
-{
- UINT32 *pci_occ_data;
- UINT32 regno, temp;
- UINT32 *pci_occ_addr;
- UINT32 data_mask;
-
- /* initialize here to keep compiler happy */
- pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- pci_occ_data = (UINT32 *) POCCDR_ADDR;
-
- /* Register numbers are DWORD indexes */
- regno = offset / 0x4;
-
- /* build mask for byte of interest */
- data_mask = ~(0x000000ff << ((offset % 0x4) * 8));
-
- /* Set up the cycle. */
- if (sys_config_setup (busno, devno, funcno, regno, &pci_occ_addr, &pci_occ_data) != OK)
- return (ERROR);
-
- /* set up 32-bit word, clear old data, OR in new data */
- temp = (UINT32)(((UINT32) *data) << ((offset % 0x4) * 8));
- *pci_occ_data &= data_mask;
- *pci_occ_data |= temp;
-
- if (pci_cycle_cleanup (busno) == OK)
- {
- PRINT_ON();
- return (OK);
- }
- else
- {
- PRINT_ON();
- return (ERROR);
- }
-}
-
-/**************************************************************************
-* sys_write_config_word - this function performs a PCI configuration cycle
-* and writes a 16-bit word.
-*
-* This function will write a word to config space on the PCI bus. It is
-* a user service intended to be called through the calls interface.
-*/
-ULONG sys_write_config_word (
- UINT32 busno,
- UINT32 devno,
- UINT32 funcno,
- UINT32 offset,
- UINT16 *data
- )
-{
- UINT32 *pci_occ_data;
- UINT32 regno, temp;
- UINT32 *pci_occ_addr;
- UINT32 data_mask;
-
- /* initialize here to keep compiler happy */
- pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- pci_occ_data = (UINT32 *) POCCDR_ADDR;
-
- /* Offsets must be word-aligned */
- if (offset % 0x2) return (ERROR);
-
- /* Register numbers are DWORD indexes */
- regno = offset / 0x4;
-
- /* build mask for word of interest */
- data_mask= ~(0x0000ffff << ((offset % 0x4) * 8));
-
- /* Set up the cycle. */
- if (sys_config_setup (busno, devno, funcno, regno, &pci_occ_addr, &pci_occ_data) != OK)
- return (ERROR);
-
- /* set up 32-bit word */
- temp = (UINT32)(((UINT32) *data) << ((offset % 0x4) * 8));
- *pci_occ_data &= data_mask;
- *pci_occ_data |= temp;
-
- if (pci_cycle_cleanup (busno) == OK)
- {
- PRINT_ON();
- return (OK);
- }
- else
- {
- PRINT_ON();
- return (ERROR);
- }
-}
-
-/**************************************************************************
-* sys_write_config_dword - this function performs a PCI configuration cycle
-* and writes a 32-bit word.
-*
-* This function will write a dword to config space on the PCI bus. It is
-* a user service intended to be called through the calls interface.
-*/
-ULONG sys_write_config_dword (
- UINT32 busno,
- UINT32 devno,
- UINT32 funcno,
- UINT32 offset,
- UINT32 *data
- )
-{
- UINT32 *pci_occ_data;
- UINT32 regno;
- UINT32 *pci_occ_addr;
-
- /* initialize here to keep compiler happy */
- pci_occ_addr = (UINT32 *) POCCAR_ADDR;
- pci_occ_data = (UINT32 *) POCCDR_ADDR;
-
- /* Offsets must be dword-aligned */
- if (offset % 0x4) return (ERROR);
-
- /* Register numbers are DWORD indexes */
- regno = offset / 0x4;
-
- /* Set up the cycle. */
- if (sys_config_setup (busno, devno, funcno, regno, &pci_occ_addr, &pci_occ_data) != OK)
- return (ERROR);
-
- /* Now do the write */
- *pci_occ_data = *data;
-
- if (pci_cycle_cleanup (busno) == OK)
- {
- PRINT_ON();
- return (OK);
- }
- else
- {
- PRINT_ON();
- return (ERROR);
- }
-}
-
-/******************************************************************************
-* sys_find_pci_device - find a PCI device based on Vendor ID and Device ID
-*
-* This function returns the location of PCI devices that have a specific
-* Device ID and Vendor ID. Given a Vendor ID, Device ID, and an Index, the
-* function returns the Bus Number, Device Number, and Function Number of the
-* Nth Device/Function whose Vendor ID and Device ID match the input parameters.
-*
-* Calling software can find all devices having the same Vendor ID and Device ID
-* by making successive calls to this function starting with the index set to 0,
-* and incrementing the index until the function returns DEVICE_NOT_FOUND. A
-* return value of BAD_VENDOR_ID indicates that the Vendor ID value passed had
-* a value of all 1's.
-*
-*/
-STATUS sys_find_pci_device (int vendor_id, int device_id, int index, PCI_DEVICE_LOCATION *devloc)
-{
- int found;
- int multifunction = FALSE;
- USHORT vendid, devid;
- ULONG bus, device, function;
- UCHAR header_type;
-
- if (vendor_id == 0xffff) return (BAD_VENDOR_ID);
-
- found = 0;
-
- for (bus = 0; bus <= lastbus; bus++)
- {
- for (device = 0; device < MAX_DEVICE_NUMBER; device++)
- {
- for (function = 0; function < MAX_FUNCTION_NUMBER; function++)
- {
-
- /* before we go beyond function 0, make sure that the
- device is truly a multi-function device, otherwise we may
- get aliasing */
- if (function == 0)
- {
- sys_read_config_byte (bus,device,function,HEADER_TYPE_OFFSET,&header_type);
- if (!(header_type & MULTIFUNCTION_DEVICE))
- multifunction = FALSE;
- else multifunction = TRUE;
- }
-
-
- /* If no device there, go on to next device */
- if ((sys_read_config_word (bus,device,function,VENDOR_ID_OFFSET,&vendid)== ERROR) ||
- (sys_read_config_word (bus,device,function,DEVICE_ID_OFFSET,&devid)== ERROR))
- {
- break; /* go on to next device */
- }
-
- /* If not a match */
- if ((devid != device_id) || (vendid != vendor_id))
- {
- if (multifunction == FALSE) break; /* go on to next device */
- else continue; /* go on to next function */
- }
-
- /* If we've gotten this far we've found a match */
-
- /* check to see if we need to look for another occurrance */
- if (index-- != 0)
- {
- if (multifunction == FALSE) break; /* go on to next device */
- else continue; /* go on to next function */
- }
-
- /* found the correct occurrance (index) */
- else
- {
- devloc->bus_number = bus;
- devloc->device_number = device;
- devloc->function_number = function;
- return (OK);
- }
- } /* function */
- } /* device */
- } /* bus */
-
- /* If we haven't returned by this point, no match was found */
- return (DEVICE_NOT_FOUND);
+ return (OK);
}
-/******************************************************************************
-* sys_find_pci_class_code - find a PCI device based on a specific Class Code
-*
-* This function returns the location of PCI devices that have a specific
-* Class Code. Given a Class Code and an Index, the function returns the Bus
-* Number, Device Number, and Function Number of the Nth Device/Function whose
-* Class Code matches the input parameters.
-*
-* Calling software can find all devices having the same Class Code
-* by making successive calls to this function starting with the index set to 0,
-* and incrementing the index until the function returns DEVICE_NOT_FOUND.
-*
-*/
-STATUS sys_find_pci_class_code (
- int class_code,
- int index,
- PCI_DEVICE_LOCATION *devloc
- )
-{
- USHORT vendid;
- ULONG bus, device, function;
- UCHAR dev_class, header_type;
- int multifunction = FALSE;
-
- for (bus = 0; bus <= lastbus; bus++)
- {
- for (device = 0; device <= MAX_DEVICE_NUMBER; device++)
- {
-
- for (function = 0; function < MAX_FUNCTION_NUMBER; function++)
- {
-
- /* before we go beyond function 0, make sure that the
- device is truly a multi-function device, otherwise we may
- get aliasing */
- if (function == 0)
- {
- sys_read_config_byte (bus,device,function,HEADER_TYPE_OFFSET,&header_type);
- if (!(header_type & MULTIFUNCTION_DEVICE)) multifunction = FALSE;
- else multifunction = TRUE;
- }
-
- /* If no device there, go on to next device */
- if ((sys_read_config_word (bus,device,function,VENDOR_ID_OFFSET,&vendid)== ERROR) ||
- (sys_read_config_byte (bus,device,function,BASE_CLASS_OFFSET,&dev_class)== ERROR))
- {
- break; /* go on to next device */
- }
-
- /* If not a match */
- if (dev_class != class_code)
- {
- if (multifunction == FALSE) break; /* go on to next device */
- else continue; /* go on to next function */
- }
-
- /* If we've gotten this far we've found a match */
-
- /* check to see if we need to look for another occurrance */
- if (index-- != 0)
- {
- if (multifunction == FALSE) break; /* go on to next device */
- else continue; /* go on to next function */
- }
-
- /* found the correct occurrance (index) */
- else
- {
- devloc->bus_number = bus;
- devloc->device_number = device;
- devloc->function_number = function;
- return (OK);
- }
- }
- }
- }
- /* If we haven't returned by this point, no match was found */
- return (DEVICE_NOT_FOUND);
-}
/******************************************************************************
-* sys_pci_bios_present - determine if a PCI BIOS is present
-*
-* This function allows the caller to determine whether the PCI BIOS interface
-* function set is present, and what the current interface version level is.
-* It also provides information about what hardware mechanism is used for
-* accessing configuration space and whether or not the hardware supports
-* generation of PCI Special Cycles.
-*
-*/
-STATUS sys_pci_bios_present (PCI_BIOS_INFO *info)
-{
- /* 0x00 indicates PCI BIOS functions present */
- info->present_status = 0x00;
-
- /* Config types 0 or 1, no special cycle mechanisms */
- info->hardware_mech_config = CONFIG_MECHANISM_1 | CONFIG_MECHANISM_2;
- info->hardware_mech_special = 0x00;
-
- info->if_level_major_ver = 0x02;
- info->if_level_minor_ver = 0x01;
-
- info->last_pci_bus = lastbus;
-
- return (OK);
-}
-
-
-/******************************************************************************
-* sys_generate_special_cycle - generate a PCI Special Cycle
-*
-* This function allows for generation of PCI Special Cycles. The generated
-* special cycle will be broadcast on a specific PCI Bus in the system.
-*
-* PCI Special Cycles are not supported by Cyclone Hardware.
-*
-*/
-STATUS sys_generate_special_cycle (int bus_number, int special_cycle_data)
-{
- return (FUNC_NOT_SUPPORTED);
-}
-
-/******************************************************************************
-* sys_get_irq_routing_options - get the PCI interrupt routing options
-*
-* The PCI Interrupt routing fabric on the Cyclone Hardware is not
-* reconfigurable (fixed mapping relationships).
*
+* Checks to see if the "bus" argument identifies a PCI bus which is located
+* off of the Primary PCI bus of the board.
*/
-STATUS sys_get_irq_routing_options (PCI_IRQ_ROUTING_TABLE *table)
+int off_ppci_bus (int busno)
{
- return (FUNC_NOT_SUPPORTED);
+ if (busno == primary_busno)
+ return (TRUE);
+ else if (busno == secondary_busno)
+ return (FALSE);
+ else if (busno <= bus0_lastbus)
+ return (TRUE);
+ else
+ return (FALSE);
}
/******************************************************************************
* sys_set_pci_irq - connect a PCI interrupt to a processor IRQ.
*
* The PCI Interrupt routing fabric on the Cyclone Hardware is not
* reconfigurable (fixed mapping relationships) and therefore, this function
* is not supported.
*
*/
-STATUS sys_set_pci_irq (
- int int_pin,
- int irq_num,
- int bus_dev
- )
+STATUS sys_set_pci_irq (int int_pin, int irq_num, int bus_dev)
{
return (FUNC_NOT_SUPPORTED);
}
-/******************************************************************************
-*
-* print_config_space - print contents of config space
-*
-* This function prints out the contents of the PCI configuration space for
-* the selected PCI device. The local RN functions are accessible using bus= -1
-* and function=0 for the Bridge and bus = -1 function=1 for the ATU.
-*
-*/
-void print_config_space (int busno, int devno, int function)
-{
- ULONG offset;
- UINT32 long_data;
- UINT16 short_data;
- UINT8 byte_data;
- register PCI_CONFIG_SPACE *cptr = 0;
- USHORT vendor_id = 0xffff;
- USHORT device_id = 0xffff;
- USHORT subvendor_id = 0xffff;
- USHORT subdevice_id = 0xffff;
- int header_type;
-
- if ((busno > (int)lastbus) || (busno < -1))
- {
- printf("Invalid bus number = %d\n", busno);
- return;
- }
-
- if (devno < -1)
- {
- printf("Invalid device number = %d\n", devno);
- return;
- }
-
- if ((busno == -1) && (devno == -1) && (function == 0)) /* local Bridge device */
- {
- cptr = (PCI_CONFIG_SPACE *) VIDR_ADDR;
- printf("\n\n\nReading Configuration Space for 80960RN PCI-PCI Bridge\n");
- }
- else if ((busno == -1) && (devno == -1) && (function == 1)) /* local ATU device */
- {
- cptr = (PCI_CONFIG_SPACE *) ATUVID_ADDR;
- printf("\n\n\nReading Configuration Space for 80960RN ATU\n");
- }
-
- if ((busno == -1) && (devno == -1) && (function == 0))
- {
- /* this is the bridge function */
- printf("-----------------------------------------------------------------\n\n");
- printf("Vendor ID = 0x%04X ",cptr->pci1_config.vendor_id);
- printf("Device ID = 0x%04X\n",cptr->pci1_config.device_id);
- printf("Command Register = 0x%04X ",cptr->pci1_config.command);
- printf("Status Register = 0x%04X\n",cptr->pci1_config.status);
- printf("Revision ID = 0x%02X ",cptr->pci1_config.revision_id);
- printf("Programming Interface = 0x%02X\n",cptr->pci1_config.prog_if);
- printf("Sub Class = 0x%02X ",cptr->pci1_config.sub_class);
- printf("Base Class = 0x%02X\n",cptr->pci1_config.base_class);
- printf("Cache Line Size = 0x%02X ",cptr->pci1_config.cache_line_size);
- printf("Latency Timer = 0x%02X\n",cptr->pci1_config.latency_timer);
- printf("Header Type = 0x%02X ",cptr->pci1_config.header_type);
- printf("BIST = 0x%02X\n",cptr->pci1_config.bist);
- printf("Primary Bus Number = 0x%02X ",cptr->pci1_config.primary_busno);
- printf("Secondary Bus Number = 0x%02X\n",cptr->pci1_config.secondary_busno);
- printf("Sub Bus Number = 0x%02X ",cptr->pci1_config.subordinate_busno);
- printf("Secondary Latency = 0x%02X\n",cptr->pci1_config.secondary_latency_timer);
- printf("Secondary I/O Base = 0x%02X ",cptr->pci1_config.io_base);
- printf("Secondary I/O Limit = 0x%02X\n",cptr->pci1_config.io_limit);
- printf("Secondary Status = 0x%04X ",cptr->pci1_config.secondary_status);
- printf("Secondary Memory Base = 0x%04X\n",cptr->pci1_config.mem_base);
- printf("Secondary Mem Limit = 0x%04X ",cptr->pci1_config.mem_limit);
- printf("Prefetch Memory Base = 0x%04X\n",cptr->pci1_config.pfmem_base);
- printf("Prefetch Memory Limit = 0x%04X ",cptr->pci1_config.pfmem_limit);
- printf("I/O Base (Upper) = 0x%04X\n",cptr->pci1_config.iobase_upper16);
- printf("I/O Limit (Upper) = 0x%04X ",cptr->pci1_config.iolimit_upper16);
- printf("Subsystem Vendor ID = 0x%04X\n",cptr->pci1_config.sub_vendor_id);
- printf("Subsystem ID = 0x%04X ",cptr->pci1_config.sub_device_id);
- printf("Interrupt Line = 0x%02X\n",cptr->pci1_config.int_line);
- printf("Interrupt Pin = 0x%02X ",cptr->pci1_config.int_pin);
- printf("Bridge Control = 0x%04X\n",cptr->pci1_config.bridge_control);
- printf("PCI Range 0 Base = 0x%08X\n",cptr->pci1_config.pcibase_addr0);
- printf("PCI Range 1 Base = 0x%08X\n",cptr->pci1_config.pcibase_addr1);
- printf("Prefetch Base (Upper) = 0x%08X\n",cptr->pci1_config.pfbase_upper32);
- printf("Prefetch Limit(Upper) = 0x%08X\n",cptr->pci1_config.pflimit_upper32);
- printf("Expansion ROM Base = 0x%08X\n",cptr->pci1_config.pcibase_exp_rom);
- }
- else if ((busno == -1) && (devno == -1) && (function == 1))
- {
- /* this is the ATU function */
- printf("------------------------------------------------------------------\n\n");
- printf("Vendor ID = 0x%04X ",cptr->pci0_config.vendor_id);
- printf("Device ID = 0x%04X\n",cptr->pci0_config.device_id);
- printf("Command Register = 0x%04X ",cptr->pci0_config.command);
- printf("Status Register = 0x%04X\n",cptr->pci0_config.status);
- printf("Revision ID = 0x%02X ",cptr->pci0_config.revision_id);
- printf("Programming Interface = 0x%02X\n",cptr->pci0_config.prog_if);
- printf("Sub Class = 0x%02X ",cptr->pci0_config.sub_class);
- printf("Base Class = 0x%02X\n",cptr->pci0_config.base_class);
- printf("Cache Line Size = 0x%02X ",cptr->pci0_config.cache_line_size);
- printf("Latency Timer = 0x%02X\n",cptr->pci0_config.latency_timer);
- printf("Header Type = 0x%02X ",cptr->pci0_config.header_type);
- printf("BIST = 0x%02X\n",cptr->pci0_config.bist);
- printf("Interrupt Line = 0x%02X ",cptr->pci0_config.int_line);
- printf("Interrupt Pin = 0x%02X\n",cptr->pci0_config.int_pin);
- printf("Minimum Grant = 0x%02X ",cptr->pci0_config.min_gnt);
- printf("Maximum Latency = 0x%02X\n",cptr->pci0_config.max_lat);
- printf("Subsystem Vendor ID = 0x%04X ",cptr->pci0_config.sub_vendor_id);
- printf("Subsystem ID = 0x%04X\n",cptr->pci0_config.sub_device_id);
- printf("Base Address 0 = 0x%08X\n",cptr->pci0_config.pcibase_addr0);
- printf("Base Address 1 = 0x%08X\n",cptr->pci0_config.pcibase_addr1);
- printf("Base Address 2 = 0x%08X\n",cptr->pci0_config.pcibase_addr2);
- printf("Base Address 3 = 0x%08X\n",cptr->pci0_config.pcibase_addr3);
- printf("Base Address 4 = 0x%08X\n",cptr->pci0_config.pcibase_addr4);
- printf("Base Address 5 = 0x%08X\n",cptr->pci0_config.pcibase_addr5);
- printf("Cardbus CIS Pointer = 0x%08X\n",cptr->pci0_config.cardbus_cis_ptr);
- printf("Expansion ROM Base = 0x%08X\n",cptr->pci0_config.pcibase_exp_rom);
-
- }
-
- else /* device on PCI bus */
- {
- printf("\n\n\nReading Configuration Space for PCI Bus 0x%02X, Device 0x%02X, Function 0x%02X\n",
- busno, devno, function);
- printf("------------------------------------------------------------------------\n\n");
-
- /* get Vendor Id */
- offset = VENDOR_ID_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Vendor Id\n");
- return;
- }
- if (short_data == 0xffff) /* non-existant device */
- {
- printf("No such device.\n");
- return;
- }
- printf("Vendor ID = 0x%04X ",short_data);
- vendor_id = short_data;
-
- /* get Device Id */
- offset = DEVICE_ID_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Device Id\n");
- return;
- }
- printf("Device ID = 0x%04X\n",short_data);
- device_id = short_data;
-
- /* get Command Register */
- offset = COMMAND_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Command Register\n");
- return;
- }
- printf("Command Register = 0x%04X ",short_data);
-
- /* get Status Register */
- offset = STATUS_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Status Register\n");
- return;
- }
- printf("Status Register = 0x%04X\n",short_data);
-
- /* get Revision Id */
- offset = REVISION_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Revision Id\n");
- return;
- }
- printf("Revision ID = 0x%02X ",byte_data);
-
- /* get Programming Interface */
- offset = PROG_IF_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Programming Interface\n");
- return;
- }
- printf("Programming Interface = 0x%02X\n",byte_data);
-
- /* get Sub Class */
- offset = SUB_CLASS_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Sub Class\n");
- return;
- }
- printf("Sub Class = 0x%02X ",byte_data);
-
- /* get Base Class */
- offset = BASE_CLASS_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Base Class\n");
- return;
- }
- printf("Base Class = 0x%02X\n",byte_data);
-
- /* get Cache Line Size */
- offset = CACHE_LINE_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Cache Line Size\n");
- return;
- }
- printf("Cache Line Size = 0x%02X ",byte_data);
-
- /* get Latency Timer */
- offset = LATENCY_TIMER_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Latency Timer\n");
- return;
- }
- printf("Latency Timer = 0x%02X\n",byte_data);
-
- /* get Header Type */
- offset = HEADER_TYPE_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Header Type\n");
- return;
- }
- printf("Header Type = 0x%02X ",byte_data);
- header_type = (((int)byte_data) & 0x7f); /* strip multifunction bit */
-
- /* get BIST */
- offset = BIST_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading BIST\n");
- return;
- }
- printf("BIST = 0x%02X\n",byte_data);
-
- /* get Interrupt Line info */
- offset = INT_LINE_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Interrupt Line\n");
- return;
- }
- printf("Interrupt Line = 0x%02X ",byte_data);
-
- /* get Interrupt Pin info */
- offset = INT_PIN_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Interrupt Pin\n");
- return;
- }
- printf("Interrupt Pin = 0x%02X\n",byte_data);
-
- /* get Capabilities Pointer info */
- offset = CAP_PTR_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Capabilities Pointer register\n");
- return;
- }
- printf("Capabilities Pointer = 0x%02X\n",byte_data);
-
- if (header_type == 0) /* type 0 header-specific info */
- {
- /* get Min Gnt info */
- offset = MIN_GNT_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Minimum Grant\n");
- return;
- }
- printf("Minimum Grant = 0x%02X ",byte_data);
-
- /* get Max Lat info */
- offset = MAX_LAT_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Maximum Latency\n");
- return;
- }
- printf("Maximum Latency = 0x%02X\n",byte_data);
-
- /* get subsystem vendor ID */
- offset = SUB_VENDOR_ID_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Subsystem Vendor ID\n");
- return;
- }
- printf("Subsystem Vendor ID = 0x%04X ",short_data);
- subvendor_id = short_data;
-
- /* get subsystem device ID */
- offset = SUB_DEVICE_ID_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Subsystem Device ID\n");
- return;
- }
- printf("Subsystem Device ID = 0x%04X\n",short_data);
- subdevice_id = short_data;
-
- /* get Region 0 Base Address */
- offset = REGION0_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 0 Base\n");
- return;
- }
- printf("PCI Region 0 Base = 0x%08X\n",long_data);
-
- /* get Region 1 Base Address */
- offset = REGION1_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 1 Base\n");
- return;
- }
- printf("PCI Region 1 Base = 0x%08X\n",long_data);
-
- /* get Region 2 Base Address */
- offset = REGION2_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 2 Base\n");
- return;
- }
- printf("PCI Region 2 Base = 0x%08X\n",long_data);
-
- /* get Region 3 Base Address */
- offset = REGION3_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 3 Base\n");
- return;
- }
- printf("PCI Region 3 Base = 0x%08X\n",long_data);
-
- /* get Region 4 Base Address */
- offset = REGION4_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 4 Base\n");
- return;
- }
- printf("PCI Region 4 Base = 0x%08X\n",long_data);
-
- /* get Region 5 Base Address */
- offset = REGION5_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 5 Base\n");
- return;
- }
- printf("PCI Region 5 Base = 0x%08X\n",long_data);
-
- /* get Expansion ROM Base Address */
- offset = EXP_ROM_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Expansion ROM Base\n");
- return;
- }
- printf("Expansion ROM Base = 0x%08X\n",long_data);
-
- /* get Cardbus CIS pointer */
- offset = CARDBUS_CISPTR_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Cardbus CIS Pointer\n");
- return;
- }
- printf("Cardbus CIS Pointer = 0x%08X\n",long_data);
- } /* end type 0 header */
-
- else /* type 1 header_specific info */
- {
- /* get Bridge Control */
- offset = BRIDGE_CTRL_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Bridge Control Register\n");
- return;
- }
- printf("Bridge Control Reg = 0x%04X ",short_data);
-
- /* get Secondary Status */
- offset = SECONDARY_STAT_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Secondary Status Register\n");
- return;
- }
- printf("Secondary Status Reg = 0x%04X\n",short_data);
-
- /* get Primary Bus Number */
- offset = PRIMARY_BUSNO_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Primary Bus Number\n");
- return;
- }
- printf("Primary Bus No. = 0x%02X ",byte_data);
-
- /* get Secondary Bus Number */
- offset = SECONDARY_BUSNO_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Secondary Bus Number\n");
- return;
- }
- printf("Secondary Bus No. = 0x%02X\n",byte_data);
-
- /* get Subordinate Bus Number */
- offset = SUBORD_BUSNO_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Subordinate Bus Number\n");
- return;
- }
- printf("Subordinate Bus No. = 0x%02X ",byte_data);
-
- /* get Secondary Latency Timer */
- offset = SECONDARY_LAT_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading Secondary Latency Timer\n");
- return;
- }
- printf("Secondary Latency Tmr = 0x%02X\n",byte_data);
-
- /* get IO Base */
- offset = IO_BASE_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading IO Base\n");
- return;
- }
- printf("IO Base = 0x%02X ",byte_data);
-
- /* get IO Limit */
- offset = IO_LIMIT_OFFSET;
- if (sys_read_config_byte (busno,devno,function,offset,&byte_data)
- == ERROR)
- {
- printf("Error reading IO Limit\n");
- return;
- }
- printf("IO Limit = 0x%02X\n",byte_data);
-
- /* get Memory Base */
- offset = MEMORY_BASE_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Memory Base\n");
- return;
- }
- printf("Memory Base = 0x%04X ",short_data);
-
- /* get Memory Limit */
- offset = MEMORY_LIMIT_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Memory Limit\n");
- return;
- }
- printf("Memory Limit = 0x%04X\n",short_data);
-
- /* get Prefetchable Memory Base */
- offset = PREF_MEM_BASE_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Prefetchable Memory Base\n");
- return;
- }
- printf("Pref. Memory Base = 0x%04X ",short_data);
-
- /* get Prefetchable Memory Limit */
- offset = PREF_MEM_LIMIT_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading Prefetchable Memory Limit\n");
- return;
- }
- printf("Pref. Memory Limit = 0x%04X\n",short_data);
-
- /* get IO Base Upper 16 Bits */
- offset = IO_BASE_UPPER_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading IO Base Upper 16 Bits\n");
- return;
- }
- printf("IO Base Upper 16 Bits = 0x%04X ",short_data);
-
- /* get IO Limit Upper 16 Bits */
- offset = IO_LIMIT_UPPER_OFFSET;
- if (sys_read_config_word (busno,devno,function,offset,&short_data)
- == ERROR)
- {
- printf("Error reading IO Limit Upper 16 Bits\n");
- return;
- }
- printf("IO Limit Upper 16 Bits= 0x%04X\n",short_data);
-
- /* get Prefetchable Base Upper 32 Bits */
- offset = PREF_BASE_UPPER_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Prefetchable Base Upper 32 Bits\n");
- return;
- }
- printf("Pref. Base Up. 32 Bits= 0x%08X\n",long_data);
-
- /* get Prefetchable Limit Upper 32 Bits */
- offset = PREF_LIMIT_UPPER_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Prefetchable Limit Upper 32 Bits\n");
- return;
- }
- printf("Pref. Lmt. Up. 32 Bits= 0x%08X\n",long_data);
-
-
- /* get Region 0 Base Address */
- offset = REGION0_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 0 Base\n");
- return;
- }
- printf("PCI Region 0 Base = 0x%08X\n",long_data);
-
- /* get Region 1 Base Address */
- offset = REGION1_BASE_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Region 1 Base\n");
- return;
- }
- printf("PCI Region 1 Base = 0x%08X\n",long_data);
-
- /* get Expansion ROM Base Address */
- offset = TYPE1_EXP_ROM_OFFSET;
- if (sys_read_config_dword (busno,devno,function,offset,&long_data)
- == ERROR)
- {
- printf("Error reading Expansion ROM Base\n");
- return;
- }
- printf("Expansion ROM Base = 0x%08X\n",long_data);
-
- } /* end type 1 header */
-
- }
-}
-
/* check if host of backplane */
-int isHost()
+int isHost(void)
{
- if (*BACKPLANE_DET_REG & BP_HOST_BIT)
- return TRUE;
- else
- return FALSE;
+ if (*BACKPLANE_DET_REG & BP_HOST_BIT)
+ return TRUE;
+ else
+ return FALSE;
}
-
-
-/*****************************************************************************
-* sys_pci_device_initialization - initialize PCI I/O devices
-*
-* This function is responsible for initializing all PCI I/O devices for proper
-* PCI operation. All I/O devices are mapped into appropriate locations in the
-* PCI address space (based on size and alignment requirements). This function
-* must ensure that no bus conflicts exist. This function is also responsible
-* for initializing cache line size, latency timer, DEVSEL# timing, and parity
-* error response. This function fills out the data structure which is passed
-* in to it. This function will return SUCCESSFUL if at least one I/O
-* controller can be successfully configured. This function will return ERROR
-* if no I/O controllers can be initialized.
-*
-*/
-void sys_pci_device_initialization (PCI_DATA* pci_data)
-{
-
- volatile int i;
-
- bus0_lastbus = PRIMARY_BUS_NUM; /* last bus number behind bus 0 (primary bus ) */
- bus1_lastbus = SECONDARY_BUS_NUM; /* last bus number behind bus 1 (secondary bus) */
-
- pci_data->num_devices = 0; /* total number of devices configured */
- pci_data->num_functions = 0; /* total number of functions configured */
-
- init_312_pci(); /* initialize the ATU, MU and bridge on the 80312 */
-
- if (isHost())
- {
- /* If the IQ80310 board is connected to the backplane it has to initialize the Primary PCI bus */
-
- /* set PCI base addresses for primary bus */
-
- memspace_ptr[PRIMARY_BUS_NUM] = PRIMARY_MEM_BASE;
- memspace_limit[PRIMARY_BUS_NUM] = PRIMARY_MEM_LIMIT;
-
- iospace_ptr[PRIMARY_BUS_NUM] = PRIMARY_IO_BASE;
- iospace_limit[PRIMARY_BUS_NUM] = PRIMARY_IO_LIMIT;
-
- PRINT_OFF();
-
- /* Initialize Primary PCI bus */
- sys_pci_bus_init (PRIMARY_BUS_NUM, PRIMARY_BUS_NUM, pci_data);
- }
-
- /* Initialization of the Secondary PCI bus */
-
- /* set PCI base addresses for secondary bus */
-
- memspace_ptr[SECONDARY_BUS_NUM] = SECONDARY_MEM_BASE;
- memspace_limit[SECONDARY_BUS_NUM] = SECONDARY_MEM_LIMIT;
-
- iospace_ptr[SECONDARY_BUS_NUM] = SECONDARY_IO_BASE;
- iospace_limit[SECONDARY_BUS_NUM] = SECONDARY_IO_LIMIT;
-
- PRINT_OFF();
-
- /* Initialize Secondary PCI bus */
- sys_pci_bus_init (SECONDARY_BUS_NUM, SECONDARY_BUS_NUM, pci_data);
-
-
- /* Set absolute last secondary bus */
- if (bus0_lastbus > bus1_lastbus)
- lastbus = bus0_lastbus;
- else
- lastbus = bus1_lastbus;
-
- PRINT_OFF();
-
- /* before exiting, configure and enable FIQ and IRQ interrupts */
-
- _enableFiqIrq(); /* enable FIQ and IRQ interrupts in CP13 */
-
- config_ints(); /* configure interrupts */
-
- /* wait a while to clear out any unwanted NMI interrupts */
- for (i = 0; i < 100000; i++)
- ;
-
- PRINT_ON();
-
- /* enable ECC single bit correction and multi-bit reporting
- - initialization code only enables correction */
- *(volatile unsigned long *)ECCR_ADDR = 0x6;
-}
-
-
-/*****************************************************************************
-* sys_pci_bus_init - initialize PCI I/O devices
-*
-* This function is responsible for initializing all PCI I/O devices for proper
-* PCI operation. All I/O devices are mapped into appropriate locations in the
-* PCI address space (based on size and alignment requirements). This function
-* must ensure that no bus conflicts exist. This function is also responsible
-* for initializing cache line size, latency timer, DEVSEL# timing, and parity
-* error response. This function fills out the data structure which is passed
-* in to it. This function will return SUCCESSFUL if at least one I/O
-* controller can be successfully configured. This function will return ERROR
-* if no I/O controllers can be initialized.
-*/
-static void sys_pci_bus_init(UINT bus, UINT root_bus, PCI_DATA* pci_data)
-{
- UINT device, function;
- USHORT vendor, device_id;
- UINT regno;
- ULONG regvalue;
- USHORT regshort;
- UCHAR regchar;
- UCHAR intpin, intline;
- UINT line;
- UCHAR header_type;
- ULONG rom_enabled;
- UINT base_addr_reg_start;
- UINT base_addr_reg_end;
- UINT exp_rom_baseaddr;
- int multifunction;
-
-/* bridge initialization variables */
- ULONG class_code;
- UINT secondary_bus_number;
- UCHAR iospace_type;
- UCHAR data_byte;
- USHORT data_word;
- ULONG membase, iobase;
- ULONG memlimit, iolimit;
- int no_memory, no_io;
-
-#ifdef DEBUG_PCI
- printf ("Configuring PCI Bus %d.\n", bus);
- printf ("PCI Root Bus %d.\n", root_bus);
- PRINT_OFF();
-#endif
-
-for (device = 0; device <= MAX_DEVICE_NUMBER; device++)
-{
-#ifdef DEBUG_PCI
- printf ("\nConfiguring device %d.\n\n", device);
-#endif
-
- /* assume non-multifunction device at start */
- multifunction = FALSE;
-
- for (function = 0; function < MAX_FUNCTION_NUMBER; function ++)
- {
-
-#ifdef DEBUG_PCI
- printf ("Configuring function %d.\n", function);
-#endif
- /* To determine whether a device is installed in a particular slot, */
- /* we attempt to read the vendor ID from that slot. If there's */
- /* nothing there, the bridge should return 0xffff (and signal a */
- /* master abort). Otherwise, there is something there and we need */
- /* to configure it. */
- if ((sys_read_config_word(bus, device, function, VENDOR_ID_OFFSET, &vendor) == ERROR) || (vendor == 0xffff))
- {
- /* This means no device found */
-#ifdef DEBUG_PCI
- printf ("\nNo device.\n");
-#endif
- break; /* Go on to the next device */
- }
-
- /* We'll only get here if we got a real device/function */
-
- /* Count the number of devices */
- if (function == 0) (pci_data->num_devices)++;
-
- /* Count the number of functions */
- (pci_data->num_functions)++;
-
-#ifdef DEBUG_PCI
- printf ("Vendor: %x\n", vendor);
-#endif
-
- /* Read the Device ID */
- sys_read_config_word (bus,device,function,DEVICE_ID_OFFSET,&device_id);
-
-#ifdef DEBUG_PCI
- printf("\n");
- printf("Configuring PCI Bus : %d\n", bus);
- printf(" PCI Device: %d\n", device);
- printf(" Vendor Id : 0x%08X\n", vendor);
- printf(" Device Id : 0x%08X\n", device_id);
-#endif
-
- /* Read the Configuration Header Type to determine configuration */
- if (sys_read_config_byte (bus,device,function,HEADER_TYPE_OFFSET,&header_type)== ERROR) continue;
-
- /* determine if multifunction device */
- if ((header_type & MULTIFUNCTION_DEVICE) && (function == 0))
- {
-#ifdef DEBUG_PCI
- printf ("Multifunction Device Found...\n");
-#endif
- multifunction = TRUE;
- }
-
- /* strip off multifunction device indicator bit */
- header_type &= 0x7f;
-
- switch (header_type)
- {
- case STANDARD_HEADER:
- base_addr_reg_start = 0x10; /* Base Address Reg. Start Offset */
- base_addr_reg_end = 0x24; /* Base Address Reg. End Offset */
- exp_rom_baseaddr = 0x30; /* Expansion ROM Base Addr. Reg Offset */
- break;
-
- case PCITOPCI_HEADER:
- base_addr_reg_start = 0x10; /* Base Address Reg. Start Offset */
- base_addr_reg_end = 0x14; /* Base Address Reg. End Offset */
- exp_rom_baseaddr = 0x38; /* Expansion ROM Base Addr. Reg Offset */
- break;
-
- default:
- printf ("Header Type Not Supported, 0x%02X\n", header_type);
- continue; /* skip over device */
- break;
- }
-
- /* We cycle through the base registers, first writing out all */
- /* ones to the register, then reading it back to determine the */
- /* requested size in either I/O or memory space. Then we */
- /* align the top of memory or i/o space pointer, write it to */
- /* the register, and increment it. I say we so you won't feel */
- /* excluded. */
- for (regno = base_addr_reg_start; regno <= base_addr_reg_end; regno += 4)
- {
-
- /* Write out all 1's to the base register, then read it back */
- regvalue = 0xffffffff;
- sys_write_config_dword(bus,device,function,regno,(UINT32*)®value);
- sys_read_config_dword (bus,device,function,regno,(UINT32*)®value);
-
- /* Some number of the lower bits of regvalue will be clear */
- /* indicating a don't care position. The more clear bits, */
- /* the larger the requested mapping space. */
-
- if (regvalue == 0) /* ...this reg not used. */
- ;
-
- /*---------------------------------------------------------*/
- /* I/O space mapping */
- /*---------------------------------------------------------*/
- else if ((regvalue & 3) == 1) /* ...this is I/O space */
- {
- ULONG requested_size;
-
- /* Align iospace_ptr for the requested size. All bit */
- /* positions clear in regvalue must be clear in */
- /* iospace_ptr. */
- requested_size = ~(regvalue & 0xfffffffe);
-
-#ifdef DEBUG_PCI
- printf ("Configuration for I/O space...\n");
- printf ("Size request: %x; ", requested_size);
- printf ("IOspace_ptr: %x\n", iospace_ptr[root_bus]);
-#endif
-
- /* check to make sure that there is enought iospace left to grant */
- if ((iospace_ptr[root_bus] + requested_size) > iospace_limit[root_bus])
- {
- printf ("\nPCI Configuration ERROR: Out of I/O Space on Bus %d!\n", bus);
- printf (" No I/O Space Allocated to Device %d, Function %d.\n", device, function);
- return;
- }
-
- /* Align the space pointer if necessary */
- if (iospace_ptr[root_bus] & requested_size)
- {
- iospace_ptr[root_bus] &= ~requested_size;
- iospace_ptr[root_bus] += requested_size + 1;
- }
-#ifdef DEBUG_PCI
- printf("Adjusted I/O Space Ptr: %x\n", iospace_ptr[root_bus]);
- printf(" I/O Space Size : 0x%08X\n", requested_size);
- printf(" I/O Space Base : 0x%08X\n", iospace_ptr[root_bus]);
-#endif /* Write out the adjusted iospace pointer. */
-
- sys_write_config_dword (bus,device,function,regno,(UINT32*)&iospace_ptr[root_bus]);
-
- /* Update space pointer */
- iospace_ptr[root_bus] += requested_size + 1;
- }
-
- /*---------------------------------------------------------*/
- /* Memory space mapping */
- /*---------------------------------------------------------*/
- else if ((regvalue & 1) == 0) /* ...this is memory space */
- {
- ULONG requested_size;
-
- /* Type is encoded in bits 1 and 2 */
- /* 64 bit space (10) is an error for the moment, as is */
- /* the reserved value, 11. */
- if (regvalue & 0x4)
- {
- printf ("Type error in base register.\n");
- break;
- }
-
- /* Align memspace_ptr for the requested size. All bit */
- /* positions clear in regvalue must be clear in */
- /* memspace_ptr. */
- requested_size = ~(regvalue & 0xfffffff0);
-
-#ifdef DEBUG_PCI
- printf ("Configuration for memory space.\n");
- printf ("Size request: %x; ", requested_size);
- printf ("Membase_ptr: %x\n", memspace_ptr[root_bus]);
-#endif
-
-
- /* check to make sure that there is enough memspace left to grant */
- if ((memspace_ptr[root_bus] + requested_size) > memspace_limit[root_bus])
- {
- printf ("\nPCI Configuration ERROR: Out of Memory Space on Bus %d!\n", bus);
- printf (" No Memory Space Allocated to Device %d, Function %d.\n", device, function);
- printf ("Root Bus = %d, Memory Ptr = 0x%08X, Requested Size = 0x%08X, Memory Limit = 0x%08X\n",
- root_bus, memspace_ptr[root_bus], requested_size, memspace_limit[root_bus]);
-
- return;
- }
-
- if (memspace_ptr[root_bus] & requested_size)
- {
- memspace_ptr[root_bus] &= ~requested_size;
- memspace_ptr[root_bus] += requested_size + 1;
- }
-
-#ifdef DEBUG_PCI
- printf ("Adjusted Membase_ptr: %x\n", memspace_ptr[root_bus]);
- printf(" Memory Space Size : 0x%08X\n", requested_size);
- printf(" Memory Space Base : 0x%08X\n", memspace_ptr[root_bus]);
-#endif
- /* Write out the adjusted memory pointer */
- sys_write_config_dword (bus,device,function,regno,(UINT32*)&memspace_ptr[root_bus]);
- memspace_ptr[root_bus] += requested_size + 1;
- }
- }
-
- /*-------------------------------------------------------------*/
- /* Expansion ROM mapping */
- /* The expansion ROM is handled in the same way as the other */
- /* PCI base registers. If the lowest bit in this register is */
- /* set, memory-mapped accesses are not possible, since the ROM */
- /* is active. (Only one decoder). */
- /*-------------------------------------------------------------*/
-
- /* Store the state of the ROM enabled bit so we can restore it */
- sys_read_config_dword (bus,device,function,exp_rom_baseaddr,(UINT32*)®value);
- rom_enabled = regvalue & 1;
-
- /* Write out all 1's to the non-reserved bits of the base register, then read it back */
- regvalue = 0xffffffff;
- sys_write_config_dword(bus,device,function,EXP_ROM_OFFSET,(UINT32*)®value);
- sys_read_config_dword (bus,device,function,EXP_ROM_OFFSET,(UINT32*)®value);
-
- /* Some number of the lower bits of regvalue will be clear */
- /* indicating a don't care position. The more clear bits, */
- /* the larger the requested mapping space. */
-
- if ((regvalue & 0xffff800) != 0) /* No mapping if it's 0 */
- {
- ULONG requested_size;
-
-#ifdef DEBUG_PCI
- printf ("Expansion ROM detected.\n");
-#endif
-
- /* Expansion ROMs will map into memory space, so... */
- /* Align memspace_ptr for the requested size. All bit */
- /* positions clear in regvalue must be clear in */
- /* memspace_ptr. */
- requested_size = ~(regvalue & 0xfffff800);
-
-#ifdef DEBUG_PCI
- printf ("Size request: %x; ", requested_size);
- printf ("Membase_ptr: %x\n", memspace_ptr[root_bus]);
-#endif
-
- /* check to make sure that there is enought memspace left to grant */
- if ((memspace_ptr[root_bus] + requested_size) > memspace_limit[root_bus])
- {
- printf ("\nPCI Configuration ERROR: Out of Memory Space on Bus %d!\n", bus);
- printf (" No Expansion ROM Space Allocated to Device %d, Function %d.\n", device, function);
- return;
- }
-
- if (memspace_ptr[root_bus] & requested_size)
- {
- memspace_ptr[root_bus] &= ~requested_size;
- memspace_ptr[root_bus] += requested_size + 1;
- }
-
-#ifdef DEBUG_PCI
- printf("Adjusted Membase_ptr: %x\n", memspace_ptr[root_bus]);
- printf(" Exp. ROM Space Size : 0x%08X\n", requested_size);
- printf(" Exp. ROM Space Base : 0x%08X\n", memspace_ptr[root_bus]);
-#endif
- /* Write out the adjusted memory pointer */
- regvalue = memspace_ptr[root_bus] | rom_enabled;
- sys_write_config_dword (bus,device,function,EXP_ROM_OFFSET,(UINT32*)®value);
- memspace_ptr[root_bus] += requested_size + 1;
-
- } /* End of expansion ROM mapping. */
-
- /* No expansion ROM to map so disable expansion ROM address decodes */
- else /* If no ROM space, clear the decode bit */
- {
- regvalue = 0;
- sys_write_config_dword (bus,device,function,EXP_ROM_OFFSET,(UINT32*)®value);
- }
-
-
- /*-------------------------------------------------------------*/
- /* Miscellaneous settings */
- /*-------------------------------------------------------------*/
-
- /* Read interrupt pin, write interrupt line according to PCI spec */
- sys_read_config_byte (bus,device,function,INT_PIN_OFFSET,&intpin);
- pci_to_xint(device, intpin, (int*)&line);
- intline = line;
- sys_write_config_byte (bus,device,function,INT_LINE_OFFSET,&intline);
-
- /* Set Latency value to relatively and arbitrary small number */
- regchar = LATENCY_VALUE;
- sys_write_config_byte (bus,device,function,LATENCY_TIMER_OFFSET,®char);
-
- if (header_type != PCITOPCI_HEADER)
- {
- /* Set the master enable bit, and enable I/O and Mem spaces */
- /* in the device Command Register only for non-bridge devices */
- sys_read_config_word (bus,device,function,COMMAND_OFFSET,®short);
-
- regshort |= PCI_CMD_IOSPACE | PCI_CMD_MEMSPACE | PCI_CMD_BUS_MASTER;
- sys_write_config_word(bus,device,function,COMMAND_OFFSET,®short);
-
- }
-
- /****** Bridge Configuration *******/
-
- /* To determine whether an installed device is a PCI-to-PCI Bridge
- device, read the Base Class and the Sub Class from the device's
- Configuration header. If the Base Class = 0x06 and the
- Sub Class = 0x04, the device is a PCI-to-PCI Bridge and requires
- additional initialization including the initialization of its
- Secondary PCI bus. */
-
- if (sys_read_config_dword (bus,device,function,REVISION_OFFSET,(UINT32*)&class_code) != ERROR)
- {
- /* Parse the class code into Base Class and Sub Class */
- if ((((class_code >> 16) & 0x0000ffff) == 0x0604) &&
- (header_type == PCITOPCI_HEADER))
- {
-
- #ifdef DEBUG_PCI
- printf ("PCI-to-PCI Bridge Device.\n");
- printf ("Hit a Key to Continue...\n");
- hexIn();
- #endif
-
- if (root_bus == 0) /* root bus = primary bus */
- {
-
- if (bus0_lastbus == 0)
- bus0_lastbus = 2;
- else
- bus0_lastbus = bus0_lastbus + 1;
-
- /* assign new PCI bus number */
- secondary_bus_number = bus0_lastbus;
- }
-
- else /* root bus = secondary bus */
- {
- if (bus1_lastbus == 1)
- {
- if (bus0_lastbus != 0)
- bus1_lastbus = bus0_lastbus + 1;
- else
- bus1_lastbus = 2;
- }
- else
- bus1_lastbus = bus1_lastbus + 1;
-
- /* assign new PCI bus number */
- secondary_bus_number = bus1_lastbus;
- }
-
-
-
- #ifdef DEBUG_PCI
- printf ("Secondary Bus Number = %d.\n",secondary_bus_number);
- #endif
-
- /* set up the bus numbers in the bridge's config. space */
-
- /* Primary Bus Number */
- data_byte = (UCHAR)root_bus;
- sys_write_config_byte (bus,device,function,PRIMARY_BUSNO_OFFSET,&data_byte);
-
- /* Secondary Bus Number */
- data_byte = (UCHAR)secondary_bus_number;
- sys_write_config_byte (bus,device,function,SECONDARY_BUSNO_OFFSET,&data_byte);
-
- /* Set Subordinate Bus Number to a maximum so that config cycles
- will be passed on to devices located on subordinate buses */
- data_byte = (UCHAR)MAX_SUB_BUSNO;
- sys_write_config_byte (bus,device,function,SUBORD_BUSNO_OFFSET,&data_byte);
-
- #ifdef DEBUG_PCI
- sys_read_config_byte (bus,device,function,PRIMARY_BUSNO_OFFSET,&data_byte);
- printf ("Primary Bus = %d\n", data_byte);
- sys_read_config_byte (bus,device,function,SECONDARY_BUSNO_OFFSET,&data_byte);
- printf ("Secondary Bus = %d\n", data_byte);
- sys_read_config_byte (bus,device,function,SUBORD_BUSNO_OFFSET,&data_byte);
- printf ("Subordinate Bus = %d\n", data_byte);
- #endif
-
- /* To figure out the PCI Memory space and PCI I/O space
- windows on the bridge, read the memory and I/O space
- information before the secondary bus is configured
- and then read it afterwards to determine the window
- size for each PCI region
-
- For secondary busses, the Memory space window of the
- PCI-to-PCI bridge must start and end on a 1 Mbyte boundary
-
- For secondary busses, the I/O space window of the
- PCI-to-PCI bridge must start and end on a 4 Kbyte boundary
- */
-
- /* round up start of PCI memory space to a 1 Mbyte start address */
- if (memspace_ptr[root_bus] & 0xfffff)
- {
- memspace_ptr[root_bus] &= ~(0xfffff);
- memspace_ptr[root_bus] += 0x100000;
- }
-
- /* round up start of PCI I/O space to a 4 Kbyte start address */
- if (iospace_ptr[root_bus] & 0xfff)
- {
- iospace_ptr[root_bus] &= ~(0xfff);
- iospace_ptr[root_bus] += 0x1000;
- }
-
- membase = memspace_ptr[root_bus];
- iobase = iospace_ptr[root_bus];
-
- #ifdef DEBUG_PCI
- printf ("*** About to do a recursive call ***\n");
- printf ("Hit a Key to Continue...\n");
- hexIn();
- #endif
-
- /* initialize the subordinate PCI bus */
- sys_pci_bus_init (secondary_bus_number, root_bus, pci_data);
-
- #ifdef DEBUG_PCI
- printf ("Returned from previous recursive call.\n");
- #endif
-
- /* Upon return, set the correct Subordinate Bus Number */
- if (root_bus == 0)
- data_byte = (UCHAR) bus0_lastbus;
- else
- data_byte = (UCHAR) bus1_lastbus;
-
- #ifdef DEBUG_PCI
- printf ("Subordinate Bus Number Now = %d\n", (int)data_byte);
- printf ("Hit a Key to Continue...\n");
- hexIn();
- #endif
- sys_write_config_byte (bus,device,function,SUBORD_BUSNO_OFFSET,&data_byte);
-
- /* round up end of PCI memory space to a 1 Mbyte start address */
- if (memspace_ptr[root_bus] & 0xfffff)
- {
- memspace_ptr[root_bus] &= ~(0xfffff);
- memspace_ptr[root_bus] += 0x100000;
- }
-
- /* round up end of PCI I/O space to a 4 Kbyte start address */
- if (iospace_ptr[root_bus] & 0xfff)
- {
- iospace_ptr[root_bus] &= ~(0xfff);
- iospace_ptr[root_bus] += 0x1000;
- }
-
- memlimit = memspace_ptr[root_bus] - 1;
- iolimit = iospace_ptr[root_bus] - 1;
-
- /* Assume bridge has memory request unless told otherwise */
- no_memory = FALSE;
- no_io = FALSE;
-
- /* if there is no requested memory range, set the membase and
- memlimit values to zero and set the no_memory range flag */
- if (membase == (memspace_ptr[root_bus]))
- {
- membase = 0;
- memlimit = 0;
- no_memory = TRUE;
- }
-
- /* if there is no requested IO range, set the iobase and
- iolimit values to zero and set the no_io range flag */
- if (iobase == (iospace_ptr[root_bus]))
- {
- iobase = 0;
- iolimit = 0;
- no_io = TRUE;
- }
-
- /* Determine if the Bridge supports 16 or 32 bit I/O space decodes */
- sys_read_config_byte (bus,device,function,IO_BASE_OFFSET,&iospace_type);
-
- /* 16 Bit I/O space for ISA compatibility
- - fill in only the IO Base and IO Limit registers */
- if (((iospace_type & 0x0f) == 0x00) &&
- (!(iolimit & 0xffff0000)))
- {
- #ifdef DEBUG_PCI
- printf ("Bridge supports 16 Bit I/O Space\n");
- #endif
- /* I/O Base Register */
- data_byte = (UCHAR)((iobase & 0x0000f000) >> 8);
- sys_write_config_byte (bus,device,function,IO_BASE_OFFSET,&data_byte);
- #ifdef DEBUG_PCI
- printf ("I/O Base Register = 0x%02X\n", data_byte);
- #endif
-
- /* I/O Limit Register */
- data_byte = (UCHAR)((iolimit & 0x0000f000) >> 8);
- sys_write_config_byte (bus,device,function,IO_LIMIT_OFFSET,&data_byte);
- #ifdef DEBUG_PCI
- printf ("I/O Limit Register = 0x%02X\n", data_byte);
- #endif
- }
-
- /* 32 Bit I/O space
- - fill in the IO Base and IO Limit registers
- - fill in the IO Base Upper and IO Limit Upper registers */
- else if ((iospace_type & 0x0f) == 0x01)
- {
- #ifdef DEBUG_PCI
- printf ("Bridge supports 32 Bit I/O Space\n");
- #endif
-
- /* I/O Base Register */
- data_byte = (UCHAR)((iobase & 0x0000f000) >> 8);
- sys_write_config_byte (bus,device,function,IO_BASE_OFFSET,&data_byte);
- #ifdef DEBUG_PCI
- printf ("I/O Base Register = 0x%02X\n", data_byte);
- #endif
-
- /* I/O Limit Register */
- data_byte = (UCHAR)((iolimit & 0x0000f000) >> 8);
- sys_write_config_byte (bus,device,function,IO_LIMIT_OFFSET,&data_byte);
- #ifdef DEBUG_PCI
- printf ("I/O Limit Register = 0x%02X\n", data_byte);
- #endif
-
- /* I/O Base Upper 16 Bits Register */
- data_word = (USHORT)((iobase & 0xffff0000) >> 16);
- sys_write_config_word (bus,device,function,IO_BASE_UPPER_OFFSET,&data_word);
- #ifdef DEBUG_PCI
- printf ("I/O Base Upper 16 Bits Register = 0x%04X\n", data_word);
- #endif
-
- /* I/O Limit Upper 16 Bits Register */
- data_word = (USHORT)((iolimit & 0xffff0000) >> 16);
- sys_write_config_word (bus,device,function,IO_LIMIT_UPPER_OFFSET,&data_word);
- #ifdef DEBUG_PCI
- printf ("I/O Limit Upper 16 Bits Register = 0x%04X\n", data_word);
- #endif
- }
-
- /* Memory Base Register */
- data_word = (USHORT)((membase & 0xfff00000) >> 16);
- sys_write_config_word (bus,device,function,MEMORY_BASE_OFFSET,&data_word);
- #ifdef DEBUG_PCI
- printf ("Memory Base Register = 0x%04X\n", data_word);
- #endif
-
- /* Memory and Prefetchable Memory Limit Registers */
- data_word = (USHORT)((memlimit & 0xfff00000) >> 16);
- sys_write_config_word (bus,device,function,MEMORY_LIMIT_OFFSET,&data_word);
- sys_write_config_word (bus,device,function,PREF_MEM_LIMIT_OFFSET,&data_word);
- #ifdef DEBUG_PCI
- printf ("Memory Limit Register = 0x%04X\n", data_word);
- #endif
-
-
- /* Currently does not support prefetchable memory.
- Set the prefetchable memory range to an unused value so that
- a user can not make a prefetchable memory access */
-
- /* Prefetchable Memory Base Register*/
- data_word = 0xffff;
- sys_write_config_word (bus,device,function,PREF_MEM_BASE_OFFSET,&data_word);
- #ifdef DEBUG_PCI
- printf ("Prefetchable Memory Base Register = 0x%04X\n", data_word);
- #endif
-
-
- /* Prefetchable Memory Limit Register*/
- data_word = 0xffff;
- sys_write_config_word (bus,device,function,PREF_MEM_LIMIT_OFFSET,&data_word);
- #ifdef DEBUG_PCI
- printf ("Prefetchable Memory Limit Register = 0x%04X\n", data_word);
- #endif
-
- /* Set the secondary latency timer on the device. We use the value 0x0f,*/
- /* which is approximately what you might get if you used the */
- /* formula found in the NCR SCSI adapter documentation: */
- /* Latency Timer = 2 + (Burst size * (typical wait states + 1)) */
- regchar = LATENCY_VALUE;
- sys_write_config_byte (bus,device,function,SECONDARY_LAT_OFFSET,®char);
-
- /* Reset the Command Register for PCI to PCI bridges */
- /* (bridges have different settings in command register) */
- sys_read_config_word (bus,device,function,COMMAND_OFFSET,®short);
- regshort |= BRIDGE_MASTER_ENAB | BRIDGE_SERR_ENAB;
- /* if memory space is requested, memory transactions should
- be turned on */
- if (!no_memory)
- regshort |= BRIDGE_MEMSPACE_ENAB;
- /* if io space is requested, memory transactions should
- be turned on */
- if (!no_io)
- regshort |= BRIDGE_IOSPACE_ENAB;
- sys_write_config_word(bus,device,function,COMMAND_OFFSET,®short);
-
- /* Set the Bridge Control Register */
- sys_read_config_word (bus,device,function,BRIDGE_CTRL_OFFSET,®short);
- regshort |= BRIDGE_PARITY_ERR | BRIDGE_SEER_ENAB | BRIDGE_MASTER_ABORT;
- sys_write_config_word(bus,device,function,BRIDGE_CTRL_OFFSET,®short);
-
- }
- }
-
- #ifdef DEBUG_PCI
- printf ("\nHit a Key to Continue...\n");
- hexIn();
- #endif
-
- /* if not a multifunction device, go on to next device */
- if (multifunction == FALSE)
- break;
- } /* End for (function...) */
-} /* End for (device...) */
-
-#ifdef DEBUG_PCI
- printf ("Leaving the init function for bus %d.\n", bus);
- printf ("\nHit a Key to Continue...\n");
- hexIn();
-#endif
-
-return;
-}
-
-/***************************************************************************
-*
-* show_pci - print out Device/Vendor ID of all PCI devices in system
-*
-*/
-void show_pci(void)
-{
-unsigned char header_type;
-unsigned short vendor, device_id;
-unsigned int bus, device, function;
-
-
- printf (" Bus Device Function Vendor ID Device ID\n");
- printf ("----- ------ -------- --------- ---------\n");
-
- for (bus = 0; bus < MAX_PCI_BUSES; bus++)
- {
- for (device = 0; device <= MAX_DEVICE_NUMBER; device++)
- {
- for (function = 0; function <= MAX_FUNCTION_NUMBER; function++)
- {
- if ((sys_read_config_word (bus, device, function, VENDOR_ID_OFFSET, &vendor) == ERROR) || (vendor == 0xffff))
- /* This means no device found */
- break; /* Go on to the next device */
- else
- {
- sys_read_config_word (bus, device, function, DEVICE_ID_OFFSET, &device_id);
- printf (" 0x%02X 0x%02X 0x%02X",bus,device,function);
- printf (" 0x%04X 0x%04X\n", vendor,device_id);
- }
-
- /* before we go on to the next function, make sure that the
- device is truly a multi-function device, otherwise we may
- get aliasing */
- sys_read_config_byte (bus, device, function, HEADER_TYPE_OFFSET, &header_type);
-
- if (!(header_type & MULTIFUNCTION_DEVICE)) break;
-
- } /* End for (function) */
- } /* End for (device) */
- } /* End for (bus) */
-}
-
-extern unsigned hal_dram_size;
-
-/*********************************************************************************
-* init_312_pci - Initialize the Primary and Secondary ATUs, Messaging Unit, and
-* PCI-to-PCI bridge on the 80312 Companion chip
-*
-*/
-void init_312_pci(void)
-{
- UINT32 *ATU_reg;
- UINT32 *MU_reg;
- UINT16 *ATU_reg_16;
- UINT8 *ATU_reg_8;
- UINT32 limit_reg;
- UINT32 adj_dram_size;
- UINT16 *BR_reg_16;
- UINT8 *BR_reg_8;
-
- /********* vendor / device id **********/
-
- /* set subsytem vendor ID */
- ATU_reg_16 = (UINT16 *) ASVIR_ADDR;
- *ATU_reg_16 = 0x113C;
-
- /* set subsytem ID = 700 hex for PCI700 */
- ATU_reg_16 = (UINT16 *) ASIR_ADDR;
- *ATU_reg_16 = 0x0700;
-
-
- /******* Primary Inbound ATU *********/
-
- /* set primary inbound ATU translate value register to point to base of local DRAM */
- ATU_reg = (UINT32 *) PIATVR_ADDR;
- *ATU_reg = MEMBASE_DRAM & 0xFFFFFFFC;
-
- /* set primary inbound ATU limit register to include all of installed DRAM.
- This value used as a mask. */
- ATU_reg = (UINT32 *) PIALR_ADDR;
- adj_dram_size = hal_dram_size;
- limit_reg = (0xFFFFFFFF-(adj_dram_size-1)) & 0xFFFFFFF0;
- *ATU_reg = limit_reg;
-
- if (isHost() == TRUE)
- {
- /* set the primary inbound ATU base address to the start of DRAM */
- ATU_reg = (UINT32 *) PIABAR_ADDR;
- *ATU_reg = MEMBASE_DRAM & 0xFFFFF000;
-
- /********* Set Primary Outbound Windows *********/
-
- /* Note: The primary outbound ATU memory window value register
- and i/o window value registers are defaulted to 0 */
-
- /* set the primary outbound windows to directly map Local - PCI requests */
- /* outbound memory window */
- ATU_reg = (UINT32 *) POMWVR_ADDR;
- *ATU_reg = PRIMARY_MEM_BASE;
-
- /* outbound DAC Window */
- ATU_reg = (UINT32 *) PODWVR_ADDR;
- *ATU_reg = PRIMARY_DAC_BASE;
-
- /* outbound I/O window */
- ATU_reg = (UINT32 *) POIOWVR_ADDR;
- *ATU_reg = PRIMARY_IO_BASE;
- }
-
- /******** Secondary Inbound ATU ***********/
-
- /* set secondary inbound ATU translate value register to point to base of local DRAM */
- ATU_reg = (UINT32 *) SIATVR_ADDR;
- *ATU_reg = MEMBASE_DRAM & 0xFFFFFFFC;
-
- /* set secondary inbound ATU base address to start of DRAM */
- ATU_reg = (UINT32 *) SIABAR_ADDR;
- *ATU_reg = MEMBASE_DRAM & 0xFFFFF000;
-
- /* set secondary inbound ATU limit register to include all of
- installed DRAM. This value used as a mask. */
-
- /* cyclone merge 1/21/97 */
- /* always allow secondary pci access to all memory (even with A0 step) */
- limit_reg = (0xFFFFFFFF - (adj_dram_size - 1)) & 0xFFFFFFF0;
- ATU_reg = (UINT32 *) SIALR_ADDR;
- *ATU_reg = limit_reg;
-
-
- /********** Set Secondary Outbound Windows ***********/
-
- /* Note: The secondary outbound ATU memory window value register
- and i/o window value registers are defaulted to 0 */
-
- /* set the secondary outbound window to directly map Local - PCI requests */
- /* outbound memory window */
- ATU_reg = (UINT32 *) SOMWVR_ADDR;
- *ATU_reg = SECONDARY_MEM_BASE;
-
- /* outbound DAC Window */
- ATU_reg = (UINT32 *) SODWVR_ADDR;
- *ATU_reg = SECONDARY_DAC_BASE;
-
- /* outbound I/O window */
- ATU_reg = (UINT32 *) SOIOWVR_ADDR;
- *ATU_reg = SECONDARY_IO_BASE;
-
- /*********** command / config / latency registers ************/
-
- if (isHost() == TRUE)
- {
- /* allow primary ATU to act as a bus master, respond to PCI
- memory accesses, assert P_SERR#, and enable parity checking */
- ATU_reg_16 = (UINT16 *) PATUCMD_ADDR;
- *ATU_reg_16 = (PCI_CMD_SERR_ENAB | PCI_CMD_PARITY | PCI_CMD_BUS_MASTER | PCI_CMD_MEMSPACE);
- }
-
- /* allow secondary ATU to act as a bus master, respond to PCI memory accesses, and assert S_SERR# */
- ATU_reg_16 = (UINT16 *) SATUCMD_ADDR;
- *ATU_reg_16 = (PCI_CMD_SERR_ENAB | PCI_CMD_PARITY | PCI_CMD_BUS_MASTER | PCI_CMD_MEMSPACE);
-
- /* enable primary and secondary outbound ATUs, BIST, and primary bus direct addressing */
- ATU_reg = (UINT32 *) ATUCR_ADDR;
- *ATU_reg = 0x00000006; /* no direct addressing window - enable both ATUs */
-
-
- /************* bridge registers *******************/
-
- if (isHost() == TRUE)
- {
- /* set the bridge command register */
- BR_reg_16 = (UINT16 *) PCR_ADDR;
- *BR_reg_16 = (PCI_CMD_SERR_ENAB | PCI_CMD_PARITY | PCI_CMD_BUS_MASTER | PCI_CMD_MEMSPACE);
-
- /* set the secondary bus number to 1 */
- BR_reg_8 = (UINT8 *) SBNR_ADDR;
- *BR_reg_8 = SECONDARY_BUS_NUM;
-
- /* set the bridge control register */
- BR_reg_16 = (UINT16 *) BCR_ADDR;
- *BR_reg_16 = 0x0823;
-
- /* set the primary bus number to 0 */
- BR_reg_8 = (UINT8 *) PBNR_ADDR;
- *BR_reg_8 = PRIMARY_BUS_NUM;
- }
-
- /* suppress secondary bus idsels to provide */
- /* private secondary devices */
- BR_reg_16 = (UINT16 *) SISR_ADDR;
- *BR_reg_16 = 0x03FF;
-}
Index: hal/arm/xscale/iq80310/current/src/diag/test_menu.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/test_menu.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 test_menu.c
--- hal/arm/xscale/iq80310/current/src/diag/test_menu.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/test_menu.c 13 Nov 2002 15:41:08 -0000
@@ -89,69 +89,62 @@ static void printMenu (MENU_ITEM menuTab
* RETURNS:
*
* The menu item argument, or NULL if the item chosen is QUIT.
*/
MENU_ARG menu (
- MENU_ITEM menuTable[],
- int numMenuItems,
- char *title,
- unsigned long options
- )
+ MENU_ITEM menuTable[],
+ int numMenuItems,
+ char *title,
+ unsigned long options
+ )
{
-int item; /* User's menu item choice */
+ int item; /* User's menu item choice */
/*
* Get the user's first choice. Always display the menu the first time.
*/
item = menuGetChoice (menuTable, numMenuItems, title, MENU_OPT_NONE);
if (item == QUIT)
- return (NULL);
+ return (NULL);
/*
* If the user just wants a value returned, return the argument. If the
* argument is null, return the item number itself.
*/
- if (options & MENU_OPT_VALUE)
- {
- if (menuTable[item].arg == NULL)
- return ((void *)item);
- else
- return (menuTable[item].arg);
+ if (options & MENU_OPT_VALUE) {
+ if (menuTable[item].arg == NULL)
+ return ((void *)item);
+ else
+ return (menuTable[item].arg);
}
/*
* Process menu items until the user selects QUIT
*/
- while (TRUE)
- {
- /*
- * Call the action routine for the chosen item. If the argument is
- * NULL, pass the item number itself.
- */
- if (menuTable[item].actionRoutine != NULL)
- {
- if (menuTable[item].arg == NULL)
- {
- printf("\n");
- (*menuTable[item].actionRoutine) ((void *)item);
- }
- else
- {
- printf("\n");
- (*menuTable[item].actionRoutine) (menuTable[item].arg);
- }
- }
-
- /*
- * Get the next choice, using any display options the user specified.
- */
- item = menuGetChoice (menuTable, numMenuItems, title, options);
- if (item == QUIT)
- return (NULL);
+ while (TRUE) {
+ /*
+ * Call the action routine for the chosen item. If the argument is
+ * NULL, pass the item number itself.
+ */
+ if (menuTable[item].actionRoutine != NULL) {
+ if (menuTable[item].arg == NULL) {
+ printf("\n");
+ (*menuTable[item].actionRoutine) ((void *)item);
+ } else {
+ printf("\n");
+ (*menuTable[item].actionRoutine)(menuTable[item].arg);
+ }
+ }
+
+ /*
+ * Get the next choice, using any display options the user specified.
+ */
+ item = menuGetChoice (menuTable, numMenuItems, title, options);
+ if (item == QUIT)
+ return (NULL);
}
-
-} /* end menu () */
+}
/***************************************************************************
*
* menuGetChoice - Get the user's menu choice.
@@ -163,77 +156,63 @@ int item; /* User's menu item choice */
* RETURNS:
* The item number of the user's menu choice. (-1 if they chose QUIT)
*/
static int
-menuGetChoice (
- MENU_ITEM menuTable[],
+menuGetChoice (MENU_ITEM menuTable[],
int numMenuItems,
char *title,
unsigned long options
)
{
-/*char inputLine[MAX_INPUT_LINE_SIZE];*/
-
-int choice;
+ int choice;
/*
* Suppress display of the menu the first time if we're asked
*/
if (!(options & MENU_OPT_SUPPRESS_DISP))
- printMenu (menuTable, numMenuItems, title);
+ printMenu (menuTable, numMenuItems, title);
/*
* Prompt for a selection. Redisplay the menu and prompt again
* if there's an error in the selection.
*/
choice = -1;
- while (choice < 0 || choice > numMenuItems)
- {
-
- printf ("\nEnter the menu item number (0 to quit): ");
-
- choice = decIn ();
-
- if (choice < 0 || choice > numMenuItems)
-
- printMenu (menuTable, numMenuItems, title);
-
+ while (choice < 0 || choice > numMenuItems) {
+ printf ("\nEnter the menu item number (0 to quit): ");
+ choice = decIn ();
+ if (choice < 0 || choice > numMenuItems)
+ printMenu (menuTable, numMenuItems, title);
}
if (choice == 0)
-
- return (QUIT);
+ return (QUIT);
return (choice - 1);
-} /* end menuGetChoice () */
+}
/***************************************************************************
*
* printMenu - Print the menu
*
*
*/
static void
-printMenu (
- MENU_ITEM menuTable[],
+printMenu (MENU_ITEM menuTable[],
int numMenuItems,
char *title
)
{
int i;
-
printf("\n%s\n\n", title);
for (i = 0; i < numMenuItems; i++)
- {
- printf ("%2d - %s\n", i+1, menuTable[i].itemName);
- }
+ printf ("%2d - %s\n", i+1, menuTable[i].itemName);
printf(" 0 - quit");
-} /* end printMenu () */
+}
Index: hal/arm/xscale/iq80310/current/src/diag/test_menu.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/test_menu.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 test_menu.h
--- hal/arm/xscale/iq80310/current/src/diag/test_menu.h 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/test_menu.h 13 Nov 2002 15:41:09 -0000
@@ -103,15 +103,15 @@ For example:
* The following types define an entry in the menu table. Each entry describes
* one menu item, including a string to describe that item, an action
* routine to call when that item is chosen, and an argument to pass when the
* action routine is called.
*/
-typedef void (*MENU_RTN) ();
typedef volatile void *MENU_ARG;
+typedef void (*MENU_RTN) (MENU_ARG);
typedef struct menuItem
{
- char *itemName; /* string to print with the menu */
+ char *itemName; /* string to print with the menu */
MENU_RTN actionRoutine; /* routine to call when item is chosen */
MENU_ARG arg; /* argument to actionRoutine */
} MENU_ITEM;
Index: hal/arm/xscale/iq80310/current/src/diag/xscale_test.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/xscale_test.c,v
retrieving revision 1.1
diff -u -p -5 -r1.1 xscale_test.c
--- hal/arm/xscale/iq80310/current/src/diag/xscale_test.c 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/iq80310/current/src/diag/xscale_test.c 13 Nov 2002 15:41:10 -0000
@@ -47,401 +47,343 @@
//####DESCRIPTIONEND####
//
//===========================================================================*/
/************************************************************************/
-/* iq80310_test.c - Main diagnostics for IQ80310 board */
-/* */
-/* Modification History */
-/* -------------------- */
-/* 11oct00, ejb, Created for IQ80310 StrongARM2 */
+/* iq80310_test.c - Main diagnostics for IQ80310 board */
+/* */
+/* Modification History */
+/* -------------------- */
+/* 11oct00, ejb, Created for IQ80310 StrongARM2 */
/* 18dec00 jwf */
/* 02feb01 jwf added tests: _coy_tight_loop, cache_loop, LoopMemTest, */
-/* special_mem_test written by snc */
+/* special_mem_test written by snc */
/* 07feb01 jwf added function calls to a variable delay time generator */
/* 09feb01 jwf added function version_info to show version information */
/* about OS, BOARD, CPLD, 80200 ID, 80312 ID. */
/************************************************************************/
+#include <redboot.h>
+#include <cyg/io/pci_hw.h>
+#include <cyg/io/pci.h>
#include "7_segment_displays.h"
#include "test_menu.h"
#include "iq80310.h"
#include "pci_bios.h"
-extern void read_int_status();
-extern void _disableDCache();
-extern void _enableDCache();
-extern void _enableFiqIrq();
-extern void _usec_delay();
-extern void _msec_delay();
-extern void _enable_timer();
-extern void _disable_timer();
-extern long _read_timer();
-extern long _read_cpsr();
+extern void __disableDCache(void);
+extern void __enableDCache(void);
+extern void _enableFiqIrq(void);
+extern void _usec_delay(void);
+extern void _msec_delay(void);
+extern void _enable_timer(void);
+extern void _disable_timer(void);
+extern int xgetchar_timeout(char *ch, int msec);
+extern char xgetchar(void);
-/* 02/02/01 jwf */
-extern void _coy_tight_loop();
+/* 02/02/01 jwf */
extern long decIn(void);
extern long hexIn(void);
extern void hex32out(unsigned long num);
extern char* sgets(char *s);
-extern void flash_test(void) RAM_FUNC_SECT;
+extern void flash_test(MENU_ARG arg) RAM_FUNC_SECT;
extern STATUS pci_isr_connect (int intline, int bus, int device, int (*handler)(int), int arg);
extern STATUS pci_to_xint(int device, int intpin, int *xint);
-extern void timer_test (void);
+extern void timer_test (MENU_ARG arg);
-/* 02/07/01 jwf */
-extern void time_delay (UINT32 count, volatile int num_tmr_int);
+extern void delay_ms(int msecs);
extern int memTest (long startAddr, long endAddr);
/* 02/02/01 jwf */
extern int LoopMemTest (long startAddr, long endAddr);
-extern void uart_test(void);
+extern void uart_test(MENU_ARG arg);
extern void pci_ether_test (UINT32 busno, UINT32 devno, UINT32 funcno);
extern void config_ints(void); /* configure interrupts */
-extern void sys_pci_device_initialization (PCI_DATA* pci_data);
-extern STATUS sys_find_pci_device (int vendor_id, int device_id, int index, PCI_DEVICE_LOCATION *devloc);
extern int eeprom_write (unsigned long pci_base, int eeprom_addr, unsigned short *p_data, int nwords);
-extern ULONG sys_read_config_dword (UINT32 busno,UINT32 devno,UINT32 funcno,UINT32 offset,UINT32 *data);
extern int enable_external_interrupt (int int_id);
extern int disable_external_interrupt (int int_id);
extern int isr_connect(int int_num, void (*handler)(int), int arg);
extern int isr_disconnect(int int_num);
-extern void init_external_timer();
-extern void uninit_external_timer();
-extern int isHost();
+extern void init_external_timer(void);
+extern void uninit_external_timer(void);
+extern int isHost(void);
-void pci_int_test (void);
+void pci_int_test (MENU_ARG arg);
void hdwr_diag (void);
-void rotary_switch (void);
-void seven_segment_display (void);
-void backplane_detection(void);
-void battery_status(void);
-/* void timer_test (void); */
-void ether_test (void);
-void gpio_test (void);
+void rotary_switch (MENU_ARG arg);
+void seven_segment_display (MENU_ARG arg);
+void backplane_detection(MENU_ARG arg);
+void battery_status(MENU_ARG arg);
+void ether_test (MENU_ARG arg);
+void gpio_test (MENU_ARG arg);
/* 02/02/01 jwf */
-void static cache_loop (void);
+void static cache_loop (MENU_ARG arg);
/* 02/09/01 jwf */
-void version_info (void);
+void version_info (MENU_ARG arg);
void read_coyanosa_id_reg (void);
char board_revision (void);
-static void battery_test_menu (void);
-static void battery_test_write (void);
-static void battery_test_read (void);
+static void battery_test_menu (MENU_ARG arg);
+static void battery_test_write (MENU_ARG arg);
+static void battery_test_read (MENU_ARG arg);
/* 01/11/01 jwf */
void select_host_test_system (void);
-void internal_timer(void);
-static void enet_setup (void);
-static void memory_tests (void);
-static void repeat_mem_test (void);
+void internal_timer(MENU_ARG arg);
+static void enet_setup (MENU_ARG arg);
+static void memory_tests (MENU_ARG arg);
+static void repeat_mem_test (MENU_ARG arg);
/* 02/02/01 jwf */
-static void special_mem_test (void);
+static void special_mem_test (MENU_ARG arg);
-static void spci_tests (void), ppci_tests (void);
-STATUS Device_Seek(
- int verbose,
- unsigned long adapter_vendor,
- unsigned long adapter_device_id,
- unsigned long dev_index,
- PCI_DEVICE_LOCATION *dev_info
- );
+static void spci_tests (MENU_ARG arg), ppci_tests (MENU_ARG arg);
-#define VENDOR_INTEL 0x8086
-#define INTEL_NAME "Intel Corporation Inc."
+#define VENDOR_INTEL 0x8086
+#define INTEL_NAME "Intel Corporation Inc."
#define I80303_BRIDGE 0x0309
#define I80303_NAME0 "80303 PCI-PCI Bridge"
-#define I80303_ATU 0x5309
+#define I80303_ATU 0x5309
#define I80303_NAME1 "80303 Address Translation Unit"
-#define I82557 0x1229
-#define I82557_NAME "82557/82558/82559 10/100 LAN Controller"
+#define I82557 0x1229
+#define I82557_NAME "82557/82558/82559 10/100 LAN Controller"
-#define I82559ER 0x1209
+#define I82559ER 0x1209
#define I82559ER_NAME "82559ER 10/100 LAN Controller"
/* Test Menu Table */
-static MENU_ITEM testMenu[] =
-{
- {"Memory Tests", memory_tests, 0},
- {"Repeating Memory Tests", repeat_mem_test, 0},
- {"16C552 DUART Serial Port Tests", uart_test, 0},
- {"Rotary Switch S1 Test", rotary_switch, 0},
- {"7 Segment LED Tests", seven_segment_display,0},
- {"Backplane Detection Test", backplane_detection, 0},
- {"Battery Status Test", battery_status, 0},
- {"External Timer Test", timer_test, 0},
+static MENU_ITEM testMenu[] = {
+ {"Memory Tests", memory_tests, 0},
+ {"Repeating Memory Tests", repeat_mem_test, 0},
+ {"16C552 DUART Serial Port Tests", uart_test, 0},
+ {"Rotary Switch S1 Test", rotary_switch, 0},
+ {"7 Segment LED Tests", seven_segment_display,0},
+ {"Backplane Detection Test", backplane_detection, 0},
+ {"Battery Status Test", battery_status, 0},
+ {"External Timer Test", timer_test, 0},
#ifdef CYGPKG_IO_FLASH
- {"Flash Test", flash_test, 0},
+ {"Flash Test", flash_test, 0},
#endif
- {"i82559 Ethernet Configuration", enet_setup, 0},
- {"i82559 Ethernet Test", ether_test, 0},
- {"i960Rx/303 PCI Interrupt Test", pci_int_test, 0},
- {"Internal Timer Test", internal_timer, 0},
- {"Secondary PCI Bus Test", spci_tests, 0},
- {"Primary PCI Bus Test", ppci_tests, 0},
- {"Battery Backup SDRAM Memory Test", battery_test_menu, 0},
- {"GPIO Test", gpio_test, 0},
+ {"i82559 Ethernet Configuration", enet_setup, 0},
+ {"i82559 Ethernet Test", ether_test, 0},
+ {"i960Rx/303 PCI Interrupt Test", pci_int_test, 0},
+ {"Internal Timer Test", internal_timer, 0},
+ {"Secondary PCI Bus Test", spci_tests, 0},
+ {"Primary PCI Bus Test", ppci_tests, 0},
+ {"Battery Backup SDRAM Memory Test", battery_test_menu, 0},
+ {"GPIO Test", gpio_test, 0},
/* 02/02/01 jwf */
- {"Repeat-On-Fail Memory Test", special_mem_test, 0},
- {"Coyonosa Cache Loop (No return)", cache_loop, 0},
+ {"Repeat-On-Fail Memory Test", special_mem_test, 0},
+ {"Coyonosa Cache Loop (No return)", cache_loop, 0},
/* 02/09/01 jwf */
- {"Show Software and Hardware Revision", version_info, 0}
+ {"Show Software and Hardware Revision", version_info, 0}
};
#define NUM_MENU_ITEMS (sizeof (testMenu) / sizeof (testMenu[0]))
#define MENU_TITLE "\n IQ80310 Hardware Tests"
-
-PCI_DATA pci_devices = {0, 0};
extern void __reset(void);
void hdwr_diag (void)
{
-unsigned char* led0 = (unsigned char*)MSB_DISPLAY_REG;
-unsigned char* led1 = (unsigned char*)LSB_DISPLAY_REG;
+ unsigned char* led0 = (unsigned char*)MSB_DISPLAY_REG;
+ unsigned char* led1 = (unsigned char*)LSB_DISPLAY_REG;
- *led0 = LETTER_S;
- *led1 = LETTER_S;
+ *led0 = LETTER_S;
+ *led1 = LETTER_S;
- printf ("Entering Hardware Diagnostics - Disabling Data Cache!\n\n");
+ printf ("Entering Hardware Diagnostics - Disabling Data Cache!\n\n");
- __disableDCache();
+ __disableDCache();
- sys_pci_device_initialization (&pci_devices);
-
- _enableFiqIrq(); /* enable FIQ and IRQ interrupts */
+ _enableFiqIrq(); /* enable FIQ and IRQ interrupts */
- config_ints(); /* configure interrupts for diagnostics */
-
- init_external_timer();
+ config_ints(); /* configure interrupts for diagnostics */
- /* 01/11/01 jwf */
- select_host_test_system();
+ /* 01/11/01 jwf */
+ select_host_test_system();
- menu (testMenu, NUM_MENU_ITEMS, MENU_TITLE, MENU_OPT_NONE);
-
- printf ("Exiting Hardware Diagnostics - Reenabling Data Cache!\n\n");
-
- // _enableDCache(); /* reenable DCache */
+ menu (testMenu, NUM_MENU_ITEMS, MENU_TITLE, MENU_OPT_NONE);
- uninit_external_timer();
+ printf ("Exiting Hardware Diagnostics - Reenabling Data Cache!\n\n");
+ *led0 = ZERO;
+ *led1 = ZERO;
- *led0 = ZERO;
- *led1 = ZERO;
-
- __reset(); /* reset the board so RedBoot starts with a clean slate */
-}
-
-// Use "naked" attribute to suppress C prologue/epilogue
-static void __attribute__ ((naked)) _coy_tight_loop(void)
-{
- asm ( "0: mov r0,r0\n"
- "b 0b\n");
+ __reset(); /* reset the board so RedBoot starts with a clean slate */
}
-
/* 02/02/01 jwf */
-static void cache_loop (void)
+static void cache_loop (MENU_ARG arg)
{
- printf ("Putting Processor in a Tight Loop Forever...\n\n");
-
- _coy_tight_loop();
+ printf ("Putting Processor in a Tight Loop Forever...\n\n");
- /* not reached */
+ asm ( "0: mov r0,r0\n"
+ "b 0b\n");
+ /* not reached */
}
/************************************************/
-/* Secondary PCI Bus Test */
-/* */
+/* Secondary PCI Bus Test */
+/* */
/* This test assumes that a IQ80303 eval board */
/* is installed in a secondary PCI slot. This */
/* second board must be configured with 32 Meg */
-/* of SDRAM minimum. */
-/* */
+/* of SDRAM minimum. */
+/* */
/************************************************/
-static void spci_tests (void)
+static void spci_tests (MENU_ARG arg)
{
- long start_addr;
- long mem_size;
- long end_addr;
- int first_ctrlr = 0;
- PCI_DEVICE_LOCATION dev_loc;
-
- /* Look for ATU on the secondary PCI Bus */
- printf("\nLooking for a IQ80303 board on the Secondary PCI bus:\n");
- while (TRUE)
- {
- if (Device_Seek (FALSE, VENDOR_INTEL, I80303_ATU, first_ctrlr, &dev_loc) == OK)
- {
- if (dev_loc.bus_number != SECONDARY_BUS_NUM)
- {
- continue;
- }
- else
- {
- printf("An IQ80303 board has been detected on the Secondary PCI bus.");
- break;
- }
- }
- else
- {
- printf("No IQ80303 board detected on the SPCI bus!\n");
- return;
- }
+ long start_addr;
+ long mem_size;
+ long end_addr;
+ cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
+ int bus, devfn;
+
+ /* Look for ATU on the secondary PCI Bus */
+ printf("\nLooking for a IQ80303 board on the Secondary PCI bus:\n");
+ while (TRUE) {
+ if (cyg_pci_find_device(VENDOR_INTEL, I80303_ATU, &devid)) {
+ bus = CYG_PCI_DEV_GET_BUS(devid);
+ devfn = CYG_PCI_DEV_GET_DEVFN(devid);
+ if (bus != SECONDARY_BUS_NUM)
+ continue;
+ printf("An IQ80303 board has been detected: bus[%d] devive[%d] fn[%d].",
+ bus, CYG_PCI_DEV_GET_DEV(devfn), CYG_PCI_DEV_GET_FN(devfn));
+ break;
+ } else {
+ printf("No IQ80303 board detected on the SPCI bus!\n");
+ return;
}
+ }
- printf ("i80303 ATU located at bus = 0x%02X, dev = 0x%02X, func = 0x%02X\n",
- dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number);
-
- /* read the PCI address which corresponds to the start of DRAM */
- if (sys_read_config_dword (dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number, 0x10, (UINT32 *)&start_addr) == ERROR)
- {
- printf ("Error reading PCI BAR for ATU\n");
- return;
- }
+ /* read the PCI address which corresponds to the start of DRAM */
+ cyg_pci_read_config_uint32(devid, 0x10, (UINT32 *)&start_addr);
- /* strip off indicator bits */
- start_addr &= 0xfffffff0;
+ /* strip off indicator bits */
+ start_addr &= 0xfffffff0;
- printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);
+ printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);
- /* skip over 1st Mbyte of target DRAM */
- start_addr += 0x100000;
+ /* skip over 1st Mbyte of target DRAM */
+ start_addr += 0x100000;
- mem_size = 0x1f00000;
- end_addr = start_addr + mem_size;
+ mem_size = 0x1f00000;
+ end_addr = start_addr + mem_size;
- printf("\n\nTesting memory from $");
- hex32out(start_addr);
- printf(" to $");
- hex32out(end_addr);
- printf(".\n");
+ printf("\n\nTesting memory from $");
+ hex32out(start_addr);
+ printf(" to $");
+ hex32out(end_addr);
+ printf(".\n");
- memTest(start_addr, end_addr);
- printf("\n");
+ memTest(start_addr, end_addr);
+ printf("\n");
- printf ("\nMemory test done.\n");
- printf ("Press return to continue.\n");
- (void) hexIn();
+ printf ("\nMemory test done.\n");
+ printf ("Press return to continue.\n");
+ (void) hexIn();
}
/************************************************/
-/* Primary PCI Bus Test */
-/* */
+/* Primary PCI Bus Test */
+/* */
/* This test assumes that a IQ80303 eval board */
/* is installed in a primary PCI slot. This */
/* second board must be configured with 32 Meg */
-/* of SDRAM minimum. */
-/* */
+/* of SDRAM minimum. */
+/* */
/************************************************/
-static void ppci_tests (void)
+static void ppci_tests (MENU_ARG arg)
{
- long start_addr;
- long mem_size;
- long end_addr;
- int first_ctrlr = 0;
- PCI_DEVICE_LOCATION dev_loc;
-
- /* check to see if we are the host of the backplane, if not
- return an error */
- if (isHost() == FALSE)
- {
- printf ("Invalid test configuration, must be PCI host!\n");
- return;
- }
-
- /* Look for ATU on the primary PCI Bus */
- printf("\nLooking for a IQ80303 board on the Primary PCI bus:\n");
- while (TRUE)
- {
- if (Device_Seek (FALSE, VENDOR_INTEL, I80303_ATU, first_ctrlr, &dev_loc) == OK)
- {
- if (dev_loc.bus_number != PRIMARY_BUS_NUM)
- {
- continue;
- }
- else
- {
- printf("An IQ80303 board has been detected on the Primary PCI bus\n");
- break;
- }
- }
- else
- {
- printf("No IQ80303 board detected on the PPCI bus!\n");
- return;
- }
- }
+ long start_addr;
+ long mem_size;
+ long end_addr;
+ cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
+ int bus, devfn;
- printf ("i80303 ATU located at bus = 0x%02X, dev = 0x%02X, func = 0x%02X\n",
- dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number);
+ /* check to see if we are the host of the backplane, if not
+ return an error */
+ if (isHost() == FALSE) {
+ printf ("Invalid test configuration, must be PCI host!\n");
+ return;
+ }
- /* read the PCI address which corresponds to the start of DRAM */
- if (sys_read_config_dword (dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number, 0x10, (UINT32 *)&start_addr) == ERROR)
- {
- printf ("Error reading PCI BAR for ATU\n");
- return;
+ /* Look for ATU on the primary PCI Bus */
+ printf("\nLooking for a IQ80303 board on the Primary PCI bus:\n");
+ while (TRUE) {
+ if (cyg_pci_find_device(VENDOR_INTEL, I80303_ATU, &devid)) {
+ bus = CYG_PCI_DEV_GET_BUS(devid);
+ devfn = CYG_PCI_DEV_GET_DEVFN(devid);
+ if (bus != PRIMARY_BUS_NUM)
+ continue;
+ printf("An IQ80303 board has been detected: bus[%d] devive[%d] fn[%d].",
+ bus, CYG_PCI_DEV_GET_DEV(devfn), CYG_PCI_DEV_GET_FN(devfn));
+ break;
+ } else {
+ printf("No IQ80303 board detected on the PPCI bus!\n");
+ return;
}
+ }
+
+ /* read the PCI address which corresponds to the start of DRAM */
+ cyg_pci_read_config_uint32(devid, 0x10, (UINT32 *)&start_addr);
- /* strip off indicator bits */
- start_addr &= 0xfffffff0;
+ /* strip off indicator bits */
+ start_addr &= 0xfffffff0;
- printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);
+ printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);
- /* skip over 1st Mbyte of target DRAM */
- start_addr += 0x100000;
+ /* skip over 1st Mbyte of target DRAM */
+ start_addr += 0x100000;
- mem_size = 0x1f00000;
- end_addr = start_addr + mem_size;
+ mem_size = 0x1f00000;
+ end_addr = start_addr + mem_size;
- printf("\n\nTesting memory from $");
- hex32out(start_addr);
- printf(" to $");
- hex32out(end_addr);
- printf(".\n");
+ printf("\n\nTesting memory from $");
+ hex32out(start_addr);
+ printf(" to $");
+ hex32out(end_addr);
+ printf(".\n");
- memTest(start_addr, end_addr);
- printf("\n");
+ memTest(start_addr, end_addr);
+ printf("\n");
- printf ("\nMemory test done.\n");
- printf ("Press return to continue.\n");
- (void) hexIn();
+ printf ("\nMemory test done.\n");
+ printf ("Press return to continue.\n");
+ (void) hexIn();
}
/*****************************************************************************
* memory_tests - Basic Memory Tests
*
* Memory tests can be run one of two ways - with the cache turned OFF to test
* physical memory, or with cache turned ON to test the caching
*/
-static void memory_tests (void)
+static void memory_tests (MENU_ARG arg)
{
long start_addr;
long mem_size;
long end_addr;
- printf ("Base address of memory to test (in hex): ");
+ printf ("Base address of memory to test (in hex): ");
start_addr = hexIn();
printf("\n");
printf ("Size of memory to test (in hex): ");
mem_size = hexIn();
printf("\n");
@@ -463,18 +405,18 @@ static void memory_tests (void)
/*****************************************************************************
* repeat_mem_test - Repeating Memory Tests
*
*/
-static void repeat_mem_test (void)
+static void repeat_mem_test (MENU_ARG arg)
{
unsigned long start_addr, mem_size, end_addr;
- char cache_disable[10];
+ char cache_disable[10];
- printf ("Turn off Data Cache? (y/n): ");
- sgets (cache_disable);
- printf ("\n");
+ printf ("Turn off Data Cache? (y/n): ");
+ sgets (cache_disable);
+ printf ("\n");
printf ("Base address of memory to test (in hex): ");
start_addr = hexIn();
printf("\n");
printf ("Size of memory to test (in hex): ");
mem_size = hexIn();
@@ -493,17 +435,17 @@ static void repeat_mem_test (void)
* special_mem_test - Repeat-On-Fail Memory Test
*
* Memory tests can be run one of two ways - with the cache turned OFF to test
* physical memory, or with cache turned ON to test the caching
*/
-static void special_mem_test (void)
+static void special_mem_test (MENU_ARG arg)
{
long start_addr;
long mem_size;
long end_addr;
- printf ("Base address of memory to test (in hex): ");
+ printf ("Base address of memory to test (in hex): ");
start_addr = hexIn();
printf("\n");
printf ("Size of memory to test (in hex): ");
mem_size = hexIn();
printf("\n");
@@ -520,785 +462,410 @@ static void special_mem_test (void)
printf ("\nMemory test done.\n");
printf ("Press return to continue.\n");
(void) xgetchar();
}
+const unsigned char SevSegDecode[] = {
+ ZERO, ONE, TWO, THREE, FOUR,
+ FIVE, SIX, SEVEN, EIGHT, NINE,
+ LETTER_A, LETTER_B, LETTER_C, LETTER_D,
+ LETTER_E, LETTER_F, DECIMAL_POINT,
+ DISPLAY_OFF
+};
+
/* sequential test for LSD and MSD 7 segment Leds */
-void seven_segment_display (void)
+void seven_segment_display (MENU_ARG arg)
{
+ int DisplaySequence;
+ int SelectLed;
- unsigned char SevSegDecode;
- int DisplaySequence;
- int SelectLed;
-
-/* 02/07/01 jwf */
-/* const unsigned long TIME_OUT=6000000;*/
-/* 02/02/01 jwf */
-/* unsigned long Dwell;*/
-/* volatile unsigned long Dwell;*/
-
- *( unsigned char * ) 0xfe840000 = DISPLAY_OFF; /* blank MSD 7 segment LEDS */
-
- *( unsigned char * ) 0xfe850000 = DISPLAY_OFF; /* blank LSD 7 segment LEDS */
-
-
- SelectLed=0; /* initialize 7 segment LED selection */
-
- do
- {
- /* run test data sequence for a 7 segment LED */
- for (DisplaySequence = 0; DisplaySequence <= 17; ++DisplaySequence )
- {
- /* fetch 7 segment decode byte */
- switch( DisplaySequence )
- {
- case 0:
- SevSegDecode = ZERO;
- break;
-
- case 1:
- SevSegDecode = ONE;
- break;
-
- case 2:
- SevSegDecode = TWO;
- break;
-
- case 3:
- SevSegDecode = THREE;
- break;
-
- case 4:
- SevSegDecode = FOUR;
- break;
-
- case 5:
- SevSegDecode = FIVE;
- break;
-
- case 6:
- SevSegDecode = SIX;
- break;
-
- case 7:
- SevSegDecode = SEVEN;
- break;
-
- case 8:
- SevSegDecode = EIGHT;
- break;
-
- case 9:
- SevSegDecode = NINE;
- break;
-
- case 10:
- SevSegDecode = LETTER_A;
- break;
-
- case 11:
- SevSegDecode = LETTER_B;
- break;
-
- case 12:
- SevSegDecode = LETTER_C;
- break;
-
- case 13:
- SevSegDecode = LETTER_D;
- break;
-
- case 14:
- SevSegDecode = LETTER_E;
- break;
-
- case 15:
- SevSegDecode = LETTER_F;
- break;
-
- case 16:
- SevSegDecode = DECIMAL_POINT;
- break;
-
- case 17:
- SevSegDecode = DISPLAY_OFF;
-
- default:
- break;
+ *MSB_DISPLAY_REG = DISPLAY_OFF; /* blank MSD 7 segment LEDS */
+ *LSB_DISPLAY_REG = DISPLAY_OFF; /* blank LSD 7 segment LEDS */
- } /* end switch( DisplaySequence ) */
+ SelectLed=0; /* initialize 7 segment LED selection */
+ do {
+ /* run test data sequence for a 7 segment LED */
+ for (DisplaySequence = 0; DisplaySequence <= 17; ++DisplaySequence) {
- /* display test data on selected 7 segment LED */
- /* the test data sequence for a 7 segment led will be seen as:*/
- /* 0 1 2 3 4 5 6 7 8 9 A b C d e F . */
- switch( SelectLed )
- {
- case 0:
- *( unsigned char * ) 0xfe850000 = SevSegDecode; /* write value on 7 segment LSD LED display */;
- break;
-
- case 1:
- *( unsigned char * ) 0xfe840000 = SevSegDecode; /* write value on 7 segment MSD LED display */;
- break;
-
- default:
- break;
- } /* end switch( SelectLed ) */
-
-/* 02/07/01 jwf */
- /* time delay, allows user enough time to read a value on display */
-/* for (Dwell=TIME_OUT; Dwell > 0; --Dwell );*/
- time_delay (0x325aa0, 4);/* Delay 0.4 second. Load counter with a 100ms count down (3300000)d per timer interrupt, 5 timer interrupts */
-
- } /* end for(DisplaySequence~) */
-
- ++SelectLed; /* select next 7 segment LED */
- }
- while (SelectLed < 2); /* tests a pair of 7 segment LEDs */
+ /* display test data on selected 7 segment LED */
+ /* the test data sequence for a 7 segment led will be seen as:*/
+ /* 0 1 2 3 4 5 6 7 8 9 A b C d e F . */
+ if (SelectLed)
+ *MSB_DISPLAY_REG = SevSegDecode[DisplaySequence];
+ else
+ *LSB_DISPLAY_REG = SevSegDecode[DisplaySequence];
+
+ delay_ms(400);
+
+ } /* end for(DisplaySequence~) */
+ ++SelectLed; /* select next 7 segment LED */
+ } while (SelectLed < 2); /* tests a pair of 7 segment LEDs */
- *( unsigned char * ) 0xfe840000 = LETTER_S; /* show S on the 7 segment MSD LED */
- *( unsigned char * ) 0xfe850000 = LETTER_S; /* show S on the 7 segment LSD LED */
-} /* end seven_segment_display() */
+ *MSB_DISPLAY_REG = LETTER_S;
+ *LSB_DISPLAY_REG = LETTER_S;
+}
/* 12/18/00 jwf */
/* tests rotary switch status, S1 positions 0-3, a 2 bit output code */
-void rotary_switch (void)
+void rotary_switch (MENU_ARG arg)
{
+ const unsigned char MAX_SWITCH_SAMPLES = 9;
+ unsigned char RotarySwitch[MAX_SWITCH_SAMPLES];
+ unsigned char index; /* index for Rotary Switch array */
+ unsigned char debounce; /* keeps tally of equal rotary switch data reads in a loop */
+ char ch;
+
+ *MSB_DISPLAY_REG = DISPLAY_OFF;
+ *MSB_DISPLAY_REG = DISPLAY_OFF;
+
+ printf("\n\nThe 7-Segment LSD LED shows the Rotary Switch position selected, i.e., 0-F.");
+ printf("\n\nSlowly dial the Rotary Switch through each position 0-F and confirm reading.");
+
+ printf( "\n\nStrike <CR> to exit this test." );
+ do {
+ do { /* debounce the switch contacts */
+ for (index = 0; index <= MAX_SWITCH_SAMPLES; index++) {
+ /* read rotary switch code */
+ RotarySwitch[index] = *(volatile unsigned char *)0xfe8d0000;
+ RotarySwitch[index] &= 0x0f;
+ }
+ debounce = 0;
+ for (index = 1; index <= MAX_SWITCH_SAMPLES; index++)
+ if (RotarySwitch[0] == RotarySwitch[index])
+ debounce++;
+
+ /* exit when all rotary switch code readings are equal,
+ when debounce = MAX_SWITCH_SAMPLES-1 */
+ } while (debounce < (MAX_SWITCH_SAMPLES - 1));
- /* CYGMON serial port J9 */
- unsigned char recv_data; /* RHR */
- unsigned char recv_lsr; /* LSR */
-
- const unsigned char MAX_SWITCH_SAMPLES = 9;
- unsigned char RotarySwitch[MAX_SWITCH_SAMPLES]; /* holds multiple samples of a 4 bit switch code */
- unsigned char index; /* index for Rotary Switch array */
- unsigned char debounce; /* keeps tally of equal rotary switch data reads in a loop */
- unsigned char SevSegDecode; /* holds decode data for a 7 segment LED display */
-
- char board_rev; /* holds a Board Revision number */
-
-/* 02/07/01 jwf */
-/* const unsigned long TIME_OUT = 4000000;*/
-/* 02/02/01 jwf */
-/* volatile unsigned int Dwell;*/
-
- *( unsigned char * ) 0xfe840000 = DISPLAY_OFF; /* turn off the 7 segment MSD LED */
- *( unsigned char * ) 0xfe850000 = DISPLAY_OFF; /* turn off the 7 segment LSD LED */
-
- board_rev= board_revision (); /* Determine Board Revision Number */
- if (board_rev >= BOARD_REV_E) /* Board Rev is at E or higher */
- {
- printf("\n\nThe 7-Segment LSD LED shows the Rotary Switch position selected, i.e., 0-F.");
- printf("\n\nSlowly dial the Rotary Switch through each position 0-F and confirm reading.");
- }
- else /* Unknown Board Revision, might be D or B or A. */
- {
- printf("\n\nThe 7-Segment LSD LED shows the Rotary Switch position selected, i.e., 0-3.");
- printf("\n\nSlowly dial the Rotary Switch through each position 0-3 and confirm reading.");
- }
+ /* display the rotary switch position on the 7 segment LSD LED as: 0, 1, 2, 3 */
+ *LSB_DISPLAY_REG = SevSegDecode[RotarySwitch[0]];
- printf( "\n\nStrike <CR> to exit this test." );
- while ( recv_data != 0x0d ) /* run until User types a <CR> to exit */
- {
-
- do /* debounce the switch contacts */
- {
- for(index = 0; index <= MAX_SWITCH_SAMPLES; index++) /* sample rotary switch code */
- {
- RotarySwitch[index] = *( unsigned char * ) 0xfe8d0000; /* read rotary switch code */
- RotarySwitch[index] &= 0x0f; /* mask out bits b7-b4, preserve bits b0-b3 */
- }
- debounce = 0;
- for(index = 1; index <= MAX_SWITCH_SAMPLES; index++) /* test rotary switch code samples */
- {
- if (RotarySwitch[0] == RotarySwitch[index])
- debounce++; /* keep tally of equal rotary switch code samples */
- }
- }
- while ( debounce < (MAX_SWITCH_SAMPLES - 1) ); /* exit when all rotary switch code readings are equal, when debounce = MAX_SWITCH_SAMPLES-1 */
-
- /* decipher state of rotary switch position */
- switch( RotarySwitch[0] )
- /* examine rotary switch position then display its position number on the 7 segment LSD LED */
- {
- case 0x00:
- SevSegDecode = ZERO;
- break;
-
- case 0x01:
- SevSegDecode = ONE;
- break;
-
- case 0x02:
- SevSegDecode = TWO;
- break;
-
- case 0x03:
- SevSegDecode = THREE;
- break;
-
- case 0x4:
- SevSegDecode = FOUR;
- break;
-
- case 0x5:
- SevSegDecode = FIVE;
- break;
-
- case 0x6:
- SevSegDecode = SIX;
- break;
-
- case 0x7:
- SevSegDecode = SEVEN;
- break;
-
- case 0x8:
- SevSegDecode = EIGHT;
- break;
-
- case 0x9:
- SevSegDecode = NINE;
- break;
-
- case 0xa:
- SevSegDecode = LETTER_A;
- break;
-
- case 0xb:
- SevSegDecode = LETTER_B;
- break;
-
- case 0xc:
- SevSegDecode = LETTER_C;
- break;
-
- case 0xd:
- SevSegDecode = LETTER_D;
- break;
-
- case 0xe:
- SevSegDecode = LETTER_E;
- break;
-
- case 0xf:
- SevSegDecode = LETTER_F;
- break;
-
- default:
- SevSegDecode = DECIMAL_POINT;
- break;
- }
-
- *( unsigned char * ) 0xfe850000 = SevSegDecode; /* display the rotary switch position on the 7 segment LSD LED as: 0, 1, 2, 3 */
-
- recv_lsr = *(volatile unsigned char *) 0xfe810005; /* read J9 serial port LSR */
- recv_lsr &= 0x1;
- if ( recv_lsr == 0x1) /* a character is ready in receiver buffer */
- {
- recv_data = *(volatile unsigned char *) 0xfe810000; /* read character from J9 serial port receiver buffer */
- }
-/* 02/07/01 jwf */
-/* for (Dwell=TIME_OUT; Dwell > 0; --Dwell );*/
- time_delay (0x325aa0, 2);/* Delay 0.2 second. Load counter with a 100ms count down (3300000)d per timer interrupt, 2 timer interrupts */
- }
+ } while (!xgetchar_timeout(&ch, 200) || ch != 0x0d); /* run until User types a <CR> to exit */
- *( unsigned char * ) 0xfe840000 = LETTER_S; /* show S on the 7 segment MSD LED */
- *( unsigned char * ) 0xfe850000 = LETTER_S; /* show S on the 7 segment LSD LED */
+ *MSB_DISPLAY_REG = LETTER_S;
+ *LSB_DISPLAY_REG = LETTER_S;
-} /* end rotary_switch() */
+}
/* test backplane detection, connector socket J19 pin 7 */
/* BP_DET#=0, no backplane */
/* BP_DET#=1, backplane installed */
/* b0 <--> BP_DET# */
-void backplane_detection(void)
+void backplane_detection(MENU_ARG arg)
{
- unsigned char BpDetStatus; /* L = pci700 board installed on backplane */
+ unsigned char BpDetStatus; /* L = pci700 board installed on backplane */
- BpDetStatus = *( unsigned char * ) 0xfe870000; /* read backplane detection status port */
+ BpDetStatus = *( unsigned char * ) 0xfe870000; /* read backplane detection status port */
- BpDetStatus &= 0x01; /* isolate bit b0 */
+ BpDetStatus &= 0x01; /* isolate bit b0 */
- /* examine bit 0 */
- switch( BpDetStatus )
+ /* examine bit 0 */
+ switch( BpDetStatus ) {
+ case 0x00: /* BpDetStatus = !(BP_DET#=1) = 0 */
+ printf("\nBackplane detection bit read Low, no backplane installed\n");
+ printf("\nPlace a jumper across J19.7 to J19.1, then run this test again.\n");
+ break;
- {
- case 0x00: /* BpDetStatus = !(BP_DET#=1) = 0 */
- printf("\nBackplane detection bit read Low, no backplane installed\n");
- printf("\nPlace a jumper across J19.7 to J19.1, then run this test again.\n");
- break;
+ case 0x01: /* BpDetStatus = !(BP_DET#=0) = 1 */
+ printf("\nBackplane detection bit read High, 1 backplane detected.\n");
+ printf("\nRemove jumper from J19\n");
+ break;
- case 0x01: /* BpDetStatus = !(BP_DET#=0) = 1 */
- printf("\nBackplane detection bit read High, 1 backplane detected.\n");
- printf("\nRemove jumper from J19\n");
- break;
-
- default:
- break;
- }
-
-/* 12/18/00 jwf */
- printf ("\n\nStrike <CR> to exit this test.\n\n");
- hexIn();
+ default:
+ break;
+ }
+ /* 12/18/00 jwf */
+ printf ("\n\nStrike <CR> to exit this test.\n\n");
+ hexIn();
}
/* test battery status */
/* b0 - !(BATT_PRES#=0). A battery is installed.*/
/* b1 - BATT_CHRG=1. The battery is fully charged. */
/* b2 - BATT_DISCHRG=1. The battery is fully discharged. */
-void battery_status(void)
+void battery_status(MENU_ARG arg)
{
- unsigned char BatteryStatus;
-
- unsigned char TestBit;
-
- BatteryStatus = *( unsigned char * ) 0xfe8f0000; /* read battery status port */
-
- BatteryStatus &= 0x07; /* isolate bits b0, b1, and b2 */
-
- TestBit = BatteryStatus;
-
- /* examine bit b0 BATT_PRES# */
-
- TestBit &= 0x01;
-
- if (TestBit == 0x01) /* TestBit=!(BATT_PRES#=0)=1 */
- {
-
- printf("\nBATT_PRES#=0. A battery was detected.\n");
- }
-
- else /* TestBit=!(BATT_PRES#=1)=0 */
- {
-
- printf("\nBATT_PRES#=1. No battery installed.\n"); /* skip testing bits b2 and b3 (BATT_CHRG and BATT_DISCHRG) here since no battery is installed yet */
- }
-
- /* examine bit b1 BATT_CHRG */
- TestBit |= BatteryStatus;
-
- TestBit &= 0x02;
-
- if (TestBit == 0x02) /* BATT_CHRG=1 */ /* Assume V_BATT float=4.2V, then 1.2V<V(U20.5)<=1.33V so V_BATT>3.78V,*/
-
- printf("\nBATT_CHRG=1. Battery is fully charged.\n");
+ unsigned char BatteryStatus;
- else /* BATT_CHRG=0 */ /* Assume V_BATT float=4.2V, then V(U20.5)<=1.2V so V_BATT<=3.78V */
+ BatteryStatus = *(unsigned char *)0xfe8f0000; /* read battery status port */
- printf("\nBATT_CHRG=0. Battery is charging.\n");
-
-
- /* examine bit b2 BATT_DISCHRG */
- TestBit |= BatteryStatus;
-
- TestBit &= 0x04;
-
-
- if (TestBit == 0x04) /* BATT_DISCHRG=1 */ /* Assume V_BATT float=4.2V, then V(U30.2)=<1.2V so V_BATT<=3.0V */
-
- printf("\nBATT_DISCHRG=1. Battery is fully discharged.\n");
-
- else /* BATT_DISCHRG=0 */ /* Assume V_BATT float=4.2V, then 1.2V<V(U30.2)=<1.68V so V_BATT>3.0V */
-
- printf("\nBATT_DISCHRG=0. Battery voltage measures with in normal operating range.\n");
+ /* examine bit b0 BATT_PRES# */
+ if (BatteryStatus & 0x01) /* TestBit=!(BATT_PRES#=0)=1 */
+ printf("\nBATT_PRES#=0. A battery was detected.\n");
+ else
+ printf("\nBATT_PRES#=1. No battery installed.\n");
- printf ("\n\nStrike <CR> to exit this test.\n\n");
-
- hexIn();
+ /* examine bit b1 BATT_CHRG */
+ if (BatteryStatus & 0x02) /* BATT_CHRG=1 */
+ printf("\nBATT_CHRG=1. Battery is fully charged.\n");
+ else /* BATT_CHRG=0 */
+ printf("\nBATT_CHRG=0. Battery is charging.\n");
+
+ /* examine bit b2 BATT_DISCHRG */
+ if (BatteryStatus & 0x04)
+ printf("\nBATT_DISCHRG=1. Battery is fully discharged.\n");
+ else
+ printf("\nBATT_DISCHRG=0. Battery voltage measures with in normal operating range.\n");
+ printf ("\n\nStrike <CR> to exit this test.\n\n");
+ hexIn();
}
-
-
-
/* GPIO test */
/* Header J16 pin out is: J16.1=b0, J16.3=b1, J16.5=b2, J16.7=b3, J16.9=b4, J16.11=b5, J16.13=b6, J16.15=b7 */
/* This test will require use of 2 special test sockets wired as follows for the output and input tests. */
/* Intel specifies that each GPIO pin must be pulled down after P_RST# deasserts to swamp out their weak internal active pull up */
/* Note that the internal weak active pull up tends to have more of an affect on the GPIO input port rather than the output port */
/* Therefore for the input test, jumper J16 pins: 1-2, 3-4, 5-6, 7-8, 9-10, 11-12, 13-14, 15-16, and (TBD) provide an input source for each bit */
/* For the output test, jumper J16 pins: 1-2, 3-4, 5-6, 7-8, 9-10, 11-12, 13-14, 15-16 */
/* each jumpered pin connects a weak pull down resistor, resident on board, to each GPIO pin */
-void gpio_test (void)
+void gpio_test (MENU_ARG arg)
{
- /*unsigned char GpioInputPort;*/
- unsigned char GpioOutputPort;
- unsigned char GpioOutputEnablePort;
-
- /* GPIO output port test */
-
- printf("\n\nPlug output test socket into header J16, strike 'Enter' to continue" );
- while(xgetchar()!=0x0d);
-
- /* write test data pattern to GPIO Output Enable Register at address 0x0000171c */
- *( unsigned char * ) 0x0000171c = 0x55;
+ /*unsigned char GpioInputPort;*/
+ unsigned char GpioOutputPort;
+ unsigned char GpioOutputEnablePort;
- /* read GPIO Output Enable Register from address 0x0000171c */
- GpioOutputEnablePort = *( unsigned char * ) 0x0000171c;
+ /* GPIO output port test */
- if (GpioOutputEnablePort==0x55)
- printf("\nGPIO Output Enable first write/read test PASSED.");
- else
- printf("\nGPIO Output Enable first write/read test FAILED.");
+ printf("\n\nPlug output test socket into header J16, strike 'Enter' to continue" );
+ while(xgetchar()!=0x0d);
-/*
- printf("\n\nStrike Enter to continue" );
- printf("\n0x55" );
- while(xgetchar()!=0x0d);
-*/
-
- /* write test data pattern to GPIO Output Enable Register at address 0x0000171c */
- *( unsigned char * ) 0x0000171c = 0xaa;
+ /* write test data pattern to GPIO Output Enable Register at address 0x0000171c */
+ *( unsigned char * ) 0x0000171c = 0x55;
- /* read GPIO Output Enable Register from address 0x0000171c */
- GpioOutputEnablePort = *( unsigned char * ) 0x0000171c;
+ /* read GPIO Output Enable Register from address 0x0000171c */
+ GpioOutputEnablePort = *( unsigned char * ) 0x0000171c;
- if (GpioOutputEnablePort==0xaa)
- printf("\nGPIO Output Enable second write/read test PASSED.");
- else
- printf("\nGPIO Output Enable second write/read test FAILED.");
+ if (GpioOutputEnablePort==0x55)
+ printf("\nGPIO Output Enable first write/read test PASSED.");
+ else
+ printf("\nGPIO Output Enable first write/read test FAILED.");
+ /* write test data pattern to GPIO Output Enable Register at address 0x0000171c */
+ *( unsigned char * ) 0x0000171c = 0xaa;
-
- /* enable output bits b0-b7, write test pattern to GPIO Output Enable Register at address 0x0000171c */
- *( unsigned char * ) 0x0000171c = 0x00;
-
- /* write test data pattern to GPIO Output Data Register at address 00001724h */
- *( unsigned char * ) 0x00001724 = 0x55;
-
- /* read test data pattern from GPIO Output Data Register at address 00001724h */
- GpioOutputPort = *( unsigned char * ) 0x00001724;
+ /* read GPIO Output Enable Register from address 0x0000171c */
+ GpioOutputEnablePort = *( unsigned char * ) 0x0000171c;
- if (GpioOutputPort==0x55)
- printf("\nGPIO Output Data Register first write/read test PASSED.");
- else
- printf("\nGPIO Output Data Register first write/read test FAILED.");
+ if (GpioOutputEnablePort==0xaa)
+ printf("\nGPIO Output Enable second write/read test PASSED.");
+ else
+ printf("\nGPIO Output Enable second write/read test FAILED.");
-/*
- printf("\n\nStrike Enter to continue" );
- printf("\n0x55" );
- while(xgetchar()!=0x0d);
-*/
+ /* enable output bits b0-b7, write test pattern to GPIO Output Enable Register */
+ *( unsigned char * ) 0x0000171c = 0x00;
- /* write output data pattern to GPIO Output Data Register at address 00001724h */
- *( unsigned char * ) 0x00001724 = 0xaa;
+ /* write test data pattern to GPIO Output Data Register at address 00001724h */
+ *( unsigned char * ) 0x00001724 = 0x55;
- /* read output data pattern from GPIO Output Data Register at address 00001724h */
- GpioOutputPort = *( unsigned char * ) 0x00001724;
+ /* read test data pattern from GPIO Output Data Register at address 00001724h */
+ GpioOutputPort = *( unsigned char * ) 0x00001724;
- if (GpioOutputPort==0xaa)
- printf("\nGPIO Output Data Register second write/read test PASSED.");
- else
- printf("\nGPIO Output Data Register second write/read test FAILED.");
-
-
- printf("\n\nRemove output test socket from header J16, strike 'Enter' to continue" );
- while(xgetchar()!=0x0d);
-
-
-
- /* GPIO input port test */
-/*
- printf("\n\nPlug input test socket into header J16, strike 'Enter' to continue" );
- while(xgetchar()!=0x0d);
-*/
-
- /* GPIO Input Data Register address is 00001720h */ /* read port */
-/*
- GpioInputPort = *( unsigned char * ) 0x00001720;
- if ( GpioInputPort==0x55 )
- printf("\nGPIO Input Data Register first read test PASSED");
- else
- printf("\nGPIO Input Data Register first read test FAILED");
-*/
+ if (GpioOutputPort==0x55)
+ printf("\nGPIO Output Data Register first write/read test PASSED.");
+ else
+ printf("\nGPIO Output Data Register first write/read test FAILED.");
+ /* write output data pattern to GPIO Output Data Register at address 00001724h */
+ *( unsigned char * ) 0x00001724 = 0xaa;
- /* GPIO Input Data Register address is 00001720h */ /* read port */
-/*
- GpioInputPort = *( unsigned char * ) 0x00001720;
-
- if ( GpioInputPort==0xaa )
- printf("\nGPIO Input Data Register second read test PASSED");
- else
- printf("\nGPIO Input Data Register second read test FAILED");
-*/
-/*
- printf("\n\nRemove input test socket from header J16, strike 'Enter' to continue" );
- while(xgetchar()!=0x0d);
-*/
-
-} /* end gpio_test() */
+ /* read output data pattern from GPIO Output Data Register at address 00001724h */
+ GpioOutputPort = *( unsigned char * ) 0x00001724;
-
-
-/*************************************************************************
-* Device_Seek - look for a PCI device
-*
-* During initialization, a device driver must call this function
-* (or a similar one) with the specific PCI Vendor Id and Device Id
-* of the device to be supported to determine its location (or lack
-* thereof) on the PCI bus. If multiple devices are to be supported,
-* this function must be called repeatedly with an increasing dev_index
-* until the function returns ERROR. Each instance (if any) of the device
-* will then have been identified.
-*
-* Once the device is located, the device driver can then call the
-* appropriate PCI BIOS function to read device information from PCI
-* Configuration Space (i.e. Runtime Register PCI Base address, Local
-* Memory PCI Base address, etc.)
-*
-*/
-STATUS Device_Seek(
- int verbose,
- unsigned long adapter_vendor,
- unsigned long adapter_device_id,
- unsigned long dev_index,
- PCI_DEVICE_LOCATION *dev_info
- )
-{
- if (verbose)
- {
- printf("Looking for Adapter on PCI Bus with:\n");
- printf("Vendor Id = 0x%04x\n",adapter_vendor);
- printf("Device Id = 0x%04x\n",adapter_device_id);
- printf("Index = %x\n",dev_index);
- }
-
- if (sys_find_pci_device (adapter_vendor,
- adapter_device_id,
- dev_index, dev_info) != OK)
- {
- if (verbose) printf("Failed to Find Adapter\n");
- return (ERROR);
- }
+ if (GpioOutputPort==0xaa)
+ printf("\nGPIO Output Data Register second write/read test PASSED.");
else
- {
- if (verbose)
- {
- printf("Adapter found at :\n");
- printf(" PCI Bus Number : %d\n", dev_info->bus_number);
- printf(" Device Number : %d\n", dev_info->device_number);
- }
- return (OK);
- }
+ printf("\nGPIO Output Data Register second write/read test FAILED.");
+
+ printf("\n\nRemove output test socket from header J16, strike 'Enter' to continue" );
+ while(xgetchar()!=0x0d);
}
-
/* i82559 Ethernet test */
-void ether_test (void)
+void ether_test (MENU_ARG arg)
{
-
- PCI_DEVICE_LOCATION dev_loc[6]; /* 6 is the max Enet for now */
- int unit = 0;
- int i, num_enet;
+ cyg_pci_device_id devid[6];
+ int unit = 0;
+ int i, num_enet;
- for (i = 0, num_enet = 0; i < 6; i++, num_enet++)
- {
- if (Device_Seek (FALSE, VENDOR_INTEL,
- I82557,
- i,
- &(dev_loc[num_enet])) != OK)
- {
- break;
- }
-
- }
-
- for (i = 0; i < 6; i++, num_enet++)
- {
- if (Device_Seek (FALSE, VENDOR_INTEL,
- I82559ER,
- i,
- &(dev_loc[num_enet])) != OK)
- {
- break;
- }
+ for (i = 0, num_enet = 0; i < 6; i++, num_enet++) {
+ if (i == 0)
+ devid[0] = CYG_PCI_NULL_DEVID;
+ else
+ devid[i] = devid[i-1]; // start from last one found
+ if (!cyg_pci_find_device(VENDOR_INTEL, I82557, &devid[i]))
+ break;
+ }
- }
+ for (; i < 6; i++, num_enet++) {
+ if (i == 0)
+ devid[0] = CYG_PCI_NULL_DEVID;
+ else
+ devid[i] = devid[i-1]; // start from last one found
+ if (!cyg_pci_find_device(VENDOR_INTEL, I82559ER, &devid[i]))
+ break;
+ }
- if (num_enet == 0)
- {
- printf ("No supported Ethernet devices found\n");
- return;
- }
+ if (num_enet == 0) {
+ printf ("No supported Ethernet devices found\n");
+ return;
+ }
- printf ("Supported Ethernet Devices:\n\n");
-
- printf (" Unit# Bus# Device#\n");
- printf (" ----- ---- -------\n");
- for (i = 0; i < num_enet; i++)
- {
- printf (" %d %d %d\n", i, dev_loc[i].bus_number, dev_loc[i].device_number);
- }
-
- printf ("\nEnter the unit number to test : ");
- unit = decIn();
- printf ("\n");
-
- pci_ether_test (dev_loc[unit].bus_number,
- dev_loc[unit].device_number,
- dev_loc[unit].function_number);
+ printf ("Supported Ethernet Devices:\n\n");
+ printf (" Unit# Bus# Device#\n");
+ printf (" ----- ---- -------\n");
+ for (i = 0; i < num_enet; i++)
+ printf (" %d %d %d\n", i,
+ CYG_PCI_DEV_GET_BUS(devid[i]),
+ CYG_PCI_DEV_GET_DEV(CYG_PCI_DEV_GET_DEVFN(devid[i])));
+
+ printf ("\nEnter the unit number to test : ");
+ unit = decIn();
+ printf ("\n");
+
+ pci_ether_test (CYG_PCI_DEV_GET_BUS(devid[unit]),
+ CYG_PCI_DEV_GET_DEV(CYG_PCI_DEV_GET_DEVFN(devid[unit])),
+ CYG_PCI_DEV_GET_FN(CYG_PCI_DEV_GET_DEVFN(devid[unit])));
}
/* Setup Serial EEPROM for Ethernet Configuration */
-static void enet_setup (void)
+static void enet_setup (MENU_ARG arg)
{
- UINT32 adapter_ptr; /* Ptr to PCI Ethernet adapter */
+ UINT32 adapter_ptr; /* Ptr to PCI Ethernet adapter */
+ cyg_pci_device_id devid;
- PCI_DEVICE_LOCATION dev_loc;
- UINT16 eepromData[3] =
- {
+ UINT16 eepromData[3] = {
0x4801, /* Valid EEPROM, No Expansion ROM, Rev = ?, PHY Addr = 1 */
0x0700, /* Subsystem Id - PCI700 */
0x113c /* Subsystem Vendor Id - Cyclone Microsystems */
- };
- int config_data_offset = 0x0a; /* offset into EEPROM for config. data storage */
- int ia_offset = 0x00; /* offset into EEPROM for IA storage */
- UINT8 buffer[6]; /* temporary storage for IA */
+ };
+ int config_data_offset = 0x0a; /* offset into EEPROM for config. data storage */
+ int ia_offset = 0x00; /* offset into EEPROM for IA storage */
+ UINT8 buffer[6]; /* temporary storage for IA */
UINT16 temp_node_addr[3] = {0,0,0};
UINT16 serial_no;
UINT8 revision_id = 0, port_id = 0;
- char rev_string[8];
+ char rev_string[8];
/* Cyclone identifier */
buffer[0] = 0x00;
buffer[1] = 0x80;
buffer[2] = 0x4D;
- buffer[3] = 0x46; /* board identifier - PCI700 = 70 = 0x46 */
+ buffer[3] = 0x46; /* board identifier - PCI700 = 70 = 0x46 */
- serial_no = 10000;
- while (serial_no >= 10000)
- {
- printf ("\nEnter the board serial number (1 - 9999): ");
- serial_no = decIn();
- printf ("\n");
- }
- revision_id = 8;
- while ((revision_id < 1) || (revision_id > 7))
- {
- printf ("\nEnter the board revison (A - G) : ");
- sgets (rev_string);
- rev_string[0] = (rev_string[0] & 0xdf); /* convert to upper case */
- revision_id = (rev_string[0] - 'A') + 1; /* convert to a number 1 - 7 */
- printf ("\n");
- }
- revision_id &= 0x7;
- eepromData[0] |= (revision_id << 8); /* add the rev. id to data */
-
- /* we only want to set up on-board 559 */
- dev_loc.bus_number = 2;
- dev_loc.device_number = 0;
- dev_loc.function_number = 0;
+ serial_no = 10000;
+ while (serial_no >= 10000) {
+ printf ("\nEnter the board serial number (1 - 9999): ");
+ serial_no = decIn();
+ printf ("\n");
+ }
+ revision_id = 8;
+ while ((revision_id < 1) || (revision_id > 7)) {
+ printf ("\nEnter the board revison (A - G) : ");
+ sgets (rev_string);
+ rev_string[0] = (rev_string[0] & 0xdf); /* convert to upper case */
+ revision_id = (rev_string[0] - 'A') + 1; /* convert to a number 1 - 7 */
+ printf ("\n");
+ }
+ revision_id &= 0x7;
+ eepromData[0] |= (revision_id << 8); /* add the rev. id to data */
- /* Get the PCI Base Address for mem. runtime registers */
- if (sys_read_config_dword (dev_loc.bus_number,
- dev_loc.device_number,
- dev_loc.function_number,
- 0x10, &adapter_ptr) == ERROR)
- {
- printf("Unable to read i82559 PCI Base Address\n");
- return;
- }
-
- /* strip off indicator bits */
- adapter_ptr = adapter_ptr & 0xfffffff0;
-
- printf ("Writing the Configuration Data to the Serial EEPROM... ");
- if (eeprom_write (adapter_ptr,config_data_offset,eepromData,3) != OK)
- {
- printf ("Error writing the Configuration Data to Serial EEPROM\n");
- return;
- }
- printf ("Done\n");
+ /* we only want to set up on-board 559 */
+ devid = CYG_PCI_DEV_MAKE_ID(2, CYG_PCI_DEV_MAKE_DEVFN(0,0));
+ /* Get the PCI Base Address for mem. runtime registers */
+ cyg_pci_read_config_uint32(devid, 0x10, &adapter_ptr);
+
+ /* strip off indicator bits */
+ adapter_ptr = adapter_ptr & 0xfffffff0;
+
+ printf ("Writing the Configuration Data to the Serial EEPROM... ");
+ if (eeprom_write (adapter_ptr,config_data_offset,eepromData,3) != OK) {
+ printf ("Error writing the Configuration Data to Serial EEPROM\n");
+ return;
+ }
+ printf ("Done\n");
- /* setup node's Ethernet address */
- port_id = ((0 << 6) & 0xc0); /* two bits of port number ID */
- buffer[4] = (UINT8) (((serial_no & 0x3FFF) >> 8) | port_id);
- buffer[5] = (UINT8) (serial_no & 0x00FF);
+ /* setup node's Ethernet address */
+ port_id = ((0 << 6) & 0xc0); /* two bits of port number ID */
+ buffer[4] = (UINT8) (((serial_no & 0x3FFF) >> 8) | port_id);
+ buffer[5] = (UINT8) (serial_no & 0x00FF);
- temp_node_addr[0] = (UINT16) ((buffer[1] << 8) + buffer[0]);
- temp_node_addr[1] = (UINT16) ((buffer[3] << 8) + buffer[2]);
- temp_node_addr[2] = (UINT16) ((buffer[5] << 8) + buffer[4]);
-
- printf ("Writing the Individual Address to the Serial EEPROM... ");
- if (eeprom_write (adapter_ptr,ia_offset,temp_node_addr,3) != OK)
- {
- printf ("\nError writing the IA address to Serial EEPROM.\n");
- return;
- }
- printf ("Done\n");
+ temp_node_addr[0] = (UINT16) ((buffer[1] << 8) + buffer[0]);
+ temp_node_addr[1] = (UINT16) ((buffer[3] << 8) + buffer[2]);
+ temp_node_addr[2] = (UINT16) ((buffer[5] << 8) + buffer[4]);
+
+ printf ("Writing the Individual Address to the Serial EEPROM... ");
+ if (eeprom_write (adapter_ptr,ia_offset,temp_node_addr,3) != OK) {
+ printf ("\nError writing the IA address to Serial EEPROM.\n");
+ return;
+ }
+ printf ("Done\n");
-
- /* now that we have finished writing the configuration data, we must ask the
- operator to reset the PCI916 to have the configuration changes take effect.
- After the reset, the standard Enet. port diagnostics can be run on the 916
- under test */
-
- printf ("\n\n******** Reset the IQ80310 Now to Have Changes Take Effect ********\n\n");
-
- /* wait forever as a reset will bring us back */
- while ((volatile int)TRUE)
- ;
+ /* now that we have finished writing the configuration data, we must ask the
+ operator to reset the PCI916 to have the configuration changes take effect.
+ After the reset, the standard Enet. port diagnostics can be run on the 916
+ under test */
+
+ printf ("\n\n******** Reset the IQ80310 Now to Have Changes Take Effect ********\n\n");
+
+ /* wait forever as a reset will bring us back */
+ while ((volatile int)TRUE)
+ ;
}
/* use the clock in the Performance Monitoring Unit to do delays */
void polled_delay (int usec)
{
-volatile int i;
+ volatile int i;
- _enable_timer();
+ _enable_timer();
- for (i = 0; i < usec; i++)
- _usec_delay();
+ for (i = 0; i < usec; i++)
+ _usec_delay();
- _disable_timer();
+ _disable_timer();
}
-void internal_timer()
+void internal_timer(MENU_ARG arg)
{
- int j, i;
+ int j, i;
- printf ("\n");
+ printf ("\n");
- _enable_timer();
+ _enable_timer();
- printf ("Timer enabled...\n");
+ printf ("Timer enabled...\n");
- for (j = 0; j < 20; j++)
- {
- printf (".");
- for (i = 0; i < 1000; i++)
- _msec_delay();
- }
+ for (j = 0; j < 20; j++) {
+ printf (".");
+ for (i = 0; i < 1000; i++)
+ _msec_delay();
+ }
- _disable_timer();
+ _disable_timer();
- printf ("\nTimer disabled...\n");
+ printf ("\nTimer disabled...\n");
}
-
-
-
-
#define I80960RP_BRIDGE 0x0960
#define I80960RP_NAME0 "80960RP PCI-PCI Bridge"
#define I80960RP_ATU 0x1960
#define I80960RP_NAME1 "80960RP Address Translation Unit"
@@ -1316,11 +883,11 @@ void internal_timer()
#define I80960RN_NAME1 "80960RN Address Translation Unit"
#define I80303_BRIDGE 0x0309
#define I80303_NAME0 "80303 PCI-PCI Bridge"
-#define I80303_ATU 0x5309
+#define I80303_ATU 0x5309
#define I80303_NAME1 "80303 Address Translation Unit"
/******************************************************************/
@@ -1356,18 +923,17 @@ UINT32 messagingUnitBase = (UINT32)NULL;
* line_to_string - Returns name as string of particular XINT number
*
*/
static char *line_to_string (int intline)
{
- switch (intline)
- {
- case XINT0: return("XINT0");
- case XINT1: return("XINT1");
- case XINT2: return("XINT2");
- case XINT3: return("XINT3");
- default: return("ERROR");
- }
+ switch (intline) {
+ case XINT0: return("XINT0");
+ case XINT1: return("XINT1");
+ case XINT2: return("XINT2");
+ case XINT3: return("XINT3");
+ default: return("ERROR");
+ }
}
/***************************************************************************
*
@@ -1379,129 +945,80 @@ static char *line_to_string (int intline
* the doorbell register on the i960Rx card.
*
*/
int PCI_IntHandler (int IntPin)
{
- UINT32 *OutboundDbReg = (UINT32 *)(messagingUnitBase + 0x2c);
- UINT32 *OutboundIstatReg = (UINT32 *)(messagingUnitBase + 0x30);
+ UINT32 *OutboundDbReg = (UINT32 *)(messagingUnitBase + 0x2c);
+ UINT32 *OutboundIstatReg = (UINT32 *)(messagingUnitBase + 0x30);
- switch (IntPin)
- {
- case INTA:
-
- /* check to see if we are looking at the correct interrupt */
- if (!(*OutboundIstatReg & OB_STAT_INTA))
- {
- #if 0
- printf ("OISR Mismatch!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTA Error ****\n\n");
-
- /* try to clear all sources */
- *OutboundDbReg = (OB_DBELL_INTA|OB_DBELL_INTB|OB_DBELL_INTC|OB_DBELL_INTD);
- #endif
- return (0);
- }
- else
- {
- printf ("PCI INTA generated/received\n\n");
- printf ("OISR OK!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTA Success ****\n\n");
- *OutboundDbReg |= OB_DBELL_INTA; /* try to clear specific source */
- return (1);
- }
-
- break;
-
- case INTB:
-
- /* check to see if we are looking at the correct interrupt */
- if (!(*OutboundIstatReg & OB_STAT_INTB))
- {
- #if 0
- printf ("OISR Mismatch!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTB Error ****\n\n");
-
- /* try to clear all sources */
- *OutboundDbReg = (OB_DBELL_INTA|OB_DBELL_INTB|OB_DBELL_INTC|OB_DBELL_INTD);
- #endif
- return (0);
- }
- else
- {
- printf ("PCI INTB generated/received\n\n");
- printf ("OISR OK!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTB Success ****\n\n");
- *OutboundDbReg |= OB_DBELL_INTB; /* try to clear specific source */
- return (1);
- }
-
- break;
-
- case INTC:
-
- /* check to see if we are looking at the correct interrupt */
- if (!(*OutboundIstatReg & OB_STAT_INTC))
- {
- #if 0
- printf ("OISR Mismatch!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTC Error ****\n\n");
-
- /* try to clear all sources */
- *OutboundDbReg = (OB_DBELL_INTA|OB_DBELL_INTB|OB_DBELL_INTC|OB_DBELL_INTD);
- #endif
- return (0);
- }
- else
- {
- printf ("PCI INTC generated/received\n\n");
- printf ("OISR OK!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTC Success ****\n\n");
- *OutboundDbReg |= OB_DBELL_INTC; /* try to clear specific source */
- return (1);
- }
-
- break;
-
- case INTD:
-
- /* check to see if we are looking at the correct interrupt */
- if (!(*OutboundIstatReg & OB_STAT_INTD))
- {
- #if 0
- printf ("OISR Mismatch!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTD Error ****\n\n");
-
- /* try to clear all sources */
- *OutboundDbReg = (OB_DBELL_INTA|OB_DBELL_INTB|OB_DBELL_INTC|OB_DBELL_INTD);
- #endif
- return (0);
- }
- else
- {
- printf ("PCI INTD generated/received\n\n");
- printf ("OISR OK!\n");
- printf ("OISR = 0x%X\n", *OutboundIstatReg);
- printf ("**** PCI INTD Success ****\n\n");
- *OutboundDbReg |= OB_DBELL_INTD; /* try to clear specific source */
- return (1);
- }
-
- break;
-
- default:
- printf ("Unknown interrupt received\n");
- return (0);
- break;
- }
- return (1); /* interrupt sharing support requirement */
+ switch (IntPin) {
+ case INTA:
+
+ /* check to see if we are looking at the correct interrupt */
+ if (!(*OutboundIstatReg & OB_STAT_INTA)) {
+ return (0);
+ } else {
+ printf ("PCI INTA generated/received\n\n");
+ printf ("OISR OK!\n");
+ printf ("OISR = 0x%X\n", *OutboundIstatReg);
+ printf ("**** PCI INTA Success ****\n\n");
+ *OutboundDbReg |= OB_DBELL_INTA; /* try to clear specific source */
+ return (1);
+ }
+ break;
+
+ case INTB:
+ /* check to see if we are looking at the correct interrupt */
+ if (!(*OutboundIstatReg & OB_STAT_INTB)) {
+ return (0);
+ } else {
+ printf ("PCI INTB generated/received\n\n");
+ printf ("OISR OK!\n");
+ printf ("OISR = 0x%X\n", *OutboundIstatReg);
+ printf ("**** PCI INTB Success ****\n\n");
+ *OutboundDbReg |= OB_DBELL_INTB; /* try to clear specific source */
+ return (1);
+ }
+
+ break;
+
+ case INTC:
+ /* check to see if we are looking at the correct interrupt */
+ if (!(*OutboundIstatReg & OB_STAT_INTC)) {
+ return (0);
+ } else {
+ printf ("PCI INTC generated/received\n\n");
+ printf ("OISR OK!\n");
+ printf ("OISR = 0x%X\n", *OutboundIstatReg);
+ printf ("**** PCI INTC Success ****\n\n");
+ *OutboundDbReg |= OB_DBELL_INTC; /* try to clear specific source */
+ return (1);
+ }
+
+ break;
+
+ case INTD:
+ /* check to see if we are looking at the correct interrupt */
+ if (!(*OutboundIstatReg & OB_STAT_INTD)) {
+ return (0);
+ } else {
+ printf ("PCI INTD generated/received\n\n");
+ printf ("OISR OK!\n");
+ printf ("OISR = 0x%X\n", *OutboundIstatReg);
+ printf ("**** PCI INTD Success ****\n\n");
+ *OutboundDbReg |= OB_DBELL_INTD; /* try to clear specific source */
+ return (1);
+ }
+
+ break;
+
+ default:
+ printf ("Unknown interrupt received\n");
+ return (0);
+ break;
+ }
+ return (1); /* interrupt sharing support requirement */
}
/*******************************************************************************
*
@@ -1513,52 +1030,48 @@ int PCI_IntHandler (int IntPin)
* these processors is the input to the function.
*
*/
static void i960Rx_seek (UINT32 adapter_device_id)
{
-int dev_index = 0;
-PCI_DEVICE_LOCATION dev_info;
-static char *i960Rx_name;
-
- /* get the common name for the current Rx processor */
- switch (adapter_device_id)
- {
- case I80960RN_ATU:
- i960Rx_name = " i960RN ";
- break;
- case I80960RM_ATU:
- i960Rx_name = " i960RM ";
- break;
- case I80960RP_ATU:
- i960Rx_name = "i960RP/RD";
- break;
- case I80303_ATU:
- default:
- i960Rx_name = " i80303 ";
- break;
- }
-
- while (Device_Seek (FALSE, VENDOR_INTEL,
- adapter_device_id,
- dev_index, &dev_info) == OK)
- {
- /* set up this entry into the device array */
- i960Rx_devices[num_rx_devices].device_id = adapter_device_id;
- i960Rx_devices[num_rx_devices].busno = dev_info.bus_number;
- i960Rx_devices[num_rx_devices].devno = dev_info.device_number;
- i960Rx_devices[num_rx_devices].funcno = dev_info.function_number;
-
-
- printf (" %d %s %d %d %d\n",
- num_rx_devices, i960Rx_name,
- i960Rx_devices[num_rx_devices].busno,
- i960Rx_devices[num_rx_devices].devno,
- i960Rx_devices[num_rx_devices].funcno);
+ static char *i960Rx_name;
+ cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
+ int bus, devfn;
+
+ /* get the common name for the current Rx processor */
+ switch (adapter_device_id) {
+ case I80960RN_ATU:
+ i960Rx_name = " i960RN ";
+ break;
+ case I80960RM_ATU:
+ i960Rx_name = " i960RM ";
+ break;
+ case I80960RP_ATU:
+ i960Rx_name = "i960RP/RD";
+ break;
+ case I80303_ATU:
+ default:
+ i960Rx_name = " i80303 ";
+ break;
+ }
+
+ while (cyg_pci_find_device(VENDOR_INTEL, adapter_device_id, &devid)) {
+ bus = CYG_PCI_DEV_GET_BUS(devid);
+ devfn = CYG_PCI_DEV_GET_DEVFN(devid);
+ /* set up this entry into the device array */
+ i960Rx_devices[num_rx_devices].device_id = adapter_device_id;
+ i960Rx_devices[num_rx_devices].busno = bus;
+ i960Rx_devices[num_rx_devices].devno = CYG_PCI_DEV_GET_DEV(devfn);
+ i960Rx_devices[num_rx_devices].funcno = CYG_PCI_DEV_GET_FN(devfn);
+
+ printf (" %d %s %d %d %d\n",
+ num_rx_devices, i960Rx_name,
+ i960Rx_devices[num_rx_devices].busno,
+ i960Rx_devices[num_rx_devices].devno,
+ i960Rx_devices[num_rx_devices].funcno);
- dev_index++; /* increment number of current i960Rx devices found */
- num_rx_devices++; /* increment total number of i960Rx devices found */
- }
+ num_rx_devices++; /* increment total number of i960Rx devices found */
+ }
}
/*********************************************************************************
*
@@ -1571,261 +1084,249 @@ static char *i960Rx_name;
* the target board to trigger each interrupt using the i960Rx doorbell registers.
* The test passes if all four interrupts are recieved and properly handled by the
* IQ80310.
*
*/
-void pci_int_test (void)
+void pci_int_test (MENU_ARG arg)
{
- PCI_DEVICE_LOCATION devloc;
- int indexChoice = 0;
- UINT32 long_data;
- UINT32 *OutboundImaskReg;
+ int indexChoice = 0;
+ UINT32 long_data;
+ UINT32 *OutboundImaskReg;
int intline_INTA, intline_INTB, intline_INTC, intline_INTD;
+ cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
- num_rx_devices = 0;
+ num_rx_devices = 0;
- printf ("Scanning PCI Bus for all supported i960Rx ATU Devices.....\n\n");
-
- printf (" Index Processor Bus Device Function\n");
- printf (" ----- --------- --- ------ --------\n");
-
+ printf ("Scanning PCI Bus for all supported i960Rx ATU Devices.....\n\n");
+ printf (" Index Processor Bus Device Function\n");
+ printf (" ----- --------- --- ------ --------\n");
- i960Rx_seek (I80960RN_ATU);
- i960Rx_seek (I80960RM_ATU);
- i960Rx_seek (I80960RP_ATU);
- i960Rx_seek (I80303_ATU);
+ i960Rx_seek (I80960RN_ATU);
+ i960Rx_seek (I80960RM_ATU);
+ i960Rx_seek (I80960RP_ATU);
+ i960Rx_seek (I80303_ATU);
- if (num_rx_devices == 0)
- {
- printf ("\n*** No i960Rx ATU Found on PCI Bus ***\n");
- return;
- }
+ if (num_rx_devices == 0) {
+ printf ("\n*** No i960Rx ATU Found on PCI Bus ***\n");
+ return;
+ }
- printf ("Enter index number to use for test : ");
- indexChoice = decIn();
- printf ("\n\n");
-
- if (indexChoice >= num_rx_devices)
- {
- printf ("Invalid index chosen, exiting\n");
- return;
- }
+ printf ("Enter index number to use for test : ");
+ indexChoice = decIn();
+ printf ("\n\n");
- devloc.bus_number = i960Rx_devices[indexChoice].busno;
- devloc.device_number = i960Rx_devices[indexChoice].devno;
- devloc.function_number = i960Rx_devices[indexChoice].funcno;
+ if (indexChoice >= num_rx_devices) {
+ printf ("Invalid index chosen, exiting\n");
+ return;
+ }
-
- sys_read_config_dword (devloc.bus_number,
- devloc.device_number,
- devloc.function_number,
- REGION0_BASE_OFFSET,(UINT32*)&long_data);
-
- messagingUnitBase = long_data & 0xfffffff0;
- printf ("Messaging Unit PCI Base Address = 0x%X\n", messagingUnitBase);
- OutboundImaskReg = (UINT32 *)(messagingUnitBase + 0x34);
-
- /* Normally, we would just read the intline value from the configuration
- space to determine where the interrupt is routed. However, the i960Rx
- only requested interrupt resources for one interrupt at a time... */
-
- /* compute interrupt routing values */
- if ((pci_to_xint(devloc.device_number, INTA, (int*)&intline_INTA)) ||
- (pci_to_xint(devloc.device_number, INTB, (int*)&intline_INTB)) ||
- (pci_to_xint(devloc.device_number, INTC, (int*)&intline_INTC)) ||
- (pci_to_xint(devloc.device_number, INTD, (int*)&intline_INTD)) == ERROR)
- {
- printf ("Error: Unable to connect PCI interrupts with IQ80310 interrupts\n");
- return;
- }
+
+ devid = CYG_PCI_DEV_MAKE_ID(i960Rx_devices[indexChoice].busno,
+ CYG_PCI_DEV_MAKE_DEVFN(i960Rx_devices[indexChoice].devno,
+ i960Rx_devices[indexChoice].funcno));
+
+ cyg_pci_read_config_uint32(devid, REGION0_BASE_OFFSET,(UINT32*)&long_data);
+
+ messagingUnitBase = long_data & 0xfffffff0;
+ printf ("Messaging Unit PCI Base Address = 0x%X\n", messagingUnitBase);
+ OutboundImaskReg = (UINT32 *)(messagingUnitBase + 0x34);
+
+ /* Normally, we would just read the intline value from the configuration
+ space to determine where the interrupt is routed. However, the i960Rx
+ only requested interrupt resources for one interrupt at a time... */
+
+ /* compute interrupt routing values */
+ if ((pci_to_xint(i960Rx_devices[indexChoice].devno, INTA, (int*)&intline_INTA)) ||
+ (pci_to_xint(i960Rx_devices[indexChoice].devno, INTB, (int*)&intline_INTB)) ||
+ (pci_to_xint(i960Rx_devices[indexChoice].devno, INTC, (int*)&intline_INTC)) ||
+ (pci_to_xint(i960Rx_devices[indexChoice].devno, INTD, (int*)&intline_INTD)) == ERROR) {
+ printf ("Error: Unable to connect PCI interrupts with IQ80310 interrupts\n");
+ return;
+ }
- printf ("i960Rx INTA pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTA));
- printf ("i960Rx INTB pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTB));
- printf ("i960Rx INTC pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTC));
- printf ("i960Rx INTD pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTD));
+ printf ("i960Rx INTA pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTA));
+ printf ("i960Rx INTB pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTB));
+ printf ("i960Rx INTC pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTC));
+ printf ("i960Rx INTD pin mapped to intLine %s on IQ80310\n", line_to_string(intline_INTD));
- /* Connect i960Rx PCI INTA Handler */
- if (pci_isr_connect (INTA, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTA)
- == ERROR )
- {
- printf ("Error Connecting INTA interrupt handler\n");
- return;
- }
- printf ("INTA Service Routine installed...\n");
+ /* Connect i960Rx PCI INTA Handler */
+ if (pci_isr_connect (INTA, i960Rx_devices[indexChoice].busno,
+ i960Rx_devices[indexChoice].devno, PCI_IntHandler, INTA)
+ == ERROR ) {
+ printf ("Error Connecting INTA interrupt handler\n");
+ return;
+ }
+ printf ("INTA Service Routine installed...\n");
- /* enable PCI INTA */
- enable_external_interrupt(SINTA_INT_ID);
+ /* enable PCI INTA */
+ enable_external_interrupt(SINTA_INT_ID);
- /* Connect i960Rx PCI INTB Handler */
- if (pci_isr_connect (INTB, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTB)
- == ERROR)
- {
- printf ("Error Connecting INTB interrupt handler\n");
- return;
- }
- printf ("INTB Service Routine installed...\n");
+ /* Connect i960Rx PCI INTB Handler */
+ if (pci_isr_connect (INTA, i960Rx_devices[indexChoice].busno,
+ i960Rx_devices[indexChoice].devno, PCI_IntHandler, INTB)
+ == ERROR) {
+ printf ("Error Connecting INTB interrupt handler\n");
+ return;
+ }
+ printf ("INTB Service Routine installed...\n");
- /* enable PCI INTB */
- enable_external_interrupt(SINTB_INT_ID);
+ /* enable PCI INTB */
+ enable_external_interrupt(SINTB_INT_ID);
- /* Connect i960Rx PCI INTC Handler */
- if (pci_isr_connect (INTC, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTC)
- == ERROR)
- {
- printf ("Error Connecting INTC interrupt handler\n");
- return;
- }
- printf ("INTC Service Routine installed...\n");
+ /* Connect i960Rx PCI INTC Handler */
+ if (pci_isr_connect (INTA, i960Rx_devices[indexChoice].busno,
+ i960Rx_devices[indexChoice].devno, PCI_IntHandler, INTC)
+ == ERROR) {
+ printf ("Error Connecting INTC interrupt handler\n");
+ return;
+ }
+ printf ("INTC Service Routine installed...\n");
- /* enable PCI INTC */
- enable_external_interrupt(SINTC_INT_ID);
+ /* enable PCI INTC */
+ enable_external_interrupt(SINTC_INT_ID);
- /* Connect i960Rx PCI INTD Handler */
- if (pci_isr_connect (INTD, devloc.bus_number, devloc.device_number, PCI_IntHandler, INTD)
- == ERROR)
- {
- printf ("Error Connecting INTD interrupt handler\n");
- return;
- }
- printf ("INTD Service Routine installed...\n");
+ /* Connect i960Rx PCI INTD Handler */
+ if (pci_isr_connect (INTA, i960Rx_devices[indexChoice].busno,
+ i960Rx_devices[indexChoice].devno, PCI_IntHandler, INTD)
+ == ERROR) {
+ printf ("Error Connecting INTD interrupt handler\n");
+ return;
+ }
+ printf ("INTD Service Routine installed...\n");
- /* enable PCI INTD */
- enable_external_interrupt(SINTD_INT_ID);
+ /* enable PCI INTD */
+ enable_external_interrupt(SINTD_INT_ID);
- /* make sure that the Outbound interrupts aren't masked */
- *OutboundImaskReg &= ~(OB_STAT_INTA | OB_STAT_INTB | OB_STAT_INTC | OB_STAT_INTD);
+ /* make sure that the Outbound interrupts aren't masked */
+ *OutboundImaskReg &= ~(OB_STAT_INTA | OB_STAT_INTB | OB_STAT_INTC | OB_STAT_INTD);
- /* let the ISR do the rest of the work... */
- printf ("Waiting for the PCI Interrupts to be received...\n\n");
- printf ("Hit <CR> when the test is complete\n\n\n");
+ /* let the ISR do the rest of the work... */
+ printf ("Waiting for the PCI Interrupts to be received...\n\n");
+ printf ("Hit <CR> when the test is complete\n\n\n");
- hexIn();
+ hexIn();
- return;
+ return;
}
/*******************************************/
/* Battery Backup SDRAM memory write test */
/*******************************************/
-static void battery_test_write (void)
-{
- unsigned long start_addr = SDRAM_BATTERY_TEST_BASE; /* Address to write to */
-
- /* Data to be written to address and read after the board has been powered off and powered back on */
- UINT32 junk = BATTERY_TEST_PATTERN;
-
- *(volatile UINT32 *)start_addr = junk;
-
- printf("\nThe value '");
- hex32out(BATTERY_TEST_PATTERN);
- printf ("' is now written in DRAM at address $");
- hex32out(SDRAM_BATTERY_TEST_BASE);
- printf(".\n\nYou can now power the board off, wait 60 seconds and power it back on.");
- printf("\nThen come back in the battery test menu and select option 2 to check data from DRAM.\n");
+static void battery_test_write (MENU_ARG arg)
+{
+ unsigned long start_addr = SDRAM_BATTERY_TEST_BASE; /* Address to write to */
- printf ("\nPress return to continue.\n");
- (void) hexIn();
+ /* Data to be written to address and read after the board has been powered off and powered back on */
+ UINT32 junk = BATTERY_TEST_PATTERN;
+
+ *(volatile UINT32 *)start_addr = junk;
+
+ printf("\nThe value '");
+ hex32out(BATTERY_TEST_PATTERN);
+ printf ("' is now written in DRAM at address $");
+ hex32out(SDRAM_BATTERY_TEST_BASE);
+ printf(".\n\nYou can now power the board off, wait 60 seconds and power it back on.");
+ printf("\nThen come back in the battery test menu and select option 2 to check data from DRAM.\n");
+
+ printf ("\nPress return to continue.\n");
+ (void) hexIn();
}
/******************************************/
/* Battery Backup SDRAM memory read test */
/******************************************/
-static void battery_test_read (void)
+static void battery_test_read (MENU_ARG arg)
{
- unsigned long start_addr = SDRAM_BATTERY_TEST_BASE; /* Address to read from */
- UINT32 value_written = BATTERY_TEST_PATTERN; /* Data that was written */
- UINT32 value_read;
-
- value_read = *(volatile UINT32 *)start_addr;
-
- printf ("Value written at address $");
- hex32out(SDRAM_BATTERY_TEST_BASE);
- printf (": ");
- hex32out(BATTERY_TEST_PATTERN);
- printf ("\nValue read at address $");
- hex32out(SDRAM_BATTERY_TEST_BASE);
- printf(" : ");
- hex32out(value_read);
-
- if (value_read == value_written) printf ("\n\nThe battery test is a success !\n");
- else
- {
- printf ("\n\n****************************\n");
- printf ("* The battery test failed. *\n");
- printf ("****************************\n");
- }
+ unsigned long start_addr = SDRAM_BATTERY_TEST_BASE; /* Address to read from */
+ UINT32 value_written = BATTERY_TEST_PATTERN; /* Data that was written */
+ UINT32 value_read;
+
+ value_read = *(volatile UINT32 *)start_addr;
+
+ printf ("Value written at address $");
+ hex32out(SDRAM_BATTERY_TEST_BASE);
+ printf (": ");
+ hex32out(BATTERY_TEST_PATTERN);
+ printf ("\nValue read at address $");
+ hex32out(SDRAM_BATTERY_TEST_BASE);
+ printf(" : ");
+ hex32out(value_read);
+
+ if (value_read == value_written)
+ printf ("\n\nThe battery test is a success !\n");
+ else {
+ printf ("\n\n****************************\n");
+ printf ("* The battery test failed. *\n");
+ printf ("****************************\n");
+ }
- printf ("\nBattery test done.\n");
- printf ("Press return to continue.\n");
- (void) hexIn();
+ printf ("\nBattery test done.\n");
+ printf ("Press return to continue.\n");
+ (void) hexIn();
}
/*************************************/
/* Battery Backup SDRAM memory menu */
/*************************************/
-static void battery_test_menu (void)
+static void battery_test_menu (MENU_ARG arg)
{
- /* Test Menu Table */
- static MENU_ITEM batteryMenu[] =
- {
- {"Write data to SDRAM", battery_test_write, NULL},
- {"Check data from SDRAM", battery_test_read, NULL},
- };
-
- unsigned int num_menu_items = (sizeof (batteryMenu) / sizeof (batteryMenu[0]));
-
-/* char menu_title[15] = "\n Battery Backup SDRAM memory test."; */
- char menu_title[36] = "\n Battery Backup SDRAM memory test.";
-
- printf ("\n*************************************************************************\n");
- printf ("* This test will enable you to perform a battery test in 4 steps: *\n");
- printf ("* 1/ Select option 1 to write the value '");
- hex32out(BATTERY_TEST_PATTERN);
- printf ("' to DRAM at address *\n* $");
- hex32out(SDRAM_BATTERY_TEST_BASE);
- printf (", *\n");
- printf ("* 2/ Power the board off and wait 60 seconds, *\n");
- printf ("* 3/ Power the board back on, *\n");
- printf ("* 4/ Select option 2 to read at address $");
- hex32out(SDRAM_BATTERY_TEST_BASE);
- printf (" and compare the *\n* value to the value written '");
- hex32out(BATTERY_TEST_PATTERN);
- printf ("'. *\n");
- printf ("*************************************************************************");
+ /* Test Menu Table */
+ static MENU_ITEM batteryMenu[] = {
+ {"Write data to SDRAM", battery_test_write, NULL},
+ {"Check data from SDRAM", battery_test_read, NULL},
+ };
+
+ unsigned int num_menu_items = (sizeof (batteryMenu) / sizeof (batteryMenu[0]));
+
+ /* char menu_title[15] = "\n Battery Backup SDRAM memory test."; */
+ char menu_title[36] = "\n Battery Backup SDRAM memory test.";
+
+ printf ("\n*************************************************************************\n");
+ printf ("* This test will enable you to perform a battery test in 4 steps: *\n");
+ printf ("* 1/ Select option 1 to write the value '");
+ hex32out(BATTERY_TEST_PATTERN);
+ printf ("' to DRAM at address *\n* $");
+ hex32out(SDRAM_BATTERY_TEST_BASE);
+ printf (", *\n");
+ printf ("* 2/ Power the board off and wait 60 seconds, *\n");
+ printf ("* 3/ Power the board back on, *\n");
+ printf ("* 4/ Select option 2 to read at address $");
+ hex32out(SDRAM_BATTERY_TEST_BASE);
+ printf (" and compare the *\n* value to the value written '");
+ hex32out(BATTERY_TEST_PATTERN);
+ printf ("'. *\n");
+ printf ("*************************************************************************");
- menu (batteryMenu, num_menu_items, menu_title, MENU_OPT_NONE);
- printf ("\n");
+ menu (batteryMenu, num_menu_items, menu_title, MENU_OPT_NONE);
+ printf ("\n");
}
/* 01/11/01 jwf */
/* Make the user select their host test platform type from a list of choices. */
/* If the user picks a Cyclone SB923 then modify the Outbound PCI Translate Register on the IQ80310 for the SB923 */
void select_host_test_system (void)
{
- char selection;
-
- printf("Select your Host test system\n\n");
- printf("Make a selection by typing a number.\n\n");
- printf("1 - Cyclone SB923\n");
- printf("2 - Personal Computer or other\n");
-
- do
- {
- selection = xgetchar();
- }
- while( (selection != '1') && (selection != '2') );
+ char selection;
- if (selection == '1')
- {
- /* Modify the Outbound PCI Translate Register for a SB923, at address 0x1254 */
- *(volatile UINT32 *) POMWVR_ADDR = 0xa0000000;
- }
+ printf("Select your Host test system\n\n");
+ printf("Make a selection by typing a number.\n\n");
+ printf("1 - Cyclone SB923\n");
+ printf("2 - Personal Computer or other\n");
+
+ do {
+ selection = xgetchar();
+ } while( (selection != '1') && (selection != '2') );
+
+ if (selection == '1') {
+ /* Modify the Outbound PCI Translate Register for a SB923, at address 0x1254 */
+ *(volatile UINT32 *) POMWVR_ADDR = 0xa0000000;
+ }
}
/* 02/09/01 jwf */
/* Read the 80200 Coyanosa ID register */
@@ -1833,17 +1334,13 @@ void select_host_test_system (void)
/* in a 32MB SDRAM DIMM */
/* Store from coprocessor register 15 to memory. */
/* ARM register R0 is the address after the transfer */
void read_coyanosa_id_reg (void)
{
-
- __asm__ ("ldr r0, = 0xA1FFFFFC");
-
- __asm__ ("mrc p15, 0, r1, c0, c0, 0");
-
- __asm__ ("str r1, [r0], #0");
-
+ __asm__ ("ldr r0, = 0xA1FFFFFC");
+ __asm__ ("mrc p15, 0, r1, c0, c0, 0");
+ __asm__ ("str r1, [r0], #0");
}
/* 02/09/01 jwf */
/*
@@ -1852,93 +1349,86 @@ void read_coyanosa_id_reg (void)
*2. Cpld version. Located in the 0xFE840000 (Read)
*3. Board Revision. Located at 0xFE830000 (Read)
*4. 80200 ID data Located in CP15 Register 0
*5. 80312 Stepping Located at 0x00001008
*/
-void version_info (void)
+void version_info (MENU_ARG arg)
{
- char board_rev;
+ char board_rev;
/* show revision information for operating system */
#if CYGNUS_CYGMON_OS
- extern void version(void); /* is defined in monitor.c */
- version();
+ extern void version(void); /* is defined in monitor.c */
+ version();
#endif
#if REDHAT_REDBOOT_OS
- extern void do_version(int argc, char *argv[]);/* is defined in main.c */
- do_version(0,0);
+ extern void do_version(int argc, char *argv[]);/* is defined in main.c */
+ do_version(0,0);
#endif
- board_rev = board_revision();
- if ( board_rev >= BOARD_REV_E )
- {
- /* read Board revision register and adjust numeric revision to letter revision, 0x1 <--> A */
- printf("\nBoard Revision = %c\n",(*BOARD_REV_REG_ADDR & BOARD_REV_MASK) + 'A' - 1 );
- }
- else
- {
- /* Board letter revision might be A or B or C or D */
- printf("\nBoard Revision Unknown!\n");
- }
+ board_rev = board_revision();
+ if ( board_rev >= BOARD_REV_E ) {
+ /* read Board revision register and adjust numeric revision to letter revision, 0x1 <--> A */
+ printf("\nBoard Revision = %c\n",(*BOARD_REV_REG_ADDR & BOARD_REV_MASK) + 'A' - 1 );
+ } else {
+ /* Board letter revision might be A or B or C or D */
+ printf("\nBoard Revision Unknown!\n");
+ }
- /* read CPLD revision register and adjust numeric revision to letter revision, 0x1 <--> A */
- printf("CPLD Revision = %c\n",(*CPLD_REV_REG_ADDR & BOARD_REV_MASK) + 'A' - 1 );
+ /* read CPLD revision register and adjust numeric revision to letter revision, 0x1 <--> A */
+ printf("CPLD Revision = %c\n",(*CPLD_REV_REG_ADDR & BOARD_REV_MASK) + 'A' - 1 );
- /* Read the 80200 Coyanosa ID register */
- read_coyanosa_id_reg();
+ /* Read the 80200 Coyanosa ID register */
+ read_coyanosa_id_reg();
- printf( "80200 Revision ID = 0x%x\n", ( *(volatile unsigned long *) COYANOSA_ID_BASE_ADDR) );
+ printf( "80200 Revision ID = 0x%x\n", ( *(volatile unsigned long *) COYANOSA_ID_BASE_ADDR) );
- /* read the 80312 Yavapai Revision ID register */
- printf( "80312 Revision ID = %d\n", (*(volatile unsigned char *) RIDR_ADDR) );
+ /* read the 80312 Yavapai Revision ID register */
+ printf( "80312 Revision ID = %d\n", (*(volatile unsigned char *) RIDR_ADDR) );
- printf ("\n\nStrike <CR> to exit this test.\n\n");
+ printf ("\n\nStrike <CR> to exit this test.\n\n");
- hexIn();
-
+ hexIn();
}
/* 02/09/01 jwf */
/* Determine if the CPLD supports a Board Revision Register. */
/* If a Board Revision Register exists then return the board revision number read from a dedicated CPLD register at memory address 0xfe830000 */
/* Otherwise return a default board revision number. */
char board_revision ()
{
- /* represents the ring indicator bit logic level in UART2 */
- unsigned char ri_state;
+ /* represents the ring indicator bit logic level in UART2 */
+ unsigned char ri_state;
- /* holds a board revision number */
- char board_rev;
+ /* holds a board revision number */
+ char board_rev;
- /* access UART2 MSR at memory address 0xfe810006 through the CYGMON serial port, J9 */
- ri_state = *( unsigned char * ) 0xfe810006;
- ri_state &= RI_MASK;
-
- /* RI# pin on UART2 is grounded */
- /* CPLD design supports a Board Revision Register implemention */
- if(ri_state == RI_MASK)
- {
- /* read Board Revision register and isolate LSN */
- board_rev = (*BOARD_REV_REG_ADDR & BOARD_REV_MASK);
-
- /* Board Rev is at E or higher */
- if (board_rev >= BOARD_REV_E)
- {
- return (board_rev);
- }
- }
+ /* access UART2 MSR at memory address 0xfe810006 through the CYGMON serial port, J9 */
+ ri_state = *( unsigned char * ) 0xfe810006;
+ ri_state &= RI_MASK;
+
+ /* RI# pin on UART2 is grounded */
+ /* CPLD design supports a Board Revision Register implemention */
+ if(ri_state == RI_MASK) {
+ /* read Board Revision register and isolate LSN */
+ board_rev = (*BOARD_REV_REG_ADDR & BOARD_REV_MASK);
+
+ /* Board Rev is at E or higher */
+ if (board_rev >= BOARD_REV_E)
+ return (board_rev);
+ }
- /* RI# pin on UART2 is pulled up to 3.3V. */
- /* Unknown Board Revision! */
- /* Unable to determine a board revision because the CPLD Board Revision Register */
- /* was never implemented for IQ80310 PCI-700 board REVs A,B,C, or D. */
- /* set a default board revision value of 0x2 <--> Rev B. */
- board_rev = 0x2;
+ /* RI# pin on UART2 is pulled up to 3.3V. */
+ /* Unknown Board Revision! */
+ /* Unable to determine a board revision because the CPLD Board Revision Register */
+ /* was never implemented for IQ80310 PCI-700 board REVs A,B,C, or D. */
+ /* set a default board revision value of 0x2 <--> Rev B. */
+ board_rev = 0x2;
- /* return a default value */
- return (board_rev);
+ /* return a default value */
+ return (board_rev);
}
Index: hal/arm/xscale/npwr/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/npwr/current/ChangeLog,v
retrieving revision 1.1
diff -u -p -5 -r1.1 ChangeLog
--- hal/arm/xscale/npwr/current/ChangeLog 12 Nov 2002 17:38:53 -0000 1.1
+++ hal/arm/xscale/npwr/current/ChangeLog 13 Nov 2002 15:41:10 -0000
@@ -1,5 +1,9 @@
+2002-11-13 Mark Salter <msalter@redhat.com>
+ * include/hal_platform_setup.h: Use IOP310_EARLY_PCI_SETUP to make
+ some BIOSes happy. BTB_INIT and MMU macros provided elsewhere.
+
2002-11-12 Gary Thomas <gary@mlbassoc.com>
* src/npwr_misc.c:
* include/pkgconf/mlt_arm_xscale_npwr_rom.mlt:
* include/pkgconf/mlt_arm_xscale_npwr_rom.ldi:
Index: hal/arm/xscale/npwr/current/include/hal_platform_setup.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/npwr/current/include/hal_platform_setup.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 hal_platform_setup.h
--- hal/arm/xscale/npwr/current/include/hal_platform_setup.h 12 Nov 2002 17:38:54 -0000 1.1
+++ hal/arm/xscale/npwr/current/include/hal_platform_setup.h 13 Nov 2002 15:41:11 -0000
@@ -54,13 +54,15 @@
//####DESCRIPTIONEND####
//
//===========================================================================*/
#include <pkgconf/system.h> // System-wide configuration info
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/hal_mm.h> // More MMU definitions
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
#include <cyg/hal/hal_iop310.h> // Platform specific hardware definitions
-#include <cyg/hal/hal_mmu.h> // MMU definitions
// Define macro used to diddle the LEDs during early initialization.
// Can use r0+r1. Argument in \x.
#define CYGHWR_LED_MACRO \
b 667f ;\
@@ -93,12 +95,10 @@
#define RAM_BASE 0xa0000000
#define DRAM_SIZE (512*1024*1024) // max size of available SDRAM
#define DCACHE_SIZE (32*1024) // size of the Dcache
-#define MMU_Control_BTB 0x800
-
// Reserved area for battery backup SDRAM memory test
// This area is not zeroed out by initialization code
#define SDRAM_BATTERY_TEST_BASE 0xA1FFFFF0 // base address of last 16 memory locations in a 32MB SDRAM
@@ -136,20 +136,10 @@
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
- // Enable the BTB
- .macro BTB_INIT reg
-#ifdef CYGSEM_HAL_ARM_IOP310_BTB
- mrc p15, 0, \reg, c1, c0, 0
- orr \reg, \reg, #MMU_Control_BTB
- mcr p15, 0, \reg, c1, c0, 0
- CPWAIT \reg
-#endif
- .endm
-
// form a first-level section entry
.macro FL_SECTION_ENTRY base,x,ap,p,d,c,b
.word (\base << 20) | (\x << 12) | (\ap << 10) | (\p << 9) |\
(\d << 5) | (\c << 3) | (\b << 2) | 2
.endm
@@ -725,10 +715,12 @@ SDRAM_DRIVE_2_BANK_X8:
// Move 4 byte Test Pattern into register prior to zeroing out
// contents of SDRAM locations
ldr r9, =SDRAM_BATTERY_TEST_BASE
ldr r10, [r9]
+ IOP310_EARLY_PCI_SETUP r0, r1, r4, 0x113C, 0x0700
+
// scrub/init SDRAM if enabled/present
ldr r11, =RAM_BASE // base address of SDRAM
mov r12, r4 // size of memory to scrub
mov r8,r4 // save DRAM size
mov r0, #0 // scrub with 0x0000:0000