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XScale tweaks
- From: Mark Salter <msalter at redhat dot com>
- To: ecos-patches at sources dot redhat dot com
- Date: Wed, 22 Jan 2003 08:33:59 -0500 (EST)
- Subject: XScale tweaks
Mostly fixes for some issues turned up by gcc-3.3.
--Mark
Index: hal/arm/xscale/iop310/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/ChangeLog,v
retrieving revision 1.2
diff -u -p -5 -r1.2 ChangeLog
--- hal/arm/xscale/iop310/current/ChangeLog 13 Nov 2002 15:43:20 -0000 1.2
+++ hal/arm/xscale/iop310/current/ChangeLog 22 Jan 2003 13:29:53 -0000
@@ -1,5 +1,12 @@
+2003-01-22 Mark Salter <msalter@redhat.com>
+
+ * include/var_io.h: Remove unused duplicate code.
+ * include/hal_iop310.h: Add some more register definitions.
+ * src/iop310_pci.c (cyg_hal_plf_pci_init): Use new register
+ definitions.
+
2002-11-13 Mark Salter <msalter@redhat.com>
* src/iop310_pci.c (cyg_hal_plf_pci_init): Reorganize to deal with
early PCI setup. Also fix support for primary side bridges when
acting as PCI host.
Index: hal/arm/xscale/iop310/current/include/hal_iop310.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/include/hal_iop310.h,v
retrieving revision 1.2
diff -u -p -5 -r1.2 hal_iop310.h
--- hal/arm/xscale/iop310/current/include/hal_iop310.h 13 Nov 2002 15:43:21 -0000 1.2
+++ hal/arm/xscale/iop310/current/include/hal_iop310.h 22 Jan 2003 13:29:54 -0000
@@ -9,11 +9,11 @@
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
@@ -67,36 +67,36 @@ extern void hal_plf_hardware_init(void);
#define IOP310_SERIAL_PORT_B 0xFE810000
#define DCACHE_FLUSH_AREA 0xc0000000
// Addresses of the left and right 7-segment display
-#define DISPLAY_LEFT 0xFE840000
-#define DISPLAY_RIGHT 0xFE850000
+#define DISPLAY_LEFT 0xFE840000
+#define DISPLAY_RIGHT 0xFE850000
// 7-segment encodings for the hex display
-#define DISPLAY_0 0xc0
-#define DISPLAY_1 0xf9
-#define DISPLAY_2 0xa4
-#define DISPLAY_3 0xb0
-#define DISPLAY_4 0x99
-#define DISPLAY_5 0x92
-#define DISPLAY_6 0x82
-#define DISPLAY_7 0xF8
-#define DISPLAY_8 0x80
-#define DISPLAY_9 0x90
-#define DISPLAY_A 0x88
-#define DISPLAY_B 0x83
-#define DISPLAY_C 0xa7
-#define DISPLAY_D 0xa1
-#define DISPLAY_E 0x86
-#define DISPLAY_F 0x8e
+#define DISPLAY_0 0xc0
+#define DISPLAY_1 0xf9
+#define DISPLAY_2 0xa4
+#define DISPLAY_3 0xb0
+#define DISPLAY_4 0x99
+#define DISPLAY_5 0x92
+#define DISPLAY_6 0x82
+#define DISPLAY_7 0xF8
+#define DISPLAY_8 0x80
+#define DISPLAY_9 0x90
+#define DISPLAY_A 0x88
+#define DISPLAY_B 0x83
+#define DISPLAY_C 0xa7
+#define DISPLAY_D 0xa1
+#define DISPLAY_E 0x86
+#define DISPLAY_F 0x8e
#ifndef iop310_is_host
/* Backplane Detect Register */
-#define BACKPLANE_DET_REG ((volatile unsigned char *)0xfe870000)
-# define BP_HOST_BIT 0x1
-#define iop310_is_host() (*BACKPLANE_DET_REG & BP_HOST_BIT)
+#define BACKPLANE_DET_REG ((volatile unsigned char *)0xfe870000)
+# define BP_HOST_BIT 0x1
+#define iop310_is_host() (*BACKPLANE_DET_REG & BP_HOST_BIT)
#endif
// XINT3 mask register
#define X3ISR_REG ((volatile unsigned char *)0xfe820000)
#define X3MASK_REG ((volatile unsigned char *)0xfe860000)
@@ -105,29 +105,29 @@ extern void hal_plf_hardware_init(void);
# define XINT3_UART_1 0x04
# define XINT3_UART_2 0x08
# define XINT3_PCI_INTD 0x10
/* PAL-based external timer definitions */
-#define TIMER_LA0_REG_ADDR ((volatile unsigned char *)0xfe880000)
-#define TIMER_LA1_REG_ADDR ((volatile unsigned char *)0xfe890000)
-#define TIMER_LA2_REG_ADDR ((volatile unsigned char *)0xfe8a0000)
-#define TIMER_LA3_REG_ADDR ((volatile unsigned char *)0xfe8b0000)
-#define TIMER_ENABLE_REG_ADDR ((volatile unsigned char *)0xfe8c0000)
-
-#define TIMER_COUNT_MASK 0x5f /* 6 bits of timer data with the MSB in bit 6 not bit 5 */
-#define TIMER_CNT_ENAB 0x1
-#define TIMER_INT_ENAB 0x2
-#define EXT_TIMER_CLK_FREQ 33000000 /* external timer runs at 33 MHz */
-#define TICKS_10MSEC 100 /* 10msec = 100 ticks/sec */
-#define EXT_TIMER_10MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_10MSEC)
-#define TICKS_5MSEC 200 /* 5msec = 200 ticks/sec */
-#define EXT_TIMER_5MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_5MSEC)
-
-#define EXT_TIMER_CNT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_CNT_ENAB)
-#define EXT_TIMER_CNT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_CNT_ENAB)
-#define EXT_TIMER_INT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_INT_ENAB)
-#define EXT_TIMER_INT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_INT_ENAB)
+#define TIMER_LA0_REG_ADDR ((volatile unsigned char *)0xfe880000)
+#define TIMER_LA1_REG_ADDR ((volatile unsigned char *)0xfe890000)
+#define TIMER_LA2_REG_ADDR ((volatile unsigned char *)0xfe8a0000)
+#define TIMER_LA3_REG_ADDR ((volatile unsigned char *)0xfe8b0000)
+#define TIMER_ENABLE_REG_ADDR ((volatile unsigned char *)0xfe8c0000)
+
+#define TIMER_COUNT_MASK 0x5f /* 6 bits of timer data with the MSB in bit 6 not bit 5 */
+#define TIMER_CNT_ENAB 0x1
+#define TIMER_INT_ENAB 0x2
+#define EXT_TIMER_CLK_FREQ 33000000 /* external timer runs at 33 MHz */
+#define TICKS_10MSEC 100 /* 10msec = 100 ticks/sec */
+#define EXT_TIMER_10MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_10MSEC)
+#define TICKS_5MSEC 200 /* 5msec = 200 ticks/sec */
+#define EXT_TIMER_5MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_5MSEC)
+
+#define EXT_TIMER_CNT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_CNT_ENAB)
+#define EXT_TIMER_CNT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_CNT_ENAB)
+#define EXT_TIMER_INT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_INT_ENAB)
+#define EXT_TIMER_INT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_INT_ENAB)
// Companion chip MCU registers
#define MMR_BASE 0x00001500
#define SDIR_OFF 0x00000000
#define SDCR_OFF 0x00000004
@@ -162,348 +162,348 @@ extern void hal_plf_hardware_init(void);
/**************************
* I2C Bus Interface Unit *
**************************/
/* Processor I2C Device ID */
-#define I2C_DEVID 0x02 /* I2C slave address to which the unit responds when in slave-receive mode */
+#define I2C_DEVID 0x02 /* I2C slave address to which the unit responds when in slave-receive mode */
/* Timeout limit for SDRAM EEPROM to respond */
-#define I2C_TIMOUT 0x1000000 /* bumped this way up...used to be 0x100000*/
+#define I2C_TIMOUT 0x1000000 /* bumped this way up...used to be 0x100000*/
/* Control Register */
-#define ICR_ADDR 0x00001680 /* Address */
-#define ICR_START 0x0001 /* 1:send a Start condition to the I2C when in master mode */
-#define ICR_STOP 0x0002 /* 1:send a Stop condition after next data byte transferred on I2C bus in master mode */
-#define ICR_ACK 0x0004 /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
-#define ICR_TRANSFER 0x0008 /* 1:send/receive byte, 0:cleared by I2C unit when done */
-#define ICR_ABORT 0x0010 /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
-#define ICR_SCLENB 0x0020 /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
-#define ICR_ENB 0x0040 /* I2C unit: 1:Enabled, 0:Disabled */
-#define ICR_GCALL 0x0080 /* General Call: 1:Disabled, 0:Enabled */
-#define ICR_IEMPTY 0x0100 /* 1: IDBR Transmit Empty Interrupt Enable */
-#define ICR_IFULL 0x0200 /* 1: IDBR Receive Full Interrupt Enable */
-#define ICR_IERR 0x0400 /* 1: Bus Error Interrupt Enable */
-#define ICR_ISTOP 0x0800 /* 1: Slave Stop Detected Interrupt Enable */
-#define ICR_IARB 0x1000 /* 1: Arbitration Loss Detected Interrupt Enable */
-#define ICR_ISADDR 0x2000 /* 1: Slave Address Detected Interrupt Enable */
-#define ICR_RESET 0x4000 /* 1: I2C unit reset */
+#define ICR_ADDR 0x00001680 /* Address */
+#define ICR_START 0x0001 /* 1:send a Start condition to the I2C when in master mode */
+#define ICR_STOP 0x0002 /* 1:send a Stop condition after next data byte transferred on I2C bus in master mode */
+#define ICR_ACK 0x0004 /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
+#define ICR_TRANSFER 0x0008 /* 1:send/receive byte, 0:cleared by I2C unit when done */
+#define ICR_ABORT 0x0010 /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
+#define ICR_SCLENB 0x0020 /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
+#define ICR_ENB 0x0040 /* I2C unit: 1:Enabled, 0:Disabled */
+#define ICR_GCALL 0x0080 /* General Call: 1:Disabled, 0:Enabled */
+#define ICR_IEMPTY 0x0100 /* 1: IDBR Transmit Empty Interrupt Enable */
+#define ICR_IFULL 0x0200 /* 1: IDBR Receive Full Interrupt Enable */
+#define ICR_IERR 0x0400 /* 1: Bus Error Interrupt Enable */
+#define ICR_ISTOP 0x0800 /* 1: Slave Stop Detected Interrupt Enable */
+#define ICR_IARB 0x1000 /* 1: Arbitration Loss Detected Interrupt Enable */
+#define ICR_ISADDR 0x2000 /* 1: Slave Address Detected Interrupt Enable */
+#define ICR_RESET 0x4000 /* 1: I2C unit reset */
/* Status Register */
-#define ISR_ADDR 0x00001684 /* Address */
-#define ISR_RWMODE 0x0001 /* 1: I2C in master receive = slave transmit mode */
-#define ISR_ACK 0x0002 /* 1: I2C received/sent a Nack, 0: Ack */
-#define ISR_BUSY 0x0004 /* 1: Processor's I2C unit busy */
-#define ISR_BUSBUSY 0x0008 /* 1: I2C bus busy. Processor's I2C unit not involved */
-#define ISR_STOP 0x0010 /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
-#define ISR_ARB 0x0020 /* 1: Arbitration Loss Detected */
-#define ISR_EMPTY 0x0040 /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
-#define ISR_FULL 0x0080 /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
-#define ISR_GCALL 0x0100 /* 1: I2C unit received a General Call address */
-#define ISR_SADDR 0x0200 /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
-#define ISR_ERROR 0x0400 /* Bit set by unit when a Bus Error detected */
-
-#define ISAR_ADDR 0x00001688 /* Address of the I2C Slave Address Register */
-#define IDBR_ADDR 0x0000168C /* Address of the I2C Data Buffer Register */
-#define IDBR_MASK 0x000000ff
-#define IDBR_MODE 0x01
-#define ICCR_ADDR 0x00001690 /* Address of the I2C Clock Control Register */
-#define IBMR_ADDR 0x00001694 /* Address of the I2C Bus Monitor Register */
+#define ISR_ADDR 0x00001684 /* Address */
+#define ISR_RWMODE 0x0001 /* 1: I2C in master receive = slave transmit mode */
+#define ISR_ACK 0x0002 /* 1: I2C received/sent a Nack, 0: Ack */
+#define ISR_BUSY 0x0004 /* 1: Processor's I2C unit busy */
+#define ISR_BUSBUSY 0x0008 /* 1: I2C bus busy. Processor's I2C unit not involved */
+#define ISR_STOP 0x0010 /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
+#define ISR_ARB 0x0020 /* 1: Arbitration Loss Detected */
+#define ISR_EMPTY 0x0040 /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
+#define ISR_FULL 0x0080 /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
+#define ISR_GCALL 0x0100 /* 1: I2C unit received a General Call address */
+#define ISR_SADDR 0x0200 /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
+#define ISR_ERROR 0x0400 /* Bit set by unit when a Bus Error detected */
+
+#define ISAR_ADDR 0x00001688 /* Address of the I2C Slave Address Register */
+#define IDBR_ADDR 0x0000168C /* Address of the I2C Data Buffer Register */
+#define IDBR_MASK 0x000000ff
+#define IDBR_MODE 0x01
+#define ICCR_ADDR 0x00001690 /* Address of the I2C Clock Control Register */
+#define IBMR_ADDR 0x00001694 /* Address of the I2C Bus Monitor Register */
/* SDRAM configuration */
/* SDRAM bank size values (SPD << 2) */
-#define RAM_0MEG
-#define RAM_4MEG 4
-#define RAM_8MEG 8
-#define RAM_16MEG 16
-#define RAM_32MEG 32
-#define RAM_64MEG 64
-#define RAM_128MEG 128
-#define RAM_256MEG 256
+#define RAM_0MEG
+#define RAM_4MEG 4
+#define RAM_8MEG 8
+#define RAM_16MEG 16
+#define RAM_32MEG 32
+#define RAM_64MEG 64
+#define RAM_128MEG 128
+#define RAM_256MEG 256
/* SBR register definitions (valid bits are [7:3])*/
-#define SBR_32MEG 0x08
-#define SBR_64MEG 0x10
-#define SBR_128MEG 0x20
-#define SBR_256MEG 0x40
+#define SBR_32MEG 0x08
+#define SBR_64MEG 0x10
+#define SBR_128MEG 0x20
+#define SBR_256MEG 0x40
/* Drive Strengths - assume single DIMM configuration */
-#define SDCR_1BANK_X16 0x0aa0
-#define SDCR_2BANK_X16 0x12c8
-#define SDCR_1BANK_X8 0x1520
-#define SDCR_2BANK_X8 0x1548
-
-/* SDRAM PD bytes */
-#define BANKCNT_BYTE 0x06 /* Byte #5 of SPD: number of module banks */
-#define SDRAM_WIDTH_BYTE 0x0e /* Byte #13 of SPD: DRAM width */
-#define BANKSZ_BYTE 0x20 /* Byte #31 of SPD: module bank density */
-#define CHECKSUM_BYTE 0x40 /* Byte #63 of SPD: checksum for bytes 0-62 */
-#define CONFIG_BYTE 0x0C /* Byte #11 of SPD: DIMM configuration type (Parity or not, EEC) */
+#define SDCR_1BANK_X16 0x0aa0
+#define SDCR_2BANK_X16 0x12c8
+#define SDCR_1BANK_X8 0x1520
+#define SDCR_2BANK_X8 0x1548
+
+/* SDRAM PD bytes */
+#define BANKCNT_BYTE 0x06 /* Byte #5 of SPD: number of module banks */
+#define SDRAM_WIDTH_BYTE 0x0e /* Byte #13 of SPD: DRAM width */
+#define BANKSZ_BYTE 0x20 /* Byte #31 of SPD: module bank density */
+#define CHECKSUM_BYTE 0x40 /* Byte #63 of SPD: checksum for bytes 0-62 */
+#define CONFIG_BYTE 0x0C /* Byte #11 of SPD: DIMM configuration type (Parity or not, EEC) */
-#define SDRAM_DEVID 0xA2 /* SDRAM Device ID */
+#define SDRAM_DEVID 0xA2 /* SDRAM Device ID */
// Yavapai PCI and Peripheral Interrupt Unit
/*** Yavapai Registers ***/
/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
-#define VIDR_ADDR 0x00001000
-#define DIDR_ADDR 0x00001002
-#define PCR_ADDR 0x00001004
-#define PSR_ADDR 0x00001006
-#define RIDR_ADDR 0x00001008
-#define CCR_ADDR 0x00001009
-#define CLSR_ADDR 0x0000100C
-#define PLTR_ADDR 0x0000100D
-#define HTR_ADDR 0x0000100E
+#define VIDR_ADDR 0x00001000
+#define DIDR_ADDR 0x00001002
+#define PCR_ADDR 0x00001004
+#define PSR_ADDR 0x00001006
+#define RIDR_ADDR 0x00001008
+#define CCR_ADDR 0x00001009
+#define CLSR_ADDR 0x0000100C
+#define PLTR_ADDR 0x0000100D
+#define HTR_ADDR 0x0000100E
/* Reserved 0x0000100F through 0x00001017 */
-#define PBNR_ADDR 0x00001018
-#define SBNR_ADDR 0x00001019
-#define SUBBNR_ADDR 0x0000101A
-#define SLTR_ADDR 0x0000101B
-#define IOBR_ADDR 0x0000101C
-#define IOLR_ADDR 0x0000101D
-#define SSR_ADDR 0x0000101E
-#define MBR_ADDR 0x00001020
-#define MLR_ADDR 0x00001022
-#define PMBR_ADDR 0x00001024
-#define PMLR_ADDR 0x00001026
+#define PBNR_ADDR 0x00001018
+#define SBNR_ADDR 0x00001019
+#define SUBBNR_ADDR 0x0000101A
+#define SLTR_ADDR 0x0000101B
+#define IOBR_ADDR 0x0000101C
+#define IOLR_ADDR 0x0000101D
+#define SSR_ADDR 0x0000101E
+#define MBR_ADDR 0x00001020
+#define MLR_ADDR 0x00001022
+#define PMBR_ADDR 0x00001024
+#define PMLR_ADDR 0x00001026
/* Reserved 0x00001028 through 0x00001033 */
-#define BSVIR_ADDR 0x00001034
-#define BSIR_ADDR 0x00001036
+#define BSVIR_ADDR 0x00001034
+#define BSIR_ADDR 0x00001036
/* Reserved 0x00001038 through 0x0000103D */
-#define BCR_ADDR 0x0000103E
-#define EBCR_ADDR 0x00001040
-#define SISR_ADDR 0x00001042
-#define PBISR_ADDR 0x00001044
-#define SBISR_ADDR 0x00001048
-#define SACR_ADDR 0x0000104C
-#define PIRSR_ADDR 0x00001050
-#define SIOBR_ADDR 0x00001054
-#define SIOLR_ADDR 0x00001055
-#define SCCR_ADDR 0x00001056 /* EAS inconsistent */
-#define SMBR_ADDR 0x00001058
-#define SMLR_ADDR 0x0000105A
-#define SDER_ADDR 0x0000105C
-#define QCR_ADDR 0x0000105E
-#define CDTR_ADDR 0x00001060 /* EAS inconsistent */
+#define BCR_ADDR 0x0000103E
+#define EBCR_ADDR 0x00001040
+#define SISR_ADDR 0x00001042
+#define PBISR_ADDR 0x00001044
+#define SBISR_ADDR 0x00001048
+#define SACR_ADDR 0x0000104C
+#define PIRSR_ADDR 0x00001050
+#define SIOBR_ADDR 0x00001054
+#define SIOLR_ADDR 0x00001055
+#define SCCR_ADDR 0x00001056 /* EAS inconsistent */
+#define SMBR_ADDR 0x00001058
+#define SMLR_ADDR 0x0000105A
+#define SDER_ADDR 0x0000105C
+#define QCR_ADDR 0x0000105E
+#define CDTR_ADDR 0x00001060 /* EAS inconsistent */
/* Reserved 0x00001064 through 0x000010FFH */
/* Performance Monitoring Unit 0000 1100H through 0000 11FFH */
-#define GTMR_ADDR 0x00001100
-#define ESR_ADDR 0x00001104
-#define EMISR_ADDR 0x00001108
-/* Reserved 0x0000110C */ /* EAS inconsistent */
-#define GTSR_ADDR 0x00001110 /* EAS inconsistent */
-#define PECR1_ADDR 0x00001114 /* EAS inconsistent */
-#define PECR2_ADDR 0x00001118 /* EAS inconsistent */
-#define PECR3_ADDR 0x0000111C /* EAS inconsistent */
-#define PECR4_ADDR 0x00001120 /* EAS inconsistent */
-#define PECR5_ADDR 0x00001124 /* EAS inconsistent */
-#define PECR6_ADDR 0x00001128 /* EAS inconsistent */
-#define PECR7_ADDR 0x0000112C /* EAS inconsistent */
-#define PECR8_ADDR 0x00001130 /* EAS inconsistent */
-#define PECR9_ADDR 0x00001134 /* EAS inconsistent */
-#define PECR10_ADDR 0x00001138 /* EAS inconsistent */
-#define PECR11_ADDR 0x0000113C /* EAS inconsistent */
-#define PECR12_ADDR 0x00001140 /* EAS inconsistent */
-#define PECR13_ADDR 0x00001144 /* EAS inconsistent */
-#define PECR14_ADDR 0x00001148 /* EAS inconsistent */
-/* Reserved 0x0000104C through 0x000011FFH */ /* EAS inconsistent */
+#define GTMR_ADDR 0x00001100
+#define ESR_ADDR 0x00001104
+#define EMISR_ADDR 0x00001108
+/* Reserved 0x0000110C */ /* EAS inconsistent */
+#define GTSR_ADDR 0x00001110 /* EAS inconsistent */
+#define PECR1_ADDR 0x00001114 /* EAS inconsistent */
+#define PECR2_ADDR 0x00001118 /* EAS inconsistent */
+#define PECR3_ADDR 0x0000111C /* EAS inconsistent */
+#define PECR4_ADDR 0x00001120 /* EAS inconsistent */
+#define PECR5_ADDR 0x00001124 /* EAS inconsistent */
+#define PECR6_ADDR 0x00001128 /* EAS inconsistent */
+#define PECR7_ADDR 0x0000112C /* EAS inconsistent */
+#define PECR8_ADDR 0x00001130 /* EAS inconsistent */
+#define PECR9_ADDR 0x00001134 /* EAS inconsistent */
+#define PECR10_ADDR 0x00001138 /* EAS inconsistent */
+#define PECR11_ADDR 0x0000113C /* EAS inconsistent */
+#define PECR12_ADDR 0x00001140 /* EAS inconsistent */
+#define PECR13_ADDR 0x00001144 /* EAS inconsistent */
+#define PECR14_ADDR 0x00001148 /* EAS inconsistent */
+/* Reserved 0x0000104C through 0x000011FFH */ /* EAS inconsistent */
/* Address Translation Unit 0000 1200H through 0000 12FFH */
-#define ATUVID_ADDR 0x00001200
-#define ATUDID_ADDR 0x00001202
-#define PATUCMD_ADDR 0x00001204
-#define PATUSR_ADDR 0x00001206
-#define ATURID_ADDR 0x00001208
-#define ATUCCR_ADDR 0x00001209
-#define ATUCLSR_ADDR 0x0000120C
-#define ATULT_ADDR 0x0000120D
-#define ATUHTR_ADDR 0x0000120E
-#define ATUBISTR_ADDR 0x0000120F
-#define PIABAR_ADDR 0x00001210
+#define ATUVID_ADDR 0x00001200
+#define ATUDID_ADDR 0x00001202
+#define PATUCMD_ADDR 0x00001204
+#define PATUSR_ADDR 0x00001206
+#define ATURID_ADDR 0x00001208
+#define ATUCCR_ADDR 0x00001209
+#define ATUCLSR_ADDR 0x0000120C
+#define ATULT_ADDR 0x0000120D
+#define ATUHTR_ADDR 0x0000120E
+#define ATUBISTR_ADDR 0x0000120F
+#define PIABAR_ADDR 0x00001210
/* Reserved 0x00001214 through 0x0000122B */
-#define ASVIR_ADDR 0x0000122C
-#define ASIR_ADDR 0x0000122E
-#define ERBAR_ADDR 0x00001230
+#define ASVIR_ADDR 0x0000122C
+#define ASIR_ADDR 0x0000122E
+#define ERBAR_ADDR 0x00001230
/* Reserved 0x00001234 */
/* Reserved 0x00001238 */
-#define ATUILR_ADDR 0x0000123C
-#define ATUIPR_ADDR 0x0000123D
-#define ATUMGNT_ADDR 0x0000123E
-#define ATUMLAT_ADDR 0x0000123F
-#define PIALR_ADDR 0x00001240
-#define PIATVR_ADDR 0x00001244
-#define SIABAR_ADDR 0x00001248
-#define SIALR_ADDR 0x0000124C
-#define SIATVR_ADDR 0x00001250
-#define POMWVR_ADDR 0x00001254
+#define ATUILR_ADDR 0x0000123C
+#define ATUIPR_ADDR 0x0000123D
+#define ATUMGNT_ADDR 0x0000123E
+#define ATUMLAT_ADDR 0x0000123F
+#define PIALR_ADDR 0x00001240
+#define PIATVR_ADDR 0x00001244
+#define SIABAR_ADDR 0x00001248
+#define SIALR_ADDR 0x0000124C
+#define SIATVR_ADDR 0x00001250
+#define POMWVR_ADDR 0x00001254
/* Reserved 0x00001258 */
-#define POIOWVR_ADDR 0x0000125C
-#define PODWVR_ADDR 0x00001260
-#define POUDR_ADDR 0x00001264
-#define SOMWVR_ADDR 0x00001268
-#define SOIOWVR_ADDR 0x0000126C
+#define POIOWVR_ADDR 0x0000125C
+#define PODWVR_ADDR 0x00001260
+#define POUDR_ADDR 0x00001264
+#define SOMWVR_ADDR 0x00001268
+#define SOIOWVR_ADDR 0x0000126C
/* Reserved 0x00001270 */
-#define ERLR_ADDR 0x00001274
-#define ERTVR_ADDR 0x00001278
+#define ERLR_ADDR 0x00001274
+#define ERTVR_ADDR 0x00001278
/* Reserved 0x0000127C */
/* Reserved 0x00001280 */
/* Reserved 0x00001284 */
-#define ATUCR_ADDR 0x00001288
+#define ATUCR_ADDR 0x00001288
/* Reserved 0x0000128C */
-#define PATUISR_ADDR 0x00001290
-#define SATUISR_ADDR 0x00001294
-#define SATUCMD_ADDR 0x00001298
-#define SATUSR_ADDR 0x0000129A
-#define SODWVR_ADDR 0x0000129C
-#define SOUDR_ADDR 0x000012A0
-#define POCCAR_ADDR 0x000012A4
-#define SOCCAR_ADDR 0x000012A8
-#define POCCDR_ADDR 0x000012AC
-#define SOCCDR_ADDR 0x000012B0
-#define PAQCR_ADDR 0x000012B4
-#define SAQCR_ADDR 0x000012B8
-#define PAIMR_ADDR 0x000012BC
-#define SAIMR_ADDR 0x000012C0
+#define PATUISR_ADDR 0x00001290
+#define SATUISR_ADDR 0x00001294
+#define SATUCMD_ADDR 0x00001298
+#define SATUSR_ADDR 0x0000129A
+#define SODWVR_ADDR 0x0000129C
+#define SOUDR_ADDR 0x000012A0
+#define POCCAR_ADDR 0x000012A4
+#define SOCCAR_ADDR 0x000012A8
+#define POCCDR_ADDR 0x000012AC
+#define SOCCDR_ADDR 0x000012B0
+#define PAQCR_ADDR 0x000012B4
+#define SAQCR_ADDR 0x000012B8
+#define PAIMR_ADDR 0x000012BC
+#define SAIMR_ADDR 0x000012C0
/* Reserved 0x000012C4 through 0x000012FF */
/* Messaging Unit 0000 1300H through 0000 130FH */
-#define IMR0_ADDR 0x00001310
-#define IMR1_ADDR 0x00001314
-#define OMR0_ADDR 0x00001318
-#define OMR1_ADDR 0x0000131C
-#define IDR_ADDR 0x00001320
-#define IISR_ADDR 0x00001324
-#define IIMR_ADDR 0x00001328
-#define ODR_ADDR 0x0000132C
-#define OISR_ADDR 0x00001330
-#define OIMR_ADDR 0x00001334
+#define IMR0_ADDR 0x00001310
+#define IMR1_ADDR 0x00001314
+#define OMR0_ADDR 0x00001318
+#define OMR1_ADDR 0x0000131C
+#define IDR_ADDR 0x00001320
+#define IISR_ADDR 0x00001324
+#define IIMR_ADDR 0x00001328
+#define ODR_ADDR 0x0000132C
+#define OISR_ADDR 0x00001330
+#define OIMR_ADDR 0x00001334
/* Reserved 0x00001338 through 0x0000134F */
-#define MUCR_ADDR 0x00001350
-#define QBAR_ADDR 0x00001354
+#define MUCR_ADDR 0x00001350
+#define QBAR_ADDR 0x00001354
/* Reserved 0x00001358 */
/* Reserved 0x0000135C */
-#define IFHPR_ADDR 0x00001360
-#define IFTPR_ADDR 0x00001364
-#define IPHPR_ADDR 0x00001368
-#define IPTPR_ADDR 0x0000136C
-#define OFHPR_ADDR 0x00001370
-#define OFTPR_ADDR 0x00001374
-#define OPHPR_ADDR 0x00001378
-#define OPTPR_ADDR 0x0000137C
-#define IAR_ADDR 0x00001380
+#define IFHPR_ADDR 0x00001360
+#define IFTPR_ADDR 0x00001364
+#define IPHPR_ADDR 0x00001368
+#define IPTPR_ADDR 0x0000136C
+#define OFHPR_ADDR 0x00001370
+#define OFTPR_ADDR 0x00001374
+#define OPHPR_ADDR 0x00001378
+#define OPTPR_ADDR 0x0000137C
+#define IAR_ADDR 0x00001380
/* Reserved 0x00001384 through 0x000013FF */
/* DMA Controller 0000 1400H through 0000 14FFH */
-#define CCR0_ADDR 0x00001400
-#define CSR0_ADDR 0x00001404
+#define CCR0_ADDR 0x00001400
+#define CSR0_ADDR 0x00001404
/* Reserved 0x00001408 */
-#define DAR0_ADDR 0x0000140C
-#define NDAR0_ADDR 0x00001410
-#define PADR0_ADDR 0x00001414
-#define PUADR0_ADDR 0x00001418
-#define LADR0_ADDR 0x0000141C
-#define BCR0_ADDR 0x00001420
-#define DCR0_ADDR 0x00001424
+#define DAR0_ADDR 0x0000140C
+#define NDAR0_ADDR 0x00001410
+#define PADR0_ADDR 0x00001414
+#define PUADR0_ADDR 0x00001418
+#define LADR0_ADDR 0x0000141C
+#define BCR0_ADDR 0x00001420
+#define DCR0_ADDR 0x00001424
/* Reserved 0x00001428 through 0x0000143F */
-#define CCR1_ADDR 0x00001440
-#define CSR1_ADDR 0x00001444
+#define CCR1_ADDR 0x00001440
+#define CSR1_ADDR 0x00001444
/* Reserved 0x00001448 */
-#define DAR1_ADDR 0x0000144C
-#define NDAR1_ADDR 0x00001450
-#define PADR1_ADDR 0x00001454
-#define PUADR1_ADDR 0x00001458
-#define LADR1_ADDR 0x0000145C
-#define BCR1_ADDR 0x00001460
-#define DCR1_ADDR 0x00001464
+#define DAR1_ADDR 0x0000144C
+#define NDAR1_ADDR 0x00001450
+#define PADR1_ADDR 0x00001454
+#define PUADR1_ADDR 0x00001458
+#define LADR1_ADDR 0x0000145C
+#define BCR1_ADDR 0x00001460
+#define DCR1_ADDR 0x00001464
/* Reserved 0x00001468 through 0x0000147F */
-#define CCR2_ADDR 0x00001480
-#define CSR2_ADDR 0x00001484
+#define CCR2_ADDR 0x00001480
+#define CSR2_ADDR 0x00001484
/* Reserved 0x00001488 */
-#define DAR2_ADDR 0x0000148C
-#define NDAR2_ADDR 0x00001490
-#define PADR2_ADDR 0x00001494
-#define PUADR2_ADDR 0x00001498
-#define LADR2_ADDR 0x0000149C
-#define BCR2_ADDR 0x000014A0
-#define DCR2_ADDR 0x000014A4
+#define DAR2_ADDR 0x0000148C
+#define NDAR2_ADDR 0x00001490
+#define PADR2_ADDR 0x00001494
+#define PUADR2_ADDR 0x00001498
+#define LADR2_ADDR 0x0000149C
+#define BCR2_ADDR 0x000014A0
+#define DCR2_ADDR 0x000014A4
/* Reserved 0x000014A8 through 0x000014FF */
/* Memory Controller 0000 1500H through 0000 15FFH */
-#define SDIR_ADDR 0x00001500
-#define SDCR_ADDR 0x00001504
-#define SDBR_ADDR 0x00001508
-#define SBR0_ADDR 0x0000150C
-#define SBR1_ADDR 0x00001510
-#define SDPR0_ADDR 0x00001514
-#define SDPR1_ADDR 0x00001518
-#define SDPR2_ADDR 0x0000151C
-#define SDPR3_ADDR 0x00001520
-#define SDPR4_ADDR 0x00001524
-#define SDPR5_ADDR 0x00001528
-#define SDPR6_ADDR 0x0000152C
-#define SDPR7_ADDR 0x00001530
-#define ECCR_ADDR 0x00001534
-#define ELOG0_ADDR 0x00001538
-#define ELOG1_ADDR 0x0000153C
-#define ECAR0_ADDR 0x00001540
-#define ECAR1_ADDR 0x00001544
-#define ECTST_ADDR 0x00001548
-#define FEBR0_ADDR 0x0000154C
-#define FEBR1_ADDR 0x00001550
-#define FBSR0_ADDR 0x00001554
-#define FBSR1_ADDR 0x00001558
-#define FWSR0_ADDR 0x0000155C
-#define FWSR1_ADDR 0x00001560
-#define MCISR_ADDR 0x00001564
-#define RFR_ADDR 0x00001568
+#define SDIR_ADDR 0x00001500
+#define SDCR_ADDR 0x00001504
+#define SDBR_ADDR 0x00001508
+#define SBR0_ADDR 0x0000150C
+#define SBR1_ADDR 0x00001510
+#define SDPR0_ADDR 0x00001514
+#define SDPR1_ADDR 0x00001518
+#define SDPR2_ADDR 0x0000151C
+#define SDPR3_ADDR 0x00001520
+#define SDPR4_ADDR 0x00001524
+#define SDPR5_ADDR 0x00001528
+#define SDPR6_ADDR 0x0000152C
+#define SDPR7_ADDR 0x00001530
+#define ECCR_ADDR 0x00001534
+#define ELOG0_ADDR 0x00001538
+#define ELOG1_ADDR 0x0000153C
+#define ECAR0_ADDR 0x00001540
+#define ECAR1_ADDR 0x00001544
+#define ECTST_ADDR 0x00001548
+#define FEBR0_ADDR 0x0000154C
+#define FEBR1_ADDR 0x00001550
+#define FBSR0_ADDR 0x00001554
+#define FBSR1_ADDR 0x00001558
+#define FWSR0_ADDR 0x0000155C
+#define FWSR1_ADDR 0x00001560
+#define MCISR_ADDR 0x00001564
+#define RFR_ADDR 0x00001568
/* Reserved 0x0000156C through 0x000015FF */
/* Arbitration Control Unit 0000 1600H through 0000 167FH */
-#define IACR_ADDR 0x00001600
-#define MLTR_ADDR 0x00001604
-#define MTTR_ADDR 0x00001608
+#define IACR_ADDR 0x00001600
+#define MLTR_ADDR 0x00001604
+#define MTTR_ADDR 0x00001608
/* Reserved 0x0000160C through 0x0000163F */
/* Bus Interface Control Unit 0000 1640H through 0000 167FH */
-#define BIUCR_ADDR 0x00001640
-#define BIUISR_ADDR 0x00001644
+#define BIUCR_ADDR 0x00001640
+#define BIUISR_ADDR 0x00001644
/* Reserved 0x00001648 through 0x0000167F */
/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
-#define ICR_ADDR 0x00001680
-#define ISR_ADDR 0x00001684
-#define ISAR_ADDR 0x00001688
-#define IDBR_ADDR 0x0000168C
-#define ICCR_ADDR 0x00001690
-#define IBMR_ADDR 0x00001694
+#define ICR_ADDR 0x00001680
+#define ISR_ADDR 0x00001684
+#define ISAR_ADDR 0x00001688
+#define IDBR_ADDR 0x0000168C
+#define ICCR_ADDR 0x00001690
+#define IBMR_ADDR 0x00001694
/* Reserved 0x00001698 through 0x000016FF */
/* PCI And Peripheral Interrupt Controller 0000 1700H through 0000 17FFH */
-#define NISR_ADDR 0x00001700
-#define X7ISR_ADDR 0x00001704
-#define X6ISR_ADDR 0x00001708
-#define PDIDR_ADDR 0x00001710 /* EAS inconsistent */
+#define NISR_ADDR 0x00001700
+#define X7ISR_ADDR 0x00001704
+#define X6ISR_ADDR 0x00001708
+#define PDIDR_ADDR 0x00001710 /* EAS inconsistent */
/* Reserved 0x00001714 through 0x0000177F */
/* Application Accelerator Unit 0000 1800H through 0000 18FFH */
-#define ACR_ADDR 0x00001800
-#define ASR_ADDR 0x00001804
-#define ADAR_ADDR 0x00001808
-#define ANDAR_ADDR 0x0000180C
-#define SAR1_ADDR 0x00001810
-#define SAR2_ADDR 0x00001814
-#define SAR3_ADDR 0x00001818
-#define SAR4_ADDR 0x0000181C
-#define DAR_ADDR 0x00001820
-#define ABCR_ADDR 0x00001824
-#define ADCR_ADDR 0x00001828
-#define SAR5_ADDR 0x0000182C
-#define SAR6_ADDR 0x00001830
-#define SAR7_ADDR 0x00001834
-#define SAR8_ADDR 0x00001838
+#define ACR_ADDR 0x00001800
+#define ASR_ADDR 0x00001804
+#define ADAR_ADDR 0x00001808
+#define ANDAR_ADDR 0x0000180C
+#define SAR1_ADDR 0x00001810
+#define SAR2_ADDR 0x00001814
+#define SAR3_ADDR 0x00001818
+#define SAR4_ADDR 0x0000181C
+#define DAR_ADDR 0x00001820
+#define ABCR_ADDR 0x00001824
+#define ADCR_ADDR 0x00001828
+#define SAR5_ADDR 0x0000182C
+#define SAR6_ADDR 0x00001830
+#define SAR7_ADDR 0x00001834
+#define SAR8_ADDR 0x00001838
/* Reserved 0x0000183C through 0x000018FF */
#define X6ISR_REG ((volatile cyg_uint32 *)X6ISR_ADDR)
# define X6ISR_DIP0 0x01
@@ -528,69 +528,88 @@ extern void hal_plf_hardware_init(void);
# define NISR_DMA2 0x80
# define NISR_MU 0x100
# define NISR_AAU 0x400
# define NISR_BIU 0x800
-#define PIRSR_REG ((volatile cyg_uint32 *)PIRSR_ADDR)
-#define IISR_REG ((volatile cyg_uint32 *)IISR_ADDR)
-#define IIMR_REG ((volatile cyg_uint32 *)IIMR_ADDR)
-#define OISR_REG ((volatile cyg_uint32 *)OISR_ADDR)
-#define OIMR_REG ((volatile cyg_uint32 *)OIMR_ADDR)
-#define EMISR_REG ((volatile cyg_uint32 *)EMISR_ADDR)
-#define ISR_REG ((volatile cyg_uint32 *)ISR_ADDR)
-#define GTMR_REG ((volatile cyg_uint32 *)GTMR_ADDR)
-#define ESR_REG ((volatile cyg_uint32 *)ESR_ADDR)
-#define ADCR_REG ((volatile cyg_uint32 *)ADCR_ADDR)
-#define ICR_REG ((volatile cyg_uint32 *)ICR_ADDR)
-#define ATUCR_REG ((volatile cyg_uint32 *)ATUCR_ADDR)
-
-#define DCR0_REG ((volatile cyg_uint32 *)DCR0_ADDR)
-#define DCR1_REG ((volatile cyg_uint32 *)DCR1_ADDR)
-#define DCR2_REG ((volatile cyg_uint32 *)DCR2_ADDR)
-
-#define ECCR_REG ((volatile cyg_uint32 *)ECCR_ADDR)
-#define MCISR_REG ((volatile cyg_uint32 *)MCISR_ADDR)
-#define ELOG0_REG ((volatile cyg_uint32 *)ELOG0_ADDR)
-#define ELOG1_REG ((volatile cyg_uint32 *)ELOG1_ADDR)
-#define ECAR0_REG ((volatile cyg_uint32 *)ECAR0_ADDR)
-#define ECAR1_REG ((volatile cyg_uint32 *)ECAR1_ADDR)
-
-#define PATUISR_REG ((volatile cyg_uint32 *)PATUISR_ADDR)
-#define SATUISR_REG ((volatile cyg_uint32 *)SATUISR_ADDR)
-#define PBISR_REG ((volatile cyg_uint32 *)PBISR_ADDR)
-#define SBISR_REG ((volatile cyg_uint32 *)SBISR_ADDR)
-#define CSR0_REG ((volatile cyg_uint32 *)CSR0_ADDR)
-#define CSR1_REG ((volatile cyg_uint32 *)CSR1_ADDR)
-#define CSR2_REG ((volatile cyg_uint32 *)CSR2_ADDR)
-#define IISR_REG ((volatile cyg_uint32 *)IISR_ADDR)
-#define ASR_REG ((volatile cyg_uint32 *)ASR_ADDR)
-#define BIUISR_REG ((volatile cyg_uint32 *)BIUISR_ADDR)
-
-#define PATUSR_REG ((volatile cyg_uint16 *)PATUSR_ADDR)
-#define SATUSR_REG ((volatile cyg_uint16 *)SATUSR_ADDR)
-#define PSR_REG ((volatile cyg_uint16 *)PSR_ADDR)
-#define SSR_REG ((volatile cyg_uint16 *)SSR_ADDR)
+#define PIRSR_REG REG32(0,PIRSR_ADDR)
+#define IISR_REG REG32(0,IISR_ADDR)
+#define IIMR_REG REG32(0,IIMR_ADDR)
+#define OISR_REG REG32(0,OISR_ADDR)
+#define OIMR_REG REG32(0,OIMR_ADDR)
+#define EMISR_REG REG32(0,EMISR_ADDR)
+#define ISR_REG REG32(0,ISR_ADDR)
+#define GTMR_REG REG32(0,GTMR_ADDR)
+#define ESR_REG REG32(0,ESR_ADDR)
+#define ADCR_REG REG32(0,ADCR_ADDR)
+#define ICR_REG REG32(0,ICR_ADDR)
+#define ATUCR_REG REG32(0,ATUCR_ADDR)
+
+#define DCR0_REG REG32(0,DCR0_ADDR)
+#define DCR1_REG REG32(0,DCR1_ADDR)
+#define DCR2_REG REG32(0,DCR2_ADDR)
+
+#define ECCR_REG REG32(0,ECCR_ADDR)
+#define MCISR_REG REG32(0,MCISR_ADDR)
+#define ELOG0_REG REG32(0,ELOG0_ADDR)
+#define ELOG1_REG REG32(0,ELOG1_ADDR)
+#define ECAR0_REG REG32(0,ECAR0_ADDR)
+#define ECAR1_REG REG32(0,ECAR1_ADDR)
+
+#define PATUISR_REG REG32(0,PATUISR_ADDR)
+#define SATUISR_REG REG32(0,SATUISR_ADDR)
+#define PBISR_REG REG32(0,PBISR_ADDR)
+#define SBISR_REG REG32(0,SBISR_ADDR)
+#define CSR0_REG REG32(0,CSR0_ADDR)
+#define CSR1_REG REG32(0,CSR1_ADDR)
+#define CSR2_REG REG32(0,CSR2_ADDR)
+#define IISR_REG REG32(0,IISR_ADDR)
+#define ASR_REG REG32(0,ASR_ADDR)
+#define BIUISR_REG REG32(0,BIUISR_ADDR)
+
+#define PATUSR_REG REG16(0,PATUSR_ADDR)
+#define SATUSR_REG REG16(0,SATUSR_ADDR)
+#define PSR_REG REG16(0,PSR_ADDR)
+#define SSR_REG REG16(0,SSR_ADDR)
+
+#define PCR_REG REG16(0,PCR_ADDR)
+#define PBNR_REG REG8(0,PBNR_ADDR)
+#define SBNR_REG REG8(0,SBNR_ADDR)
+#define SUBBNR_REG REG8(0,SUBBNR_ADDR)
+#define BCR_REG REG16(0,BCR_ADDR)
+#define PATUCMD_REG REG32(0,PATUCMD_ADDR)
+#define PIABAR_REG REG32(0,PIABAR_ADDR)
+#define SIABAR_REG REG32(0,SIABAR_ADDR)
+#define SIALR_REG REG32(0,SIALR_ADDR)
+#define SIATVR_REG REG32(0,SIATVR_ADDR)
+#define POMWVR_REG REG32(0,POMWVR_ADDR)
+#define POIOWVR_REG REG32(0,POIOWVR_ADDR)
+#define PODWVR_REG REG32(0,PODWVR_ADDR)
+#define SOMWVR_REG REG32(0,SOMWVR_ADDR)
+#define SOIOWVR_REG REG32(0,SOIOWVR_ADDR)
+#define SATUCMD_REG REG16(0,SATUCMD_ADDR)
+#define SODWVR_REG REG32(0,SODWVR_ADDR)
+
#define MEMBASE_DRAM 0xa0000000
/* primary PCI bus definitions */
-#define PRIMARY_BUS_NUM 0
-#define PRIMARY_MEM_BASE 0x80000000
-#define PRIMARY_DAC_BASE 0x84000000
-#define PRIMARY_IO_BASE 0x90000000
-#define PRIMARY_MEM_LIMIT 0x83ffffff
-#define PRIMARY_DAC_LIMIT 0x87ffffff
-#define PRIMARY_IO_LIMIT 0x9000ffff
+#define PRIMARY_BUS_NUM 0
+#define PRIMARY_MEM_BASE 0x80000000
+#define PRIMARY_DAC_BASE 0x84000000
+#define PRIMARY_IO_BASE 0x90000000
+#define PRIMARY_MEM_LIMIT 0x83ffffff
+#define PRIMARY_DAC_LIMIT 0x87ffffff
+#define PRIMARY_IO_LIMIT 0x9000ffff
/* secondary PCI bus definitions */
-#define SECONDARY_BUS_NUM 1
-#define SECONDARY_MEM_BASE 0x88000000
-#define SECONDARY_DAC_BASE 0x8c000000
-#define SECONDARY_IO_BASE 0x90010000
-#define SECONDARY_MEM_LIMIT 0x8bffffff
-#define SECONDARY_DAC_LIMIT 0x8fffffff
-#define SECONDARY_IO_LIMIT 0x9001ffff
+#define SECONDARY_BUS_NUM 1
+#define SECONDARY_MEM_BASE 0x88000000
+#define SECONDARY_DAC_BASE 0x8c000000
+#define SECONDARY_IO_BASE 0x90010000
+#define SECONDARY_MEM_LIMIT 0x8bffffff
+#define SECONDARY_DAC_LIMIT 0x8fffffff
+#define SECONDARY_IO_LIMIT 0x9001ffff
#ifndef __ASSEMBLER__
extern unsigned int _80312_EMISR; // Only valid for PEC ISR
#endif
@@ -606,34 +625,34 @@ extern unsigned int _80312_EMISR; // On
// reg_dram_size -- register holding size of SDRAM
// vendor_id -- PCI vendor ID
// device_id -- PCI device ID
.macro IOP310_EARLY_PCI_SETUP reg0, reg1, reg_dram_size, vendor_id, device_id
- // Setup vendor/device ID for 80312
- ldr \reg0, =ASVIR_ADDR
- ldr \reg1, =\vendor_id
- strh \reg1, [\reg0]
- ldr \reg0, =ASIR_ADDR
- ldr \reg1, =\device_id
- strh \reg1, [\reg0]
- // Make all secondary bus devices private
- ldr \reg0, =SISR_ADDR
- ldr \reg1, =0x03FF
- strh \reg1, [\reg0]
- // Setup primary inbound window into SDRAM
- ldr \reg0, =PIATVR_ADDR
- mov \reg1, #0xa0000000
- str \reg1, [\reg0]
- ldr \reg0, =PIALR_ADDR
- sub \reg1, \reg_dram_size, #1 // dram_size - 1
- mvn \reg1, \reg1 // 1s complement
- str \reg1, [\reg0]
+ // Setup vendor/device ID for 80312
+ ldr \reg0, =ASVIR_ADDR
+ ldr \reg1, =\vendor_id
+ strh \reg1, [\reg0]
+ ldr \reg0, =ASIR_ADDR
+ ldr \reg1, =\device_id
+ strh \reg1, [\reg0]
+ // Make all secondary bus devices private
+ ldr \reg0, =SISR_ADDR
+ ldr \reg1, =0x03FF
+ strh \reg1, [\reg0]
+ // Setup primary inbound window into SDRAM
+ ldr \reg0, =PIATVR_ADDR
+ mov \reg1, #0xa0000000
+ str \reg1, [\reg0]
+ ldr \reg0, =PIALR_ADDR
+ sub \reg1, \reg_dram_size, #1 // dram_size - 1
+ mvn \reg1, \reg1 // 1s complement
+ str \reg1, [\reg0]
#ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY
- ldr \reg0, =EBCR_ADDR
- mov \reg1, #0x0008
- strh \reg1, [\reg0]
-#endif
+ ldr \reg0, =EBCR_ADDR
+ mov \reg1, #0x0008
+ strh \reg1, [\reg0]
+#endif
.endm
#endif // __ASSEMBLER__
// ------------------------------------------------------------------------
@@ -646,11 +665,11 @@ extern unsigned int _80312_EMISR; // On
" b 99f\n" \
" .p2align 5\n" \
"99:\n" \
" mcr p15,0,r0,c1,c0,0\n" \
" mrc p15,0,r0,c2,c0,0\n" \
- " mov r0,r0\n" \
+ " mov r0,r0\n" \
" sub pc,pc,#4\n" \
" mov pc," #__paddr__ "\n"
/*---------------------------------------------------------------------------*/
Index: hal/arm/xscale/iop310/current/include/var_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/include/var_io.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 var_io.h
--- hal/arm/xscale/iop310/current/include/var_io.h 12 Nov 2002 17:38:50 -0000 1.1
+++ hal/arm/xscale/iop310/current/include/var_io.h 22 Jan 2003 13:29:54 -0000
@@ -147,77 +147,10 @@ externC void cyg_hal_plf_pci_init(void);
#ifndef HAL_PCI_PHYSICAL_MEMORY_BASE
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0x00000000
#define HAL_PCI_PHYSICAL_IO_BASE 0x00000000
#endif
-// Translate the PCI interrupt requested by the device (INTA#, INTB#,
-// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
-#ifndef HAL_PCI_TRANSLATE_INTERRUPT
-#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
- CYG_MACRO_START \
- cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
- cyg_uint32 __fn = CYG_PCI_DEV_GET_FN(__devfn); \
- __valid = false; \
- if (__bus == (*((cyg_uint8 *)SBNR_ADDR) + 1) && __dev == 0 && __fn == 0) {\
- __vec = CYGNUM_HAL_INTERRUPT_ETHERNET; \
- __valid = true; \
- } else { \
- cyg_uint8 __req; \
- HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
- switch (__dev % 4) { \
- case 0: \
- switch(__req) { \
- case 1: /* INTA */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTA; __valid=true; break; \
- case 2: /* INTB */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTB; __valid=true; break; \
- case 3: /* INTC */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTC; __valid=true; break; \
- case 4: /* INTD */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTD; __valid=true; break; \
- } \
- break; \
- case 1: \
- switch(__req) { \
- case 1: /* INTA */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTB; __valid=true; break; \
- case 2: /* INTB */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTC; __valid=true; break; \
- case 3: /* INTC */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTD; __valid=true; break; \
- case 4: /* INTD */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTA; __valid=true; break; \
- } \
- break; \
- case 2: \
- switch(__req) { \
- case 1: /* INTA */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTC; __valid=true; break; \
- case 2: /* INTB */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTD; __valid=true; break; \
- case 3: /* INTC */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTA; __valid=true; break; \
- case 4: /* INTD */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTB; __valid=true; break; \
- } \
- break; \
- case 3: \
- switch(__req) { \
- case 1: /* INTA */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTD; __valid=true; break; \
- case 2: /* INTB */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTA; __valid=true; break; \
- case 3: /* INTC */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTB; __valid=true; break; \
- case 4: /* INTD */ \
- __vec=CYGNUM_HAL_INTERRUPT_PCI_S_INTC; __valid=true; break; \
- } \
- break; \
- } \
- } \
- CYG_MACRO_END
-#endif
// Some of SDRAM is aliased as uncached memory for drivers.
#ifndef CYGARC_UNCACHED_ADDRESS
#define CYGARC_UNCACHED_ADDRESS(_x_) \
(((((unsigned long)(_x_)) >> 28)==0xA) ? (((unsigned long)(_x_))|0x40000000) : (unsigned long)(_x_))
Index: hal/arm/xscale/iop310/current/src/iop310_pci.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iop310/current/src/iop310_pci.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 iop310_pci.c
--- hal/arm/xscale/iop310/current/src/iop310_pci.c 13 Nov 2002 15:43:21 -0000 1.2
+++ hal/arm/xscale/iop310/current/src/iop310_pci.c 22 Jan 2003 13:29:55 -0000
@@ -80,128 +80,128 @@ void cyg_hal_plf_pci_init(void)
// ************ bridge registers *******************
if (iop310_is_host()) {
// set the primary inbound ATU base address to the start of DRAM
- *(cyg_uint32 *)PIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000;
+ *PIABAR_REG = MEMBASE_DRAM & 0xFFFFF000;
// ********* Set Primary Outbound Windows *********
// Note: The primary outbound ATU memory window value register
// and i/o window value registers are defaulted to 0
// set the primary outbound windows to directly map Local - PCI
// requests
// outbound memory window
- *(cyg_uint32 *)POMWVR_ADDR = PRIMARY_MEM_BASE;
+ *POMWVR_REG = PRIMARY_MEM_BASE;
// outbound DAC Window
- *(cyg_uint32 *)PODWVR_ADDR = PRIMARY_DAC_BASE;
+ *PODWVR_REG = PRIMARY_DAC_BASE;
// outbound I/O window
- *(cyg_uint32 *)POIOWVR_ADDR = PRIMARY_IO_BASE;
+ *POIOWVR_REG = PRIMARY_IO_BASE;
// set the bridge command register
- *(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
+ *PCR_REG = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
// set the subordinate bus number to 0xFF
- *(cyg_uint8 *)SUBBNR_ADDR = 0xFF;
+ *SUBBNR_REG = 0xFF;
// set the secondary bus number to 1
- *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
- *(cyg_uint16 *)BCR_ADDR = 0x0823;
+ *SBNR_REG = SECONDARY_BUS_NUM;
+ *BCR_REG = 0x0823;
// set the primary bus number to 0
- *(cyg_uint8 *)PBNR_ADDR = PRIMARY_BUS_NUM;
+ *PBNR_REG = PRIMARY_BUS_NUM;
// allow primary ATU to act as a bus master, respond to PCI
// memory accesses, assert P_SERR#, and enable parity checking
- *(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
+ *PATUCMD_REG = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
} else {
#ifdef CYGSEM_HAL_ARM_IOP310_CLEAR_PCI_RETRY
// Wait for PC BIOS to initialize bus number
int i;
for (i = 0; i < 15000; i++) {
- if (*((volatile cyg_uint16 *)PCR_ADDR) & CYG_PCI_CFG_COMMAND_MEMORY)
+ if (*PCR_REG & CYG_PCI_CFG_COMMAND_MEMORY)
break;
hal_delay_us(1000); // 1msec
}
for (i = 0; i < 15000; i++) {
- if (*((volatile cyg_uint8 *)SBNR_ADDR) != 0)
+ if (*SBNR_REG != 0)
break;
hal_delay_us(1000); // 1msec
}
#endif
- if (*((volatile cyg_uint8 *)SBNR_ADDR) == 0)
- *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM;
- if (*((volatile cyg_uint8 *)SUBBNR_ADDR) == 0)
- *(cyg_uint8 *)SUBBNR_ADDR = 0xFF;
- if (*((volatile cyg_uint16 *)BCR_ADDR) == 0)
- *(cyg_uint16 *)BCR_ADDR = 0x0823;
- if (*((volatile cyg_uint16 *)PCR_ADDR) == 0)
- *(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
- if (*((volatile cyg_uint16 *)PATUCMD_ADDR) == 0)
- *(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
+ if (*SBNR_REG == 0)
+ *SBNR_REG = SECONDARY_BUS_NUM;
+ if (*SUBBNR_REG == 0)
+ *SUBBNR_REG = 0xFF;
+ if (*BCR_REG == 0)
+ *BCR_REG = 0x0823;
+ if (*PCR_REG == 0)
+ *PCR_REG = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
+ if (*PATUCMD_REG == 0)
+ *PATUCMD_REG = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
}
// Initialize Secondary PCI bus (bus 1)
- *(volatile cyg_uint16 *)BCR_ADDR |= 0x40; // reset secondary bus
+ *BCR_REG |= 0x40; // reset secondary bus
hal_delay_us(10 * 1000); // 10ms enough??
- *(volatile cyg_uint16 *)BCR_ADDR &= ~0x40; // release reset
+ *BCR_REG &= ~0x40; // release reset
// ******** Secondary Inbound ATU ***********
// set secondary inbound ATU translate value register to point to base
// of local DRAM
- *(cyg_uint32 *)SIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC;
+ *SIATVR_REG = MEMBASE_DRAM & 0xFFFFFFFC;
// set secondary inbound ATU base address to start of DRAM
- *(cyg_uint32 *)SIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000;
+ *SIABAR_REG = MEMBASE_DRAM & 0xFFFFF000;
// always allow secondary pci access to all memory (even with A0 step)
limit_reg = (0xFFFFFFFF - (hal_dram_size - 1)) & 0xFFFFFFF0;
- *(cyg_uint32 *)SIALR_ADDR = limit_reg;
+ *SIALR_REG = limit_reg;
// ********** Set Secondary Outbound Windows ***********
// Note: The secondary outbound ATU memory window value register
// and i/o window value registers are defaulted to 0
// set the secondary outbound window to directly map Local - PCI requests
// outbound memory window
- *(cyg_uint32 *)SOMWVR_ADDR = SECONDARY_MEM_BASE;
+ *SOMWVR_REG = SECONDARY_MEM_BASE;
// outbound DAC Window
- *(cyg_uint32 *)SODWVR_ADDR = SECONDARY_DAC_BASE;
+ *SODWVR_REG = SECONDARY_DAC_BASE;
// outbound I/O window
- *(cyg_uint32 *)SOIOWVR_ADDR = SECONDARY_IO_BASE;
+ *SOIOWVR_REG = SECONDARY_IO_BASE;
// allow secondary ATU to act as a bus master, respond to PCI memory
// accesses, and assert S_SERR#
- *(cyg_uint16 *)SATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \
- CYG_PCI_CFG_COMMAND_PARITY | \
- CYG_PCI_CFG_COMMAND_MASTER | \
- CYG_PCI_CFG_COMMAND_MEMORY);
+ *SATUCMD_REG = (CYG_PCI_CFG_COMMAND_SERR | \
+ CYG_PCI_CFG_COMMAND_PARITY | \
+ CYG_PCI_CFG_COMMAND_MASTER | \
+ CYG_PCI_CFG_COMMAND_MEMORY);
// enable primary and secondary outbound ATUs, BIST, and primary bus
// direct addressing
- *(cyg_uint32 *)ATUCR_ADDR = 0x00000006;
+ *ATUCR_REG = 0x00000006;
- pbus_nr = *(cyg_uint8 *)PBNR_ADDR;
- sbus_nr = *(cyg_uint8 *)SBNR_ADDR;
+ pbus_nr = *PBNR_REG;
+ sbus_nr = *SBNR_REG;
// Now initialize the PCI busses.
// Next assignable bus number. Yavapai primary bus is fixed as
// bus zero and yavapai secondary is fixed as bus 1.
@@ -214,30 +214,53 @@ void cyg_hal_plf_pci_init(void)
// the Primary side
pbus_nr = 0;
sbus_nr = 0xff;
// set the primary bus number to 0
- *(cyg_uint8 *)PBNR_ADDR = 0;
+ *PBNR_REG = 0;
next_bus = 1;
// Initialize Primary PCI bus (bus 0)
cyg_pci_set_memory_base(PRIMARY_MEM_BASE);
cyg_pci_set_io_base(PRIMARY_IO_BASE);
cyg_pci_configure_bus(0, &next_bus);
// set the secondary bus number to next available number
- *(cyg_uint8 *)SBNR_ADDR = sbus_nr = next_bus;
+ *SBNR_REG = sbus_nr = next_bus;
- pbus_nr = *(cyg_uint8 *)PBNR_ADDR;
+ pbus_nr = *PBNR_REG;
next_bus = sbus_nr + 1;
}
// Initialize Secondary PCI bus (bus 1)
cyg_pci_set_memory_base(SECONDARY_MEM_BASE);
cyg_pci_set_io_base(SECONDARY_IO_BASE);
+ subbus_nr = 0xFF;
cyg_pci_configure_bus(sbus_nr, &next_bus);
- *(cyg_uint8 *)SUBBNR_ADDR = subbus_nr = next_bus - 1;
+ *SUBBNR_REG = subbus_nr = next_bus - 1;
+
+
+ if (0){
+ cyg_uint8 devfn;
+ cyg_pci_device_id devid;
+ cyg_pci_device dev_info;
+
+ diag_printf("pbus[%d] sbus[%d] subbus[%d]\n", pbus_nr, sbus_nr, subbus_nr);
+
+ devid = CYG_PCI_DEV_MAKE_ID(sbus_nr, 0) | CYG_PCI_NULL_DEVFN;
+ while (cyg_pci_find_next(devid, &devid)) {
+ devfn = CYG_PCI_DEV_GET_DEVFN(devid);
+ cyg_pci_get_device_info(devid, &dev_info);
+
+ diag_printf("\n");
+ diag_printf(" Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
+ diag_printf(" PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
+ diag_printf(" PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
+ diag_printf(" Vendor Id : 0x%08X\n", dev_info.vendor);
+ diag_printf(" Device Id : 0x%08X\n", dev_info.device);
+ }
+ }
}
// Use "naked" attribute to suppress C prologue/epilogue
static void __attribute__ ((naked)) __pci_abort_handler(void)
{
@@ -248,20 +271,20 @@ static cyg_uint32 orig_abort_vec;
static inline cyg_uint32 *pci_config_setup(cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
- cyg_uint32 *pdata, *paddr;
+ volatile cyg_uint32 *pdata, *paddr;
cyg_uint32 dev = CYG_PCI_DEV_GET_DEV(devfn);
cyg_uint32 fn = CYG_PCI_DEV_GET_FN(devfn);
if (bus < sbus_nr || bus > subbus_nr) {
- paddr = (cyg_uint32 *)POCCAR_ADDR;
- pdata = (cyg_uint32 *)POCCDR_ADDR;
+ paddr = (volatile cyg_uint32 *)POCCAR_ADDR;
+ pdata = (volatile cyg_uint32 *)POCCDR_ADDR;
} else {
- paddr = (cyg_uint32 *)SOCCAR_ADDR;
- pdata = (cyg_uint32 *)SOCCDR_ADDR;
+ paddr = (volatile cyg_uint32 *)SOCCAR_ADDR;
+ pdata = (volatile cyg_uint32 *)SOCCDR_ADDR;
}
/* Offsets must be dword-aligned */
offset &= ~3;
@@ -282,45 +305,45 @@ static inline cyg_uint32 *pci_config_set
static inline int pci_config_cleanup(cyg_uint32 bus)
{
cyg_uint32 status = 0, err = 0;
if (bus < sbus_nr || bus > subbus_nr) {
- status = *(cyg_uint16 *) PATUSR_ADDR;
+ status = *PATUSR_REG;
if ((status & 0xF900) != 0) {
err = 1;
- *(cyg_uint16 *)PATUSR_ADDR = status & 0xF980;
+ *PATUSR_REG = status & 0xF980;
}
- status = *(cyg_uint16 *) PSR_ADDR;
+ status = *PSR_REG;
if ((status & 0xF900) != 0) {
err = 1;
- *(cyg_uint16 *)PSR_ADDR = status & 0xF980;
+ *PSR_REG = status & 0xF980;
}
- status = *(cyg_uint32 *) PATUISR_ADDR;
+ status = *PATUISR_REG;
if ((status & 0x79F) != 0) {
err = 1;
- *(cyg_uint32 *) PATUISR_ADDR = status & 0x79f;
+ *PATUISR_REG = status & 0x79f;
}
- status = *(cyg_uint32 *) PBISR_ADDR;
+ status = *PBISR_REG;
if ((status & 0x3F) != 0) {
err = 1;
- *(cyg_uint32 *) PBISR_ADDR = status & 0x3F;
+ *PBISR_REG = status & 0x3F;
}
} else {
- status = *(cyg_uint16 *) SATUSR_ADDR;
+ status = *SATUSR_REG;
if ((status & 0xF900) != 0) {
err = 1;
- *(cyg_uint16 *) SATUSR_ADDR = status & 0xF900;
+ *SATUSR_REG = status & 0xF900;
}
- status = *(cyg_uint16 *) SSR_ADDR;
+ status = *SSR_REG;
if ((status & 0xF900) != 0) {
err = 1;
- *(cyg_uint16 *) SSR_ADDR = status & 0xF980;
+ *SSR_REG = status & 0xF980;
}
- status = *(cyg_uint32 *) SATUISR_ADDR;
+ status = *SATUISR_REG;
if ((status & 0x69F) != 0) {
err = 1;
- *(cyg_uint32 *) SATUISR_ADDR = status & 0x69F;
+ *SATUISR_REG = status & 0x69F;
}
}
((volatile unsigned *)0x20)[4] = orig_abort_vec;
HAL_ICACHE_SYNC();
Index: hal/arm/xscale/iq80310/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/ChangeLog,v
retrieving revision 1.2
diff -u -p -5 -r1.2 ChangeLog
--- hal/arm/xscale/iq80310/current/ChangeLog 13 Nov 2002 15:43:21 -0000 1.2
+++ hal/arm/xscale/iq80310/current/ChangeLog 22 Jan 2003 13:29:55 -0000
@@ -1,5 +1,13 @@
+2003-01-22 Mark Salter <msalter@redhat.com>
+
+ * src/diag/diag.c: Don't define DEFINE_VARS.
+ * src/diag/pci_serv.c: Remove pci_int_handlers decl.
+ * src/diag/iq80310.h: Remove cmd_stat declaration.
+ * src/diag/flash.c: Declare cmd_stat.
+ * include/plf_io.h: Remove unused duplicate code.
+
2002-11-13 Mark Salter <msalter@redhat.com>
* misc/redboot_RAM.ecm: Remove CYGPKG_IO_SERIAL_ARM_XSCALE_IQ80310.
* misc/redboot_RAMA.ecm: Ditto.
* misc/redboot_ROM.ecm: Ditto
Index: hal/arm/xscale/iq80310/current/include/plf_io.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/include/plf_io.h,v
retrieving revision 1.1
diff -u -p -5 -r1.1 plf_io.h
--- hal/arm/xscale/iq80310/current/include/plf_io.h 12 Nov 2002 17:38:51 -0000 1.1
+++ hal/arm/xscale/iq80310/current/include/plf_io.h 22 Jan 2003 13:29:55 -0000
@@ -9,11 +9,11 @@
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
@@ -53,103 +53,18 @@
//
//####DESCRIPTIONEND####
//
//=============================================================================
-#include <pkgconf/hal_arm_xscale_iop310.h>
-
-#include <cyg/hal/hal_iop310.h>
-
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_platform_ints.h> // Interrupt vectors
-
-extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset);
-extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset);
-extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset);
-extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset,
- cyg_uint32 val);
-extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset,
- cyg_uint16 val);
-extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
- cyg_uint32 devfn,
- cyg_uint32 offset,
- cyg_uint8 val);
-
-/* primary PCI bus definitions */
-#define PRIMARY_BUS_NUM 0
-#define PRIMARY_MEM_BASE 0x80000000
-#define PRIMARY_DAC_BASE 0x84000000
-#define PRIMARY_IO_BASE 0x90000000
-#define PRIMARY_MEM_LIMIT 0x83ffffff
-#define PRIMARY_DAC_LIMIT 0x87ffffff
-#define PRIMARY_IO_LIMIT 0x9000ffff
-
-
-/* secondary PCI bus definitions */
-#define SECONDARY_BUS_NUM 1
-#define SECONDARY_MEM_BASE 0x88000000
-#define SECONDARY_DAC_BASE 0x8c000000
-#define SECONDARY_IO_BASE 0x90010000
-#define SECONDARY_MEM_LIMIT 0x8bffffff
-#define SECONDARY_DAC_LIMIT 0x8fffffff
-#define SECONDARY_IO_LIMIT 0x9001ffff
-
-// Initialize the PCI bus.
-externC void cyg_hal_plf_pci_init(void);
-#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
-
-// Read a value from the PCI configuration space of the appropriate
-// size at an address composed from the bus, devfn and offset.
-#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
- __val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
-
-#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
- __val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
-
-#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
- __val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
-
-// Write a value to the PCI configuration space of the appropriate
-// size at an address composed from the bus, devfn and offset.
-#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
- cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
-
-#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
- cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
-
-#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
- cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
-
-//-----------------------------------------------------------------------------
-// Resources
-
-// Map PCI device resources starting from these addresses in PCI space.
-#define HAL_PCI_ALLOC_BASE_MEMORY (SECONDARY_MEM_BASE)
-#define HAL_PCI_ALLOC_BASE_IO (SECONDARY_IO_BASE)
-
-// This is where the PCI spaces are mapped in the CPU's address space.
-#define HAL_PCI_PHYSICAL_MEMORY_BASE 0x00000000
-#define HAL_PCI_PHYSICAL_IO_BASE 0x00000000
-
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
cyg_uint32 __fn = CYG_PCI_DEV_GET_FN(__devfn); \
__valid = false; \
- if (__bus == (*((cyg_uint8 *)SBNR_ADDR) + 1) && __dev == 0 && __fn == 0) {\
+ if (__bus == (*SBNR_REG) + 1) && __dev == 0 && __fn == 0) { \
__vec = CYGNUM_HAL_INTERRUPT_ETHERNET; \
__valid = true; \
} else { \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
@@ -203,18 +118,9 @@ externC void cyg_hal_plf_pci_init(void);
} \
break; \
} \
} \
CYG_MACRO_END
-
-// Some of SDRAM is aliased as uncached memory for drivers.
-//#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
-#define CYGARC_UNCACHED_ADDRESS(_x_) \
- (((((unsigned long)(_x_)) >> 28)==0xA) ? (((unsigned long)(_x_))|0x40000000) : (unsigned long)(_x_))
-#define CYGARC_VIRT_TO_BUS(_x_) \
- (((((unsigned long)(_x_)) >> 28)==0xA) ? (unsigned long)(_x_) : (((unsigned long)(_x_))&~0x40000000))
-
-#define CYGARC_PHYSICAL_ADDRESS(x) (x)
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
Index: hal/arm/xscale/iq80310/current/src/diag/diag.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/diag.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 diag.c
--- hal/arm/xscale/iq80310/current/src/diag/diag.c 13 Nov 2002 15:43:22 -0000 1.2
+++ hal/arm/xscale/iq80310/current/src/diag/diag.c 22 Jan 2003 13:29:55 -0000
@@ -6,11 +6,11 @@
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -50,11 +50,10 @@
//
//####DESCRIPTIONEND####
//
//==========================================================================
-#define DEFINE_VARS
#include <redboot.h>
#include <cyg/io/eth/eth_drv.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_cache.h>
Index: hal/arm/xscale/iq80310/current/src/diag/flash.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/flash.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 flash.c
--- hal/arm/xscale/iq80310/current/src/diag/flash.c 13 Nov 2002 15:43:22 -0000 1.2
+++ hal/arm/xscale/iq80310/current/src/diag/flash.c 22 Jan 2003 13:29:55 -0000
@@ -4,11 +4,11 @@
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -130,10 +130,11 @@ typedef unsigned char FLASH_TYPE;
(unsigned)(x)))
unsigned long *flash_buffer = (unsigned long *)0xa1000000;
+int cmd_stat;
extern void _flushICache(void);
extern void _enableICache(void);
extern void _disableICache(void);
extern void _switchMMUpageTables(void);
Index: hal/arm/xscale/iq80310/current/src/diag/iq80310.h
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/iq80310.h,v
retrieving revision 1.2
diff -u -p -5 -r1.2 iq80310.h
--- hal/arm/xscale/iq80310/current/src/diag/iq80310.h 13 Nov 2002 15:43:22 -0000 1.2
+++ hal/arm/xscale/iq80310/current/src/diag/iq80310.h 22 Jan 2003 13:29:56 -0000
@@ -4,11 +4,11 @@
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -195,11 +195,10 @@ typedef void (*VOIDFUNCPTR) (int);
#define COYANOSA_ID_BASE_ADDR 0xA1FFFFFC
/* Definitions for data types and constants used in Flash.c */
typedef unsigned long ADDR;
#define NO_ADDR ((ADDR)0x800000) /* last address of Flash memory + 1 */
-int cmd_stat;
#ifndef ERR
#define ERR -1
#endif
/* Error code Constants */
#define E_EEPROM_ADDR 12
Index: hal/arm/xscale/iq80310/current/src/diag/pci_serv.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80310/current/src/diag/pci_serv.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 pci_serv.c
--- hal/arm/xscale/iq80310/current/src/diag/pci_serv.c 13 Nov 2002 15:43:22 -0000 1.2
+++ hal/arm/xscale/iq80310/current/src/diag/pci_serv.c 22 Jan 2003 13:30:17 -0000
@@ -4,11 +4,11 @@
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -101,13 +101,10 @@ typedef struct
int device;
} INT_HANDLER;
#define NUM_PCI_XINTS 4 /* XINT0 - XINT3 */
#define MAX_PCI_HANDLERS 8 /* maximum handlers per PCI Xint */
-
-/* Table where the interrupt handler addresses are stored. */
-INT_HANDLER pci_int_handlers[4][MAX_PCI_HANDLERS];
extern void hexIn(void);
extern int pci_config_cycle;
extern void _enableFiqIrq(void);
extern void config_ints(void); /* configure interrupts */
Index: hal/arm/xscale/iq80321/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80321/current/ChangeLog,v
retrieving revision 1.9
diff -u -p -5 -r1.9 ChangeLog
--- hal/arm/xscale/iq80321/current/ChangeLog 23 Sep 2002 13:35:46 -0000 1.9
+++ hal/arm/xscale/iq80321/current/ChangeLog 22 Jan 2003 13:30:17 -0000
@@ -1,5 +1,9 @@
+2003-01-22 Mark Salter <msalter@redhat.com>
+
+ * src/diag/diag.c: Don't define DEFINE_VARS.
+
2002-09-23 Mark Salter <msalter@redhat.com>
* include/plf_mmap.h: Remove. Not used.
2002-09-19 Mark Salter <msalter@redhat.com>
Index: hal/arm/xscale/iq80321/current/src/diag/diag.c
===================================================================
RCS file: /cvs/ecos/ecos/packages/hal/arm/xscale/iq80321/current/src/diag/diag.c,v
retrieving revision 1.2
diff -u -p -5 -r1.2 diag.c
--- hal/arm/xscale/iq80321/current/src/diag/diag.c 23 May 2002 23:02:33 -0000 1.2
+++ hal/arm/xscale/iq80321/current/src/diag/diag.c 22 Jan 2003 13:30:17 -0000
@@ -6,11 +6,11 @@
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
-// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
@@ -49,12 +49,10 @@
// This code is part of RedBoot (tm).
//
//####DESCRIPTIONEND####
//
//==========================================================================
-
-#define DEFINE_VARS
#include <redboot.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_cache.h>
#include CYGHWR_MEMORY_LAYOUT_H