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uE250 - Add PCI interrupts
- From: Gary Thomas <gary at mlbassoc dot com>
- To: eCos patches <ecos-patches at sources dot redhat dot com>
- Date: 24 Feb 2003 11:10:37 -0700
- Subject: uE250 - Add PCI interrupts
Index: hal/arm/xscale/pxa2x0/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/pxa2x0/current/ChangeLog,v
retrieving revision 1.2
diff -u -5 -p -b -r1.2 ChangeLog
--- hal/arm/xscale/pxa2x0/current/ChangeLog 21 Feb 2003 18:02:35 -0000 1.2
+++ hal/arm/xscale/pxa2x0/current/ChangeLog 24 Feb 2003 18:00:50 -0000
@@ -1,5 +1,10 @@
+2003-02-24 Gary Thomas <gary at mlbassoc dot com>
+
+ * src/pxa2x0_misc.c (hal_IRQ_handler): Pass 'sources' on to any
+ extended IRQ handler (it may need them).
+
2003-02-20 Gary Thomas <gary at mlbassoc dot com>
* src/pxa2x0_misc.c (hal_hardware_init): Move call to hal_if_init()
into platform code (so it can do I/O). Also, support common CDL
for CACHE startup enables.
Index: hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c,v
retrieving revision 1.2
diff -u -5 -p -b -r1.2 pxa2x0_misc.c
--- hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c 21 Feb 2003 18:02:36 -0000 1.2
+++ hal/arm/xscale/pxa2x0/current/src/pxa2x0_misc.c 24 Feb 2003 15:49:56 -0000
@@ -164,20 +164,20 @@ void hal_delay_us(cyg_int32 usecs)
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
cyg_uint32 sources, index;
+ sources = *PXA2X0_ICIP;
+
#ifdef HAL_EXTENDED_IRQ_HANDLER
// Use platform specific IRQ handler, if defined
// Note: this macro should do a 'return' with the appropriate
// interrupt number if such an extended interrupt exists. The
// assumption is that the line after the macro starts 'normal' processing.
- HAL_EXTENDED_IRQ_HANDLER(index);
+ HAL_EXTENDED_IRQ_HANDLER(sources);
#endif
- sources = *PXA2X0_ICIP;
-
if ( sources & 0xff0000 )
index = 16;
else if ( sources & 0xff00 )
index = 8;
else if ( sources & 0xff )
@@ -256,11 +256,11 @@ void hal_interrupt_unmask(int vector)
}
void hal_interrupt_acknowledge(int vector)
{
-#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+#ifdef HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE
// Use platform specific handling, if defined
// Note: this macro should do a 'return' for "extended" values of 'vector'
// Normal vectors are handled by code subsequent to the macro call.
HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
Index: hal/arm/xscale/uE250/current/ChangeLog
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/ChangeLog,v
retrieving revision 1.1
diff -u -5 -p -b -r1.1 ChangeLog
--- hal/arm/xscale/uE250/current/ChangeLog 21 Feb 2003 18:17:33 -0000 1.1
+++ hal/arm/xscale/uE250/current/ChangeLog 24 Feb 2003 18:02:10 -0000
@@ -1,5 +1,14 @@
+2003-02-24 Gary Thomas <gary at mind dot be>
+
+ * include/plx.h: Clean up unused code.
+
+ * src/uE250_pci.c:
+ * src/uE250_misc.c:
+ * include/plf_io.h:
+ * include/hal_plf_ints.h: Support interrupts via PCI bus.
+
2003-02-04 Gary Thomas <gary at mind dot be>
* src/xilinx-load.c:
* src/uE250_plx.c:
* src/uE250_pci.c:
Index: hal/arm/xscale/uE250/current/include/hal_plf_ints.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/include/hal_plf_ints.h,v
retrieving revision 1.1
diff -u -5 -p -b -r1.1 hal_plf_ints.h
--- hal/arm/xscale/uE250/current/include/hal_plf_ints.h 21 Feb 2003 18:17:33 -0000 1.1
+++ hal/arm/xscale/uE250/current/include/hal_plf_ints.h 24 Feb 2003 17:50:43 -0000
@@ -59,10 +59,66 @@
#include <pkgconf/hal.h>
#include CYGBLD_HAL_VAR_INTS_H
#include <cyg/hal/plf_io.h>
//----------------------------------------------------------------------------
+// Additional interrupts from PCI & Motherboard
+#define _uPCI_BASE_INTERRUPT (96+17)
+
+#define CYGNUM_HAL_INTERRUPT_PCI_INTA (_uPCI_BASE_INTERRUPT+0)
+#define CYGNUM_HAL_INTERRUPT_PCI_INTB (_uPCI_BASE_INTERRUPT+1)
+#define CYGNUM_HAL_INTERRUPT_PCI_INTC (_uPCI_BASE_INTERRUPT+2)
+#define CYGNUM_HAL_INTERRUPT_PCI_INTD (_uPCI_BASE_INTERRUPT+3)
+#define CYGNUM_HAL_INTERRUPT_PXA (_uPCI_BASE_INTERRUPT+4)
+
+#undef CYGNUM_HAL_ISR_MIN
+#undef CYGNUM_HAL_ISR_MAX
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (_uPCI_BASE_INTERRUPT+4)
+
+//----------------------------------------------------------------------------
+// Platform specific interrupt handling
+externC int _uE250_extended_irq(void);
+externC void _uE250_extended_int_mask(int vector);
+externC void _uE250_extended_int_unmask(int vector);
+externC void _uE250_extended_int_acknowledge(int vector);
+externC void _uE250_extended_int_configure(int vector, int level, int up);
+externC void _uE250_extended_int_set_level(int vector, int level);
+
+#define HAL_EXTENDED_IRQ_HANDLER(sources) \
+ if ((sources & (1 << CYGNUM_HAL_INTERRUPT_GPIO1)) != 0) { \
+ int res = _uE250_extended_irq(); \
+ if (res) return res; \
+ };
+#define HAL_EXTENDED_INTERRUPT_MASK(vector) \
+ if (vector >= _uPCI_BASE_INTERRUPT) { \
+ _uE250_extended_int_mask(vector); \
+ return; \
+ }
+#define HAL_EXTENDED_INTERRUPT_UNMASK(vector) \
+ if (vector >= _uPCI_BASE_INTERRUPT) { \
+ _uE250_extended_int_unmask(vector); \
+ return; \
+ }
+#define HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector) \
+ if (vector >= _uPCI_BASE_INTERRUPT) { \
+ _uE250_extended_int_acknowledge(vector); \
+ return; \
+ }
+#define HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up) \
+ if (vector >= _uPCI_BASE_INTERRUPT) { \
+ _uE250_extended_int_configure(vector, level, up); \
+ return; \
+ }
+#define HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level) \
+ if (vector >= _uPCI_BASE_INTERRUPT) { \
+ _uE250_extended_int_set_level(vector, level); \
+ return; \
+ }
+
+
+//----------------------------------------------------------------------------
// Reset.
#undef HAL_PLATFORM_RESET
#define HAL_PLATFORM_RESET() \
CYG_MACRO_START \
cyg_uint32 ctrl; \
Index: hal/arm/xscale/uE250/current/include/plf_io.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/include/plf_io.h,v
retrieving revision 1.1
diff -u -5 -p -b -r1.1 plf_io.h
--- hal/arm/xscale/uE250/current/include/plf_io.h 21 Feb 2003 18:17:33 -0000 1.1
+++ hal/arm/xscale/uE250/current/include/plf_io.h 24 Feb 2003 17:11:36 -0000
@@ -67,11 +67,11 @@
#define PCICTL_MEM_REMAP PCI_CTL_IO(0x0000)
#define PCICTL_IO_REMAP PCI_CTL_IO(0x0004)
#define PCICTL_CONFIG_REMAP PCI_CTL_IO(0x0008)
#define PCICTL_INT_RESET PCI_CTL_IO(0x0010)
#define PCICTL_STATUS_REG PCI_CTL_IO_BYTE(0x0010)
-#define PCICTL_INT_EDGE PCI_CTL_IO(0x0011)
+#define PCICTL_INT_EDGE PCI_CTL_IO_BYTE(0x0011)
#define PCICTL_IRQ_MASK PCI_CTL_IO(0x0014)
#define PCICTL_MISC PCI_CTL_IO(0x001C)
#define PCI_RESET (1 << 0)
#define PCI_WRITEBUF (1 << 1)
@@ -169,11 +169,13 @@ extern void cyg_hal_plf_pci_cfg_write_by
// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
-#define HAL_PCI_TRANSLATE_INTERRUPT(__bus, __devfn, __vector, __valid)
+externC void _uE250_pci_translate_interrupt(int bus, int devfn, int *vector, int *valid);
+#define HAL_PCI_TRANSLATE_INTERRUPT(__bus, __devfn, __vector, __valid) \
+ _uE250_pci_translate_interrupt(__bus, __devfn, &__vector, &__valid)
// Special I/O access functions
externC cyg_uint8 pci_io_read_8(cyg_uint32 address);
externC cyg_uint16 pci_io_read_16(cyg_uint32 address);
externC cyg_uint32 pci_io_read_32(cyg_uint32 address);
Index: hal/arm/xscale/uE250/current/include/plx.h
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/include/plx.h,v
retrieving revision 1.1
diff -u -5 -p -b -r1.1 plx.h
--- hal/arm/xscale/uE250/current/include/plx.h 21 Feb 2003 18:17:33 -0000 1.1
+++ hal/arm/xscale/uE250/current/include/plx.h 21 Feb 2003 18:30:28 -0000
@@ -39,51 +39,31 @@
//
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
-#if 0
-#define PCI_MEM_BASE 0x0C000000
-#define LOCALBUS_MEM_BASE 0x00100000
-#define PCI_MEM_BASE2 0x10000000
-#define DISPLAY_MEM_BASE 0x04000000
-#define PLX_PCI_SLOT 0x5
-#else
#define LOCALBUS_CONFIG_OFFSET 0x0
#define LOCALBUS_OFFSET 0x100
-#endif
#ifndef _DEFINE_VARS
#define __global externC
#else
#define __global
#endif
__global cyg_uint32 _plx_config_addr;
__global cyg_uint32 _plx_localbus_addr;
#undef __global
-#if 0
-#define plx_config_readl(a) (*(volatile cyg_uint32 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_CONFIG_OFFSET + (a)))
-#define plx_config_writel(v,a) (*(volatile cyg_uint32 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_CONFIG_OFFSET + (a)))=(v)
-
-#define localbus_readb(a) (*(volatile cyg_uint8 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_OFFSET + (a)))
-#define localbus_readw(a) (*(volatile cyg_uint16 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_OFFSET + (a)))
-#define localbus_readl(a) (*(volatile cyg_uint32 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_OFFSET + (a)))
-#define localbus_writeb(v,a) (*(volatile cyg_uint8 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_OFFSET + (a)))=(v)
-#define localbus_writew(v,a) (*(volatile cyg_uint16 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_OFFSET + (a)))=(v)
-#define localbus_writel(v,a) (*(volatile cyg_uint32 *)(PCI_MEM_BASE + LOCALBUS_MEM_BASE + LOCALBUS_OFFSET + (a)))=(v)
-#else
#define plx_config_readl(a) (*(volatile cyg_uint32 *)(_plx_config_addr + (a)))
#define plx_config_writel(v,a) (*(volatile cyg_uint32 *)(_plx_config_addr + (a)))=(v)
#define localbus_readb(a) (*(volatile cyg_uint8 *)(_plx_localbus_addr + (a)))
#define localbus_readw(a) (*(volatile cyg_uint16 *)(_plx_localbus_addr + (a)))
#define localbus_readl(a) (*(volatile cyg_uint32 *)(_plx_localbus_addr + (a)))
#define localbus_writeb(v,a) (*(volatile cyg_uint8 *)(_plx_localbus_addr + (a)))=(v)
#define localbus_writew(v,a) (*(volatile cyg_uint16 *)(_plx_localbus_addr + (a)))=(v)
#define localbus_writel(v,a) (*(volatile cyg_uint32 *)(_plx_localbus_addr + (a)))=(v)
-#endif
#define display_readb(a) (*(volatile cyg_uint8 *)(PCI_MEM_BASE2 + DISPLAY_MEM_BASE + (a)))
#define display_readw(a) (*(volatile cyg_uint16 *)(PCI_MEM_BASE2 + DISPLAY_MEM_BASE + (a)))
#define display_readl(a) (*(volatile cyg_uint32 *)(PCI_MEM_BASE2 + DISPLAY_MEM_BASE + (a)))
#define display_writeb(v,a) (*(volatile cyg_uint8 *)(PCI_MEM_BASE2 + DISPLAY_MEM_BASE + (a)))=(v)
Index: hal/arm/xscale/uE250/current/src/uE250_misc.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/src/uE250_misc.c,v
retrieving revision 1.1
diff -u -5 -p -b -r1.1 uE250_misc.c
--- hal/arm/xscale/uE250/current/src/uE250_misc.c 21 Feb 2003 18:17:33 -0000 1.1
+++ hal/arm/xscale/uE250/current/src/uE250_misc.c 24 Feb 2003 18:05:13 -0000
@@ -131,10 +131,16 @@ plf_hardware_init(void)
#endif // ! CYG_HAL_STARTUP_ROM - RAM start only
hal_if_init();
cyg_hal_plf_pci_init();
+ // Set up to handle PCI interrupts
+ HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_GPIO1, 0, 0); // Falling edge
+ HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GPIO1);
+ PCICTL_INT_RESET = 0xFF; // Clear all pending interrupts
+ PCICTL_INT_EDGE = 0xFF; // Generate interrupts
+ PCICTL_IRQ_MASK = 0x00; // All masked
initialize_plx_bridge();
}
//
@@ -164,8 +170,68 @@ hal_arm_mem_real_region_top( cyg_uint8 *
regionend = (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size;
}
#endif
return regionend;
}
+
+// ------------------------------------------------------------------------
+// Extended, platform-specific, interrupt handling
+
+// FIXME - still needs work to support interrupts from PXA bridge
+
+int
+_uE250_extended_irq(void)
+{
+ cyg_uint32 stat = PCICTL_STATUS_REG;
+ int irq = 0;
+
+ if (stat & 0x1F0) {
+ PCICTL_INT_RESET = 0xFF; // Clear all pending interrupts
+ }
+ if (stat & 0x00F) {
+ // PCI interrupt
+ for (irq = 0; irq < 4; irq++) {
+ if ((stat & (1 << irq)) != 0) {
+ break;
+ }
+ }
+ irq += _uPCI_BASE_INTERRUPT;
+ }
+ HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_GPIO1);
+ PCICTL_INT_EDGE = 0xFF; // Generate interrupts
+ return irq;
+}
+
+void
+_uE250_extended_int_mask(int vector)
+{
+ if (vector <= CYGNUM_HAL_INTERRUPT_PCI_INTD) {
+ PCICTL_IRQ_MASK &= ~(1<<(vector-CYGNUM_HAL_INTERRUPT_PCI_INTA));
+ }
+}
+
+void
+_uE250_extended_int_unmask(int vector)
+{
+ if (vector <= CYGNUM_HAL_INTERRUPT_PCI_INTD) {
+ PCICTL_IRQ_MASK |= (1<<(vector-CYGNUM_HAL_INTERRUPT_PCI_INTA));
+ }
+}
+
+void
+_uE250_extended_int_acknowledge(int vector)
+{
+}
+
+void
+_uE250_extended_int_configure(int vector, int level, int up)
+{
+}
+
+void
+_uE250_extended_int_set_level(int vector, int level)
+{
+}
+
// ------------------------------------------------------------------------
// EOF uE250_misc.c
Index: hal/arm/xscale/uE250/current/src/uE250_pci.c
===================================================================
RCS file: /misc/cvsfiles/ecos/packages/hal/arm/xscale/uE250/current/src/uE250_pci.c,v
retrieving revision 1.1
diff -u -5 -p -b -r1.1 uE250_pci.c
--- hal/arm/xscale/uE250/current/src/uE250_pci.c 21 Feb 2003 18:17:33 -0000 1.1
+++ hal/arm/xscale/uE250/current/src/uE250_pci.c 24 Feb 2003 17:44:02 -0000
@@ -149,11 +149,20 @@ cyg_hal_plf_pci_init(void)
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
+}
+void
+_uE250_pci_translate_interrupt(int bus, int devfn, int *vector, int *valid)
+{
+ int dev = CYG_PCI_DEV_GET_DEV(devfn);
+
+ *vector = _uPCI_BASE_INTERRUPT+(dev-1);
+ diag_printf("%s.%d - dev: %d = %d\n", __FUNCTION__, __LINE__, dev, *vector);
+ valid = true;;
}
static void
cyg_hal_plf_pci_clear_idsel(void)
{
--
------------------------------------------------------------
Gary Thomas |
MLB Associates | Consulting for the
+1 (970) 229-1963 | Embedded world
http://www.mlbassoc.com/ |
email: <gary at mlbassoc dot com> |
gpg: http://www.chez-thomas.org/gary/gpg_key.asc
------------------------------------------------------------