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new XScale ports (IXP425 based)


? devs/eth/arm/grg
? devs/eth/arm/ixdp425
? devs/flash/arm/grg
? devs/flash/arm/ixdp425
? hal/arm/xscale/grg
? hal/arm/xscale/ixdp425
? hal/arm/xscale/ixp425
Index: ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/ChangeLog,v
retrieving revision 1.102
diff -u -p -5 -r1.102 ChangeLog
--- ChangeLog	5 Mar 2003 16:41:26 -0000	1.102
+++ ChangeLog	18 Mar 2003 12:54:22 -0000
@@ -1,5 +1,9 @@
+2003-03-18  Mark Salter  <msalter at redhat dot com>
+
+        * ecos.db: Add support for XScale IXP425, IXDP425, GRG.
+
 2003-03-05  John Dallaway  <jld at ecoscentric dot com>
 
 	* ecosadmin.tcl: Prevent calls to 'cygpath' with an empty
 	path argument.
 
Index: NEWS
===================================================================
RCS file: /cvs/ecos/ecos/packages/NEWS,v
retrieving revision 1.67
diff -u -p -5 -r1.67 NEWS
--- NEWS	28 Feb 2003 09:26:02 -0000	1.67
+++ NEWS	18 Mar 2003 12:54:24 -0000
@@ -1,5 +1,7 @@
+* New ports for Intel XScale IXP425 boards (IXDP425 and Generic Residential
+  Gateway).
 * SNMP code now works with the FreeBSD stack
 * Simple Network Time Protocol (SNTP) client contributed by Andrew Lunn.
 * Added port for NMI uE250 (ARM Xscale PXA250) platform, contributed 
   by Mind, NV.
 * Port added for IDT MIPS IDT79RC32334 reference platform, including Flash,
Index: ecos.db
===================================================================
RCS file: /cvs/ecos/ecos/packages/ecos.db,v
retrieving revision 1.91
diff -u -p -5 -r1.91 ecos.db
--- ecos.db	25 Feb 2003 14:40:23 -0000	1.91
+++ ecos.db	18 Mar 2003 12:54:28 -0000
@@ -460,10 +460,30 @@ package CYGPKG_DEVS_FLASH_IQ80321 {
         description "
            This package contains hardware support for FLASH memory
 	   on the IQ80321 platform."
 }
 
+package CYGPKG_DEVS_FLASH_IXDP425 {
+	alias 		{ "FLASH memory support for IXDP425" flash_ixdp425 }
+	directory	devs/flash/arm/ixdp425
+	script		flash_ixdp425.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the IXDP425 platform."
+}
+
+package CYGPKG_DEVS_FLASH_GRG {
+	alias 		{ "FLASH memory support for GRG" flash_grg }
+	directory	devs/flash/arm/grg
+	script		flash_grg.cdl
+	hardware
+        description "
+           This package contains hardware support for FLASH memory
+	   on the Intel Generic Residential Gateway platform."
+}
+
 package CYGPKG_DEVS_FLASH_ARM_INTEGRATOR {
         alias           { "FLASH memory support for ARM INTEGRATOR" flash_integrator }
         directory       devs/flash/arm/integrator
         script          flash_integrator.cdl
         hardware
@@ -1391,10 +1411,28 @@ package CYGPKG_DEVS_ETH_ARM_XSCALE_IQ803
 	directory	devs/eth/arm/iq80310
 	script		iq80310_eth_drivers.cdl
         description     "Ethernet driver for Intel IQ80310 with onboard 82559 NIC."
 }
 
+package CYGPKG_DEVS_ETH_ARM_IXDP425_I82559 {
+	alias 		{ "IXDP425 (PCI) / Intel 82559 ethernet driver"
+			   devs_eth_arm_ixdp425_i82559 }
+	hardware
+	directory	devs/eth/arm/ixdp425/i82559
+	script		ixdp425_i82559_eth_driver.cdl
+        description     "Ethernet driver for IXDP425 with Intel 82559 PCI NIC."
+}
+
+package CYGPKG_DEVS_ETH_ARM_GRG_I82559 {
+	alias 		{ "GRG / Intel 82559 ethernet driver"
+			   devs_eth_arm_grg_i82559 }
+	hardware
+	directory	devs/eth/arm/grg/i82559
+	script		grg_i82559_eth_driver.cdl
+        description     "Ethernet driver for GRG with Intel 82559 PCI NIC."
+}
+
 package CYGPKG_DEVS_ETH_I386_PC_I82559 {
 	alias 		{ "Standard PC with EtherPro 10/100 ethernet device"
 			   devs_eth_i386_pc_i82559 pc_etherpro }
 	hardware
 	directory	devs/eth/i386/pc/i82559
@@ -2251,10 +2289,40 @@ package CYGPKG_HAL_ARM_XSCALE_IQ80321 {
         description "
         The IQ80321 HAL package provides the support needed to run
         eCos on an Intel XScale IQ80321 evaluation board."
 }
 
+package CYGPKG_HAL_ARM_XSCALE_IXP425 {
+	alias		{ "Intel XScale IXP425 Network Processor" hal_arm_xscale_ixp425 }
+	directory	hal/arm/xscale/ixp425
+	script		hal_arm_xscale_ixp425.cdl
+	hardware
+        description "
+        The XScale IXP425 HAL package provides the support needed to run
+        eCos on Intel XScale IXP425 network processor based systems."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_IXDP425 {
+	alias		{ "Intel XScale IXDP425 Network Processor eval board" hal_arm_xscale_ixdp425 }
+	directory	hal/arm/xscale/ixdp425
+	script		hal_arm_xscale_ixdp425.cdl
+	hardware
+        description "
+        The IXDP425 HAL package provides the support needed to run
+        eCos on an Intel XScale IXDP425 network processor evaluation board."
+}
+
+package CYGPKG_HAL_ARM_XSCALE_GRG {
+	alias		{ "Intel XScale Generic Residential Gateway" hal_arm_xscale_grg }
+	directory	hal/arm/xscale/grg
+	script		hal_arm_xscale_grg.cdl
+	hardware
+        description "
+        The GRG HAL package provides the support needed to run eCos on an
+        Intel Generic Residential Gateway evaluation board."
+}
+
 package CYGPKG_HAL_ARM_XSCALE_PXA2X0 {
 	alias		{ "Intel PXA2X0" hal_arm_xscale_pxa2x0 }
 	directory	hal/arm/xscale/pxa2x0
 	script		hal_arm_xscale_pxa2x0.cdl
 	hardware
@@ -3629,10 +3697,44 @@ target iq80321 {
                    CYGPKG_DEVS_ETH_ARM_IQ80321
         }
         description "
         The IQ80321 target provides the packages needed to run
         eCos on an Intel XScale IQ80321 board."
+}
+
+target ixdp425 {
+	alias { "IXDP425 board" ixdp425 }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+	           CYGPKG_HAL_ARM_XSCALE_IXP425
+                   CYGPKG_HAL_ARM_XSCALE_IXDP425
+		   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+		   CYGPKG_DEVS_ETH_ARM_IXDP425_I82559
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_IXDP425
+        }
+        description "
+        The ixdp425 target provides the packages needed to run
+        eCos on an Intel network processor evaluation board."
+}
+
+target grg {
+	alias { "Generic Residential Gateway" grg }
+	packages { CYGPKG_HAL_ARM
+                   CYGPKG_HAL_ARM_XSCALE_CORE
+	           CYGPKG_HAL_ARM_XSCALE_IXP425
+                   CYGPKG_HAL_ARM_XSCALE_GRG
+		   CYGPKG_IO_PCI
+                   CYGPKG_DEVS_ETH_INTEL_I82559
+                   CYGPKG_DEVS_ETH_ARM_GRG_I82559
+                   CYGPKG_DEVS_FLASH_STRATA
+		   CYGPKG_DEVS_FLASH_GRG
+        }
+        description "
+        The grg target provides the packages needed to run
+        eCos on an Intel Generic Residential Gateway board."
 }
 
 target edb7xxx {
         alias		{ "Cirrus Logic EDB7xxx development board" edb7211 eb7xxx eb7211 }
 	packages	{ CYGPKG_HAL_ARM
Index: redboot/current/ChangeLog
===================================================================
RCS file: /cvs/ecos/ecos/packages/redboot/current/ChangeLog,v
retrieving revision 1.95
diff -u -p -5 -r1.95 ChangeLog
--- redboot/current/ChangeLog	5 Mar 2003 01:46:29 -0000	1.95
+++ redboot/current/ChangeLog	18 Mar 2003 12:55:22 -0000
@@ -1,5 +1,9 @@
+2003-03-18  Mark Salter  <msalter at redhat dot com>
+
+	* doc/redboot_installing.sgml: Add XScale IXDP425 and GRG.
+
 2003-03-05  Jonathan Larmour  <jifl at eCosCentric dot com>
 
 	* src/main.c (do_version): Test for CYGPKG_REDBOOT_FLASH as
 	CYGPKG_IO_FLASH can be loaded with no underlying hardware drivers!
 
Index: redboot/current/doc/redboot_installing.sgml
===================================================================
RCS file: /cvs/ecos/ecos/packages/redboot/current/doc/redboot_installing.sgml,v
retrieving revision 1.6
diff -u -p -5 -r1.6 redboot_installing.sgml
--- redboot/current/doc/redboot_installing.sgml	14 Feb 2003 02:49:07 -0000	1.6
+++ redboot/current/doc/redboot_installing.sgml	18 Mar 2003 12:55:27 -0000
@@ -8,11 +8,11 @@
 <!--                                                                 -->
 <!-- =============================================================== -->
 <!-- ####COPYRIGHTBEGIN####                                          -->
 <!--                                                                 -->
 <!-- =============================================================== -->
-<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.  -->
+<!-- Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.  -->
 <!-- This material may be distributed only subject to the terms      -->
 <!-- and conditions set forth in the Open Publication License, v1.0  -->
 <!-- or later (the latest version is presently available at          -->
 <!-- http://www.opencontent.org/openpub/)                            -->
 <!-- Distribution of the work or derivative of the work in any       -->
@@ -2802,11 +2802,11 @@ description of the associated modes.</pa
 
 </sect2></sect1>
 
 
 <sect1 id="iq80310">
-<title>ARM/Xscale Cyclone IQ80310</title>
+<title>ARM/XScale Cyclone IQ80310</title>
 <sect2>
 <title>Overview</title>
 <para><indexterm><primary>Cyclone IQ80310</primary><secondary>installing and
 testing</secondary></indexterm><indexterm><primary>installing and testing
 </primary><secondary>Cyclone IQ80310</secondary></indexterm>RedBoot supports
@@ -3143,11 +3143,11 @@ Virtual Address Range    C B  Descriptio
 for networking and XModem file transfers.</para>
 </sect2></sect1>
 
 <?Pub _newpage>
 <sect1 id="iq80321">
-<title>ARM/Xscale Intel IQ80321</title>
+<title>ARM/XScale Intel IQ80321</title>
 <sect2>
 <title>Overview</title>
 <para><indexterm><primary>Intel IQ80321</primary><secondary>installing and
 testing</secondary></indexterm><indexterm><primary>installing and testing
 </primary><secondary>Intel IQ80321</secondary></indexterm>RedBoot supports
@@ -3624,10 +3624,378 @@ Alternate Virtual Map    X C B  Descript
 <sect2>
 <title>Platform Resource Usage</title>
 <para>The Verde programmable timer0 is used for timeout support
 for networking and XModem file transfers.</para>
 </sect2></sect1>
+
+<?Pub _newpage>
+<sect1 id="IXDP425">
+<title>ARM/Intel XScale IXDP425 Network Processor Evaluation Board</title>
+<sect2>
+<title>Overview</title>
+<para><indexterm><primary>Intel IXDP425</primary><secondary>installing and
+testing</secondary></indexterm><indexterm><primary>installing and testing
+</primary><secondary>Intel IXDP</secondary></indexterm>RedBoot supports
+the builtin high-speed and console UARTs and a PCI based i82559 ethernet
+card for communication and downloads. The default serial port settings are
+115200,8,N,1. RedBoot also supports flash management for the 16MB boot flash
+on the mainboard.</para>
+
+<para>The following RedBoot configurations are supported:
+
+      <informaltable frame="all">
+	<tgroup cols="4" colsep="1" rowsep="1" align="left">
+	  <thead>
+	    <row>
+	      <entry>Configuration</entry>
+	      <entry>Mode</entry>
+	      <entry>Description</entry>
+	      <entry>File</entry>
+	    </row>
+	  </thead>
+	  <tbody>
+	    <row>
+	      <entry>ROM</entry>
+	      <entry>[ROM]</entry>
+	      <entry>RedBoot running from flash
+	      sector.</entry>
+	      <entry>redboot_ROM.ecm</entry>
+	    </row>
+	    <row>
+	      <entry>RAM</entry>
+	      <entry>[RAM]</entry>
+	      <entry>RedBoot running from RAM with RedBoot in the
+	      flash boot sector.</entry>
+	      <entry>redboot_RAM.ecm</entry>
+	    </row>
+</tbody>
+</tgroup>
+</informaltable>
+</para>
+
+</sect2>
+<sect2>
+<title>Initial Installation Method</title>
+<para>The IXDP425 flash is socketed, so initial installation may be done using
+an appropriate device programmer. JTAG based initial may also be used. In either
+case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000.
+</para>
+
+<para>After booting the initial installation of RedBoot, this warning may
+be printed: <screen>flash configuration checksum error or invalid key
+</screen>This is normal, and indicates that the flash should be configured
+for use by RedBoot. See <xref linkend="Persistent-State-Flash"> for more
+details.
+</para></sect2>
+<sect2>
+<title>LED Codes</title>
+<para>RedBoot uses the 4 digit LED display to indicate status during board
+initialization. Possible codes are:</para>
+
+<literallayout width=72>
+LED     Actions
+-------------------------------------------------------------
+  	Power-On/Reset
+        Set the CPSR
+        Enable coprocessor access
+        Drain write and fill buffer
+        Setup expansion bus chip selects
+1001
+        Enable Icache
+1002
+        Initialize SDRAM controller
+1003
+        Switch flash (CS0) from 0x00000000 to 0x50000000
+1004
+        Copy MMU table to RAM
+1005
+        Setup TTB and domain permissions
+1006
+        Enable MMU
+1007
+        Enable DCache
+1008
+        Enable branch target buffer
+1009
+        Drain write and fill buffer
+        Flush caches
+100A
+        Start up the eCos kernel or RedBoot
+0001
+
+</literallayout>
+</sect2>
+<sect2>
+<title>Rebuilding RedBoot </title>
+
+<para>These shell variables provide the platform-specific information
+needed for building RedBoot according to the procedure described in
+<xref linkend="Rebuilding-Redboot">:
+<programlisting>
+export TARGET=ixdp425
+export ARCH_DIR=arm
+export PLATFORM_DIR=xscale/ixdp425
+</programlisting>
+</para>
+
+<para>The names of configuration files are listed above with the
+description of the associated modes.</para>
+</sect2>
+
+<sect2>
+<title>Interrupts</title>
+<para>RedBoot uses an interrupt vector table which is located at address 0x8004.
+Entries in this table are pointers to functions with this protoype::      <programlisting>
+int irq_handler( unsigned vector, unsigned data )</programlisting>On the Mainstone
+board, the vector argument is one of many interrupts defined in <computeroutput>
+hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</computeroutput>:   <programlisting>
+#define CYGNUM_HAL_INTERRUPT_NPEA         0
+#define CYGNUM_HAL_INTERRUPT_NPEB         1
+#define CYGNUM_HAL_INTERRUPT_NPEC         2
+#define CYGNUM_HAL_INTERRUPT_QM1          3
+#define CYGNUM_HAL_INTERRUPT_QM2          4
+#define CYGNUM_HAL_INTERRUPT_TIMER0       5
+#define CYGNUM_HAL_INTERRUPT_GPIO0        6
+#define CYGNUM_HAL_INTERRUPT_GPIO1        7
+#define CYGNUM_HAL_INTERRUPT_PCI_INT      8
+#define CYGNUM_HAL_INTERRUPT_PCI_DMA1     9
+#define CYGNUM_HAL_INTERRUPT_PCI_DMA2     10
+#define CYGNUM_HAL_INTERRUPT_TIMER1       11
+#define CYGNUM_HAL_INTERRUPT_USB          12
+#define CYGNUM_HAL_INTERRUPT_UART2        13
+#define CYGNUM_HAL_INTERRUPT_TIMESTAMP    14
+#define CYGNUM_HAL_INTERRUPT_UART1        15
+#define CYGNUM_HAL_INTERRUPT_WDOG         16
+#define CYGNUM_HAL_INTERRUPT_AHB_PMU      17
+#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU   18
+#define CYGNUM_HAL_INTERRUPT_GPIO2        19
+#define CYGNUM_HAL_INTERRUPT_GPIO3        20
+#define CYGNUM_HAL_INTERRUPT_GPIO4        21
+#define CYGNUM_HAL_INTERRUPT_GPIO5        22
+#define CYGNUM_HAL_INTERRUPT_GPIO6        23
+#define CYGNUM_HAL_INTERRUPT_GPIO7        24
+#define CYGNUM_HAL_INTERRUPT_GPIO8        25
+#define CYGNUM_HAL_INTERRUPT_GPIO9        26
+#define CYGNUM_HAL_INTERRUPT_GPIO10       27
+#define CYGNUM_HAL_INTERRUPT_GPIO11       28           
+#define CYGNUM_HAL_INTERRUPT_GPIO12       29
+#define CYGNUM_HAL_INTERRUPT_SW_INT1      30
+#define CYGNUM_HAL_INTERRUPT_SW_INT2      31
+</programlisting>
+The data passed to the ISR is pulled from a data table <computeroutput>(hal_interrupt_data)
+</computeroutput> which immediately follows the interrupt vector table. With
+32 interrupts, the data table starts at address 0x8084.   </para>
+<para>An application may create a normal C function with the above prototype
+to be an ISR. Just poke its address into the table at the correct index and
+enable the interrupt at its source. The return value of the ISR is ignored
+by RedBoot.</para>
+</sect2>
+<sect2>
+<title>Memory Maps</title>
+<para>The RAM based page table is located at RAM start + 0x4000.
+<note><title>NOTE</title>
+<para>The virtual memory maps in this section use a C, B, and X column to indicate
+the caching policy for the region..</para>
+</note></para>
+<para><programlisting>
+X C B  Description
+- - -  ---------------------------------------------
+0 0 0  Uncached/Unbuffered
+0 0 1  Uncached/Buffered
+0 1 0  Cached/Buffered    Write Through, Read Allocate
+0 1 1  Cached/Buffered    Write Back, Read Allocate
+1 0 0  Invalid -- not used
+1 0 1  Uncached/Buffered  No write buffer coalescing
+1 1 0  Mini DCache - Policy set by Aux Ctl Register
+1 1 1  Cached/Buffered    Write Back, Read/Write Allocate
+
+Virtual Address   Physical Address  XCB  Size (MB)  Description
+---------------   ----------------  ---  ---------  -----------
+   0x00000000       0x00000000      010     256     SDRAM (cached)
+   0x10000000       0x10000000      010     256     SDRAM (alias)
+   0x20000000       0x00000000      000     256     SDRAM (uncached)
+   0x48000000       0x48000000      000      64     PCI Data
+   0x50000000       0x50000000      010      16     Flash (CS0)
+   0x51000000       0x51000000      000     112     CS1 - CS7
+   0x60000000       0x60000000      000      64     Queue Manager
+   0xC0000000       0xC0000000      000       1     PCI Controller
+   0xC4000000       0xC4000000      000       1     Exp. Bus Config
+   0xC8000000       0xC8000000      000       1     Misc IXP425 IO
+   0xCC000000       0xCC000000      000       1     SDRAM Config
+
+</programlisting></para>
+</sect2>
+<sect2>
+<title>Platform Resource Usage</title>
+<para>The IXP425 programmable OStimer0 is used for timeout support
+for networking and XModem file transfers.</para>
+</sect2></sect1>
+
+<?Pub _newpage>
+<sect1 id="GRG">
+<title>ARM/Intel XScale Generic Residential Gateway</title>
+<sect2>
+<title>Overview</title>
+<para><indexterm><primary>Intel GRG</primary><secondary>installing and
+testing</secondary></indexterm><indexterm><primary>installing and testing
+</primary><secondary>Intel GRG</secondary></indexterm>RedBoot supports
+the console UART and a PCI based i82559 ethernet card for communication
+and downloads. The default serial port settings are 115200,8,N,1. RedBoot
+also supports flash management for the 16MB onboard flash.</para>
+
+<para>The following RedBoot configurations are supported:
+
+      <informaltable frame="all">
+	<tgroup cols="4" colsep="1" rowsep="1" align="left">
+	  <thead>
+	    <row>
+	      <entry>Configuration</entry>
+	      <entry>Mode</entry>
+	      <entry>Description</entry>
+	      <entry>File</entry>
+	    </row>
+	  </thead>
+	  <tbody>
+	    <row>
+	      <entry>ROM</entry>
+	      <entry>[ROM]</entry>
+	      <entry>RedBoot running from flash
+	      sector.</entry>
+	      <entry>redboot_ROM.ecm</entry>
+	    </row>
+	    <row>
+	      <entry>RAM</entry>
+	      <entry>[RAM]</entry>
+	      <entry>RedBoot running from RAM with RedBoot in the
+	      flash boot sector.</entry>
+	      <entry>redboot_RAM.ecm</entry>
+	    </row>
+</tbody>
+</tgroup>
+</informaltable>
+</para>
+
+</sect2>
+<sect2>
+<title>Initial Installation Method</title>
+<para>The GRG flash is socketed, so initial installation may be done using
+an appropriate device programmer. JTAG based initial may also be used. In either
+case, the ROM mode RedBoot is programmed into the boot flash at address 0x00000000.
+</para>
+
+<para>After booting the initial installation of RedBoot, this warning may
+be printed: <screen>flash configuration checksum error or invalid key
+</screen>This is normal, and indicates that the flash should be configured
+for use by RedBoot. See <xref linkend="Persistent-State-Flash"> for more
+details.
+</para></sect2>
+<sect2>
+<title>Rebuilding RedBoot </title>
+
+<para>These shell variables provide the platform-specific information
+needed for building RedBoot according to the procedure described in
+<xref linkend="Rebuilding-Redboot">:
+<programlisting>
+export TARGET=grg
+export ARCH_DIR=arm
+export PLATFORM_DIR=xscale/grg
+</programlisting>
+</para>
+
+<para>The names of configuration files are listed above with the
+description of the associated modes.</para>
+</sect2>
+
+<sect2>
+<title>Interrupts</title>
+<para>RedBoot uses an interrupt vector table which is located at address 0x8004.
+Entries in this table are pointers to functions with this protoype::      <programlisting>
+int irq_handler( unsigned vector, unsigned data )</programlisting>On the Mainstone
+board, the vector argument is one of many interrupts defined in <computeroutput>
+hal/arm/xscale/ixp425/current/include/hal_var_ints.h:</computeroutput>:   <programlisting>
+#define CYGNUM_HAL_INTERRUPT_NPEA         0
+#define CYGNUM_HAL_INTERRUPT_NPEB         1
+#define CYGNUM_HAL_INTERRUPT_NPEC         2
+#define CYGNUM_HAL_INTERRUPT_QM1          3
+#define CYGNUM_HAL_INTERRUPT_QM2          4
+#define CYGNUM_HAL_INTERRUPT_TIMER0       5
+#define CYGNUM_HAL_INTERRUPT_GPIO0        6
+#define CYGNUM_HAL_INTERRUPT_GPIO1        7
+#define CYGNUM_HAL_INTERRUPT_PCI_INT      8
+#define CYGNUM_HAL_INTERRUPT_PCI_DMA1     9
+#define CYGNUM_HAL_INTERRUPT_PCI_DMA2     10
+#define CYGNUM_HAL_INTERRUPT_TIMER1       11
+#define CYGNUM_HAL_INTERRUPT_USB          12
+#define CYGNUM_HAL_INTERRUPT_UART2        13
+#define CYGNUM_HAL_INTERRUPT_TIMESTAMP    14
+#define CYGNUM_HAL_INTERRUPT_UART1        15
+#define CYGNUM_HAL_INTERRUPT_WDOG         16
+#define CYGNUM_HAL_INTERRUPT_AHB_PMU      17
+#define CYGNUM_HAL_INTERRUPT_XSCALE_PMU   18
+#define CYGNUM_HAL_INTERRUPT_GPIO2        19
+#define CYGNUM_HAL_INTERRUPT_GPIO3        20
+#define CYGNUM_HAL_INTERRUPT_GPIO4        21
+#define CYGNUM_HAL_INTERRUPT_GPIO5        22
+#define CYGNUM_HAL_INTERRUPT_GPIO6        23
+#define CYGNUM_HAL_INTERRUPT_GPIO7        24
+#define CYGNUM_HAL_INTERRUPT_GPIO8        25
+#define CYGNUM_HAL_INTERRUPT_GPIO9        26
+#define CYGNUM_HAL_INTERRUPT_GPIO10       27
+#define CYGNUM_HAL_INTERRUPT_GPIO11       28           
+#define CYGNUM_HAL_INTERRUPT_GPIO12       29
+#define CYGNUM_HAL_INTERRUPT_SW_INT1      30
+#define CYGNUM_HAL_INTERRUPT_SW_INT2      31
+</programlisting>
+The data passed to the ISR is pulled from a data table <computeroutput>(hal_interrupt_data)
+</computeroutput> which immediately follows the interrupt vector table. With
+32 interrupts, the data table starts at address 0x8084.   </para>
+<para>An application may create a normal C function with the above prototype
+to be an ISR. Just poke its address into the table at the correct index and
+enable the interrupt at its source. The return value of the ISR is ignored
+by RedBoot.</para>
+</sect2>
+<sect2>
+<title>Memory Maps</title>
+<para>The RAM based page table is located at RAM start + 0x4000.
+<note><title>NOTE</title>
+<para>The virtual memory maps in this section use a C, B, and X column to indicate
+the caching policy for the region..</para>
+</note></para>
+<para><programlisting>
+X C B  Description
+- - -  ---------------------------------------------
+0 0 0  Uncached/Unbuffered
+0 0 1  Uncached/Buffered
+0 1 0  Cached/Buffered    Write Through, Read Allocate
+0 1 1  Cached/Buffered    Write Back, Read Allocate
+1 0 0  Invalid -- not used
+1 0 1  Uncached/Buffered  No write buffer coalescing
+1 1 0  Mini DCache - Policy set by Aux Ctl Register
+1 1 1  Cached/Buffered    Write Back, Read/Write Allocate
+
+Virtual Address   Physical Address  XCB  Size (MB)  Description
+---------------   ----------------  ---  ---------  -----------
+   0x00000000       0x00000000      010      32     SDRAM (cached)
+   0x10000000       0x00000000      010      32     SDRAM (alias)
+   0x20000000       0x00000000      000      32     SDRAM (uncached)
+   0x48000000       0x48000000      000      64     PCI Data
+   0x50000000       0x50000000      010      16     Flash (CS0)
+   0x51000000       0x51000000      000     112     CS1 - CS7
+   0x60000000       0x60000000      000      64     Queue Manager
+   0xC0000000       0xC0000000      000       1     PCI Controller
+   0xC4000000       0xC4000000      000       1     Exp. Bus Config
+   0xC8000000       0xC8000000      000       1     Misc IXP425 IO
+   0xCC000000       0xCC000000      000       1     SDRAM Config
+
+</programlisting></para>
+</sect2>
+<sect2>
+<title>Platform Resource Usage</title>
+<para>The IXP425 programmable OStimer0 is used for timeout support
+for networking and XModem file transfers.</para>
+</sect2></sect1>
+
 
 <!-- ********************** CalmRISC ********************** -->
 <?Pub _newpage>
 <sect1 id="CalmRISC16">
 <title>CalmRISC/CalmRISC16 Samsung CalmRISC16 Core Evaluation Board </title>


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